CN101777614A

CN101777614A - Method for manufacturing low-dislocation-density light-emitting diode (LED) chip

Info

Publication number: CN101777614A
Application number: CN201010033353A
Authority: CN
Inventors: 伍永安; 高绍兵
Original assignee: SHANXI LEBAI LITE TECHNOLOGY Co Ltd
Current assignee: SHANXI LEBAI LITE TECHNOLOGY Co Ltd
Priority date: 2010-01-05
Filing date: 2010-01-05
Publication date: 2010-07-14

Abstract

The invention discloses a method for manufacturing a low-dislocation-density light-emitting diode (LED) chip, which belongs to the technical field of the manufacture of LED chips. The invention provides a method for manufacturing an LED chip which can reduce the dislocation density. The method for manufacturing the low-dislocation-density LED chip comprises the following steps of: 1. growing a GaN buffer layer on a C surface sapphire substrate; 2. evaporating and plating a transparent N type electrode on the GaN buffer layer; 3. evaporating and plating Ni, Ag, Ti and Au on the N type electrode layer by layer to form a reflecting layer; 4. growing a metal layer with the thickness of not smaller than 50 microns on the reflecting layer; manufacturing the metal layer into an even and periodic metal heat sink unit layer by utilizing a dry etching technology in an interval of 100-200 microns; 5. epitaxially growing an N type GaN layer on the metal heat sink unit layer; 6. growing an active layer on the N type GaN layer and adopting quaternary AlInGaN as a multiquantum well layer material; 7. growing a P type GaN layer on the active layer; and 8. growing a P type electrode on the P type GaN layer. The invention is applied to the field of the design and manufacture of the LED chips.

Description

The preparation method of low-dislocation-density led chip

Technical field

The preparation method of low-dislocation-density led chip of the present invention belongs to led chip manufacturing technology field.

Background technology

In recent years, with GaN and SiC is that the third generation semiconductor material with wide forbidden band of representative is subjected to people's extensive concern and research energetically, especially III-V hi-nitride semiconductor material and alloy and the heterojunction material relevant with them have very big advantage aspect high temperature, the high-frequency high-power device.

Can at present, the bluish-green LED of high brightness succeeds in developing, but the existence of high threading dislocation density has limited the further raising of these device performances, therefore make a breakthrough aspect the high performance LED of realization, and it is most important to reduce the GaN dislocation density.

The GaN base semiconductor has some major defects, its GaN base LED dislocation density 10 ⁸-10 ¹⁰Cm ^-2And the internal quantum efficiency of GaN base LED mainly is subjected in dislocation density, the Multiple Quantum Well piezoelectric field to close quantum well transverse shapes etc. to be influenced, and increases the internal quantum efficiency of LED to greatest extent by reducing dislocation density and polarity effect.

Have very big lattice mismatch and thermal mismatching between GaN and the sapphire, the resilient coating of grow on substrate earlier usually lattice constant gradual change or sudden change is then at epitaxial growth GaN.Although the resilient coating technology is very ripe, the GaN film that obtains with this technology growth still has very high dislocation density, and is very big to the device performance influence.

The early stage epitaxial lateral overgrowth technology that adopts at first is the certain thickness GaN interruption of growth afterwards of growing on Sapphire Substrate, and sample is taken out from reative cell, and preparation has periodic mask pattern on GaN again, adopts SiO ₂As mask material, then sample is put back to the reative cell continued growth, until the film that obtains surfacing.The characteristics of this technology are to need to be interrupted growth, are unfavorable for saving time, and reduce cost, and sample is carried out mask process from the reative cell taking-up, inevitably sample are polluted

Summary of the invention

For overcoming the deficiencies in the prior art, the invention provides a kind of manufacture method of energy lowering dislocation density led chip.

For solving the problems of the technologies described above, the technical solution used in the present invention is: the preparation method of low-dislocation-density led chip may further comprise the steps:

The first step, growing GaN resilient coating on the C surface sapphire substrate;

Second step, the N type electrode that evaporation is transparent on the GaN resilient coating;

In the 3rd step, successively evaporation Ni, Ag, Ti, Au form the reflector on N type electrode;

In the 4th step, growth one layer thickness is not less than the metal level of 50 μ m on the reflector; Utilize dry etching technology that this layer metal level is prepared into smooth, periodic metal heat sink elementary layer, 100-200 μ m at interval;

The 5th step, epitaxial growth N type GaN layer on the metal heat sink elementary layer;

In the 6th step, the active layer of growing on N type GaN layer adopts quaternary AlInGaN as the Multiple Quantum Well layer material;

The 7th step, growth P-type GaN layer on active layer;

The 8th step, growing P-type electrode on P type GaN layer.

Described reflector gross thickness interconnects to each other at 100-200nm, forms conductive network.

The thickness of described metal heat sink elementary layer is 50 μ m.

Handle P type GaN laminar surface with CF4, P type GaN laminar surface successively evaporation Ti, Al, Ni, Au form sandwich construction, gross thickness obtains the ohmic contact of the P type GaN of non-alloying at 300-1000nm.

The preparation method of low-dislocation-density led chip of the present invention compares with prior art has following beneficial effect:

The present invention is before epitaxial growth GaN, and the patterned metal heat sink of growth one deck adopts the epitaxial lateral overgrowth technology can effectively reduce the dislocation density of epitaxial loayer more earlier.Adopt the dislocation density of the LED of this method preparation to reduce 10%-30%.The cathode-luminescence spectrum strengthens 10%-30%,, electroluminescence spectrum intensity enhancing 10%-30%.

The present invention at first utilizes dry etching technology Sapphire Substrate to be prepared into the graph substrate with periodicity striped, form table top and groove, be used for growing GaN afterwards, GaN need not take out from reative cell like this, can not produce and pollute, save the time, reduced manufacturing cost it.

Description of drawings

The invention will be further described below in conjunction with accompanying drawing:

Fig. 1 is the structural representation according to the product of making of the present invention.

Among the figure: 1 is that C surface sapphire substrate, 2 is that GaN resilient coating, 3 is that N type electrode, 4 is that reflector, 5 is that metal heat sink elementary layer, 6 is that N type GaN layer, 7 is that active layer, 8 is that P type GaN layer, 9 is a P type electrode.

Embodiment

The preparation method of low-dislocation-density led chip may further comprise the steps:

The first step, growing GaN resilient coating 2 on C surface sapphire substrate 1; Second step, the N type electrode 3 that evaporation is transparent on the GaN resilient coating; In the 3rd step, successively evaporation Ni, Ag, Ti, Au form reflector 4 on N type electrode 3; In the 4th step, growth one layer thickness is not less than the metal level of 50 μ m on reflector 4; Utilize dry etching technology that this layer metal level is prepared into smooth, periodic metal heat sink elementary layer 5,100-200 μ m at interval; The 5th step, epitaxial growth N type GaN layer 6 on metal heat sink elementary layer 5; In the 6th step, growth active layer 7 on N type GaN layer 6 adopts quaternary AlInGaN as the Multiple Quantum Well layer material; The 7th step, growth P-type GaN layer 8 on active layer 7; The 8th step, growing P-type electrode 9 on P type GaN layer 8.

Described reflector 4 gross thickness interconnect to each other at 100-200nm, form conductive network.The thickness of metal heat sink elementary layer 5 is 50 μ m.Handle P type GaN layer 8 surface with CF4, successively evaporation Ti, Al, Ni, Au form sandwich construction on P type GaN layer 8 surface, and gross thickness obtains the ohmic contact of the P type GaN of non-alloying at 300-1000nm.

As shown in Figure 1, a kind of led chip of energy lowering dislocation density, comprise: C surface sapphire substrate 1, GaN resilient coating 2, N type electrode 3, reflector 4, metal heat sink elementary layer 5, N type GaN layer 6, active layer 7, P type GaN layer 8 and P type electrode 9, its structure is: the top of C surface sapphire substrate 1 is disposed with GaN resilient coating 2, N type electrode 3, reflector 4, metal heat sink elementary layer 5, N type GaN layer 6, active layer 7, P type GaN layer 8 and P type electrode 9 from bottom to top.

Metal heat sink elementary layer 5 thickness are not less than 50 microns, and the horizontal of metal heat sink elementary layer 5 is the junior unit of controlling at interval between the 100-200 μ m that is periodic distribution, and metal heat sink elementary layer 5 can effectively reduce the dislocation density of led chip.

Reflector 4 successively is made up of Ni, Ag, Ti, Au metal, is multi-quantum pit structure, and the Ni layer connects Ag layer and N type electrode 3 respectively.

N type electrode 3 is made up of the Ni and the Au of oxidation.

Between P type electrode 9 and the P type GaN layer 8 is ohmic contact.

The material of active layer 7 is AlInGaN.

Claims

1. the preparation method of low-dislocation-density led chip is characterized in that may further comprise the steps:

The 7th step, growth P-type GaN layer on active layer;

The 8th step, growing P-type electrode on P type GaN layer.

2. according to the preparation method of the described low-dislocation-density led chip of claim, it is characterized in that: described reflector gross thickness interconnects to each other at 100-200nm, forms conductive network.

3. the preparation method of low-dislocation-density led chip according to claim 1 is characterized in that: the thickness of described metal heat sink elementary layer is 50 μ m.

4. the preparation method of the led chip of low-dislocation-density according to claim 1, it is characterized in that: handle P type GaN laminar surface with CF4, successively evaporation Ti, Al, Ni, Au form sandwich construction at P type GaN laminar surface, gross thickness obtains the ohmic contact of the P type GaN layer of non-alloying at 300-1000nm.