CN101777517B - Method for manufacturing memory - Google Patents

Method for manufacturing memory Download PDF

Info

Publication number
CN101777517B
CN101777517B CN 200910045245 CN200910045245A CN101777517B CN 101777517 B CN101777517 B CN 101777517B CN 200910045245 CN200910045245 CN 200910045245 CN 200910045245 A CN200910045245 A CN 200910045245A CN 101777517 B CN101777517 B CN 101777517B
Authority
CN
Grant status
Grant
Patent type
Prior art keywords
nitride
oxide
dielectric layer
common source
method
Prior art date
Application number
CN 200910045245
Other languages
Chinese (zh)
Other versions
CN101777517A (en )
Inventor
兰国华
庄晓辉
李俊
王三坡
Original Assignee
中芯国际集成电路制造(上海)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Abstract

The invention discloses a method for manufacturing a memory, which comprises the following steps: forming a common source area, a common drain area and a bottom dielectric layer on a semiconductor substrate; sequentially stacking a floating gate, an insulating layer and a control gate on the bottom dielectric layer; depositing a nitride on the upper surface and lateral surfaces of the gate structure formed by stacking the floating gate, the insulating layer and the control gate; depositing an oxide on the surface of the nitride to fill up the gap formed in the gate structure above the common source area; removing part of the oxide; and removing the nitride above the common drain area. In the method, the layer of oxide is deposited after the nitride is deposited, a function of delaying etching is realized in the nitride removing process and Co ions are prevented from entering the bottom dielectric layer above the common source area in a subsequent Co ion injection process, so the charges in the floating gate is prevented from escaping to the bottom dielectric layer above the common source area, the holding capacity of the data stored in the floating gate is improved, and the memory data storage time is improved.

Description

存储器制造方法 A method of manufacturing a memory

技术领域 FIELD

[0001] 本发明涉及半导体制造方法领域,具体地说,涉及一种存储器制造方法。 [0001] The present invention relates to the field of semiconductor manufacturing method, and more particularly, to a method for manufacturing a memory. 背景技术 Background technique

[0002] 存储器用于存储大量数字信息,据近期调查显示,在世界范围内,存储器芯片交易量约占半导体芯片交易量的30%。 [0002] memory for storing large amounts of digital information, according to a recent survey, worldwide, trading volume memory chips account for about 30% of the trading volume of the semiconductor chip. 多年来,工艺技术的进步和市场需求的增加催生出很多高密度的各类存储器芯片,如随机存储器(RAM)、动态随机存储器(DRAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM)、闪存(FLASH)和铁电存储器(FRAM)等。 Over the years, technology advances and increasing market demands spawned many types of high-density memory chips, such as a random access memory (RAM), dynamic random access memory (DRAM), a read only memory (ROM), an erasable programmable only read-only memory (EPROM), a flash memory (FLASH) and a ferroelectric memory (FRAM) and the like.

[0003] 目前存储器技术正向提高集成度以及缩小元件尺寸的方向发展。 [0003] Development of the current memory technologies to improve the forward direction and reduce the integration element size. 用户使用存储器时,除要求存储器具备高存储能力,低功耗及高可靠性外,对存储器的数据存储时间也提出了高要求,例如要求数据存储时间为10年以上。 When the user uses the memory, in addition to the memory required with high storage capacity, low power consumption and high reliability, the data stored in the time memory also high demands, such as requiring the data storage time of 10 years.

[0004] 存储器的数据存储时间通常采用数据保持能力测试(data retation testing)方案测量,该方案通常为: [0004] Data is usually stored in the time store data retention test (data retation testing) measuring program, the program is generally as follows:

[0005] 首先将存储器在温度为250°C的环境里烘烤M小时,然后测试存储器内存储单元的阈值电压(Vt)值,如果Vt小于预定值,意味着该存储器的数据保持能力比较低,其数据存储时间也就较短。 [0005] The first memory M baked hours at a temperature of ambient to 250 ° C, and then the threshold voltage (Vt) of the memory cell within the test value if less than the predetermined value Vt, which means that the data storage capacity is relatively low retention , the data storage time will be shorter.

[0006] 现有存储器制造方法包括步骤: [0006] The conventional memory fabrication method comprising the steps of:

[0007] 第一步:参阅图1A,在半导体基体1内形成共源区3和共漏区2,然后在半导体基体1上表面形成底介电层4,再在底介电层4上表面的预定区域依次形成浮栅5、绝缘层6 以及控制栅7构成栅结构,所述栅结构覆盖的基体1内的区域位于共源区3及共漏区2之间; [0007] Step: Refer to Figure 1A, a semiconductor substrate 3 and a common drain region 2 forming the common source region 1, the bottom dielectric layer 4 is then formed on the surface of the semiconductor substrate 1, and then on the bottom dielectric layer 4 surface a predetermined region 5 sequentially formed on the floating gate, a control gate insulating layer 6 and 7 constituting the gate structure, the gate region in a structure covering the base 2 is located between the common source region 3 and a common drain region;

[0008] 第二步:参阅图1B,在底介电层4上表面栅结构未覆盖的区域,以及所述栅结构的上表面和侧面,沉积氮化物8 ; [0008] Second Step: Referring to Figure 1B, a region of the surface not covered by the gate structure on the bottom dielectric layer 4, and the upper surface and side surfaces of the gate structure, depositing a nitride 8;

[0009] 第三步:参阅图1C,去除底介电层4上表面栅结构未覆盖的区域上的氮化物8。 [0009] Third Step: Refer to Figure 1C, the nitride is removed in the region of the dielectric layer 4 on the bottom surface of the gate structure uncovered 8.

[0010] 第四步:参阅图1D,采用离子注入工艺,在暴露出的底介电层4上注入钴(Co)离子并进行,然后进行化学反应,使得在所述在注入Co离子区域的底介电层4上含有二硅化钴10(CoSi2)。 [0010] The fourth step: see 1D, the ion implantation process, injection cobalt (Co) ions on the exposed end of the dielectric layer 4 and then a chemical reaction, such that Co ions in the implanted region in containing cobalt disilicide 10 (CoSi2) on the bottom dielectric layer 4. 由于二硅化钴10是低阻相物质,其电阻比较低,因此在含有二硅化钴10的漏极表面连接漏极线,使得漏极线与漏极表面形成的连线阻抗将大大减小,从而可使得电路通过漏极线对上述制造的存储单元读取数据的速度得到极大改善。 Because cobalt disilicide phase 10 is a low resistance material, the resistance is relatively low, so the drain containing cobalt disilicide surface 10 is connected to the drain line such that the drain line and the drain wiring formed on the surface impedance will be greatly reduced, so that the circuit can be greatly improved through the drain line of the memory cell to read data of the above-described manufacturing speed.

[0011] 在对上述制造工艺制成的存储器的浮栅5进行数据保持能力测试时,不良率为6%以上,上述存储器制造流程的缺陷在于:在第三步制造过程中,当去除底介电层4中覆盖共漏区2的区域上表面的氮化物8时,底介电层4中覆盖共源区3的区域上表面的氮化物8也会被去除,导致后续注入Co离子时,在共源区3位置的底介电层4中也会有Co离子注入,后续的化学反应步骤使得使得在共源区3位置的底介质层4也含有二硅化钴10。 [0011] When the floating gate made of the above-described manufacturing process of the memory 5 data retention tests, failure was more than 6%, the above-described manufacturing process is defective memory comprising: a third step in the manufacturing process, when removed via the bottom dielectric layer 4 covering a total area of ​​the drain region 2 on the nitride surface 8, the bottom dielectric layer 4 covers the common source regions of the nitride surface area 3 8 will be removed, resulting in the subsequent ion implantation Co, in common source region bottom dielectric layer 3 will have position 4 Co ion implantation, so that subsequent chemical reaction steps such that the bottom dielectric layer common source region 3 position 4 also contains cobalt disilicide 10.

[0012] 于是在针对浮栅5进行数据保持能力测试过程中,存储器经过M小时烘烤后,测试人员发现存储在浮栅5内的电荷将逃逸至在共源区3上含有二硅化钴10的底介质层4中,进而导致测试出的存储器数据保持能力较差,即存储器的数据存储时间降低。 [0012] Thus the data for the floating gate 5 during the retention test, the memory M after hours of baking, the test found that the charge stored in the floating gate 5 would escape to 10 containing cobalt disilicide on the common source region 3 the bottom dielectric layer 4, leading to test the ability of poor data holding memory, i.e. memory data storage time is reduced. 发明内容 SUMMARY

[0013] 本发明要解决的技术问题是提供一种存储器制造方法,以提高数据保持能力。 [0013] The present invention is to solve the technical problem of providing a method for manufacturing a memory to enhance data retention.

[0014] 为解决上述技术问题,本发明提供的的存储器制造方法,包括如下步骤: [0014] In order to solve the above problems, the present invention provides a method of manufacturing a memory, comprising the steps of:

[0015] 在半导体基体上形成共源区和共漏区、底介电层、并在所述底介电层上依次堆叠形成浮栅、绝缘层以及控制栅; [0015] form a common source and common drain regions, a bottom dielectric layer on a semiconductor substrate, and sequentially stacked to form a floating gate, an insulating layer on the bottom dielectric layer and a control gate;

[0016] 在所述浮栅、绝缘层以及控制栅堆叠形成的栅结构上表面以及侧面沉淀氮化物; [0016] and a side surface of a nitride precipitate on the gate structure of the floating gate, and a control gate stack insulating layer is formed;

[0017] 在所述氮化物表面上沉淀氧化物,以填满所述栅结构在共源区上方形成的间隙, 其中,所述栅结构在共源区上方形成的间隙小于其在共漏区上方形成的间隙; [0017] The oxide precipitate on the nitride surface to fill the gap of the gate structure over the common source region is formed, wherein a gap between the gate structure is formed over the common source region is smaller than the common drain region above the gap formed;

[0018] 去除部分氧化物,同时,在共源区上方的间隙还存留部分氧化物; [0018] removing portions of the oxide, while the gap above the common source region and remain part of the oxide;

[0019] 去除在所述共漏区上方的氮化物。 [0019] In the co-remove the nitride over the drain region.

[0020] 进一步的,在所述共漏区上的底介电层中注入钴离子; [0020] Further, the bottom dielectric layer of cobalt ions on the common drain region implantation;

[0021] 将注入的钴离子反应形成钴化物; [0021] The cobalt ion implantation to form cobalt compound;

[0022] 在形成钴化物的底介电层上形成金属连线。 [0022] The metal wiring is formed on the bottom dielectric layer of cobalt compound is formed.

[0023] 进一步的,所述氮化物为氮化硅。 [0023] Further, the nitride is silicon nitride.

[0024] 进一步的,所述钴化物为二硅化钴。 [0024] Further, the cobalt compound is cobalt disilicide.

[0025] 进一步的,所述绝缘层为包含氧化物-氮化物-氧化物或包含氧化物-氮化物的介质结构。 [0025] Further, the insulating layer comprising an oxide - nitride - oxide or an oxide comprising - a nitride dielectric structure.

[0026] 进一步的,所述绝缘层为氧化物与氮化物的组合物、氧化物或氮化物。 [0026] Further, the insulating layer of the composition of the oxide and the nitride, oxide or nitride.

[0027] 进一步的,所述浮栅以及控制栅为多晶硅。 [0027] Further, the floating gate and the control gate polysilicon.

[0028] 与现有存储器制造方法相比,本发明在形成氮化物后再沉淀一层氧化物,以填满多个所述浮栅、绝缘层及控制栅堆叠形成的栅结构之间在共源区上方的间隙,为在后续刻蚀去除氧化物的过程中,去除在共漏区上方形成的氧化物后,共源区上方的间隙还存留部分氧化物,在蚀刻去除氮化物过程中起到延缓蚀刻的作用,使得在刻蚀去除氮化物时,共源区上方的间隙还残留部分氮化物,阻止后续Co离子注入过程中Co离子进入到共源区上的底介质层,从而避免了浮栅内的电荷逃逸到共源区的底介质层,提高存储在浮栅内的数据保持能力,进而提高存储器数据存储时间。 [0028] Compared with the conventional method of manufacturing a memory, between the gate structure of the present invention the precipitate formed after the nitride layer of oxide, to fill a plurality of said floating gate and a control gate stack insulating layer formed in the co- clearance above the source region is removed in the subsequent etching process of the oxide, the total removal of the oxide over the drain region is formed, the space above the common source region and remain part of the oxide, the nitride is removed in the etching process from delaying the etching, such that upon removal of the nitride etch, clearance above the common source region further residual portion nitride, prevent subsequent Co Co ions during ion implantation into the bottom dielectric layer on the common source region, thus avoiding escape of charges in the floating gate to the source region of the bottom dielectric layer co-improving data stored in the holding capacity of the floating gate, thereby improving memory data storage time.

附图说明 BRIEF DESCRIPTION

[0029] 以下结合附图和具体实施方式对本发明的芯片制造方法作进一步的详细说明。 [0029] The following specific embodiments in conjunction with the accompanying drawings and described in detail further chip manufacturing method according to the present invention.

[0030] 图IA-图ID为现有技术的存储器制造方法的截面示意图; [0031 ] 图2A-图2F是本发明实施例的存储器制造方法截面示意图。 [0030] FIG FIGS IA- ID is a schematic cross-sectional memory fabrication method of the prior art; [0031] FIGS. 2A- 2F are memory fabrication method of an embodiment of the present invention is a schematic sectional view.

具体实施方式 Detailed ways

[0032] 请参阅图1A,在半导体基体1上形成共源区3和共漏区2、底介电层4、并在所述底介电层4上表面的预定区域依次堆叠形成浮栅5、绝缘层6以及控制栅7构成栅结构,所述栅结构覆盖的基体1内的区域位于共源区3及共漏区2之间。 [0032] Please refer to FIG. 1A, a common source region 3 and the common drain region on the semiconductor substrate 12, the bottom dielectric layer 4, and are sequentially stacked to form the floating gate 5 in a predetermined region on the surface 4 of the bottom dielectric layer , the insulating layer 6 and the control gate electrode 7 constituting the gate structure, the gate region in a structure covering the base 2 is located between the common source region and common drain region 3.

[0033] 所述浮栅5和控制栅6均为多晶硅。 [0033] The floating gate electrodes 5 and 6 are the control gate polysilicon. 所述绝缘层6可以为氧化物与氮化物的组合物、氧化物或氮化物,比如ONO (氧化物-氮化物-氧化物)的介质结构或者ON (氧化物-氮化物)的介质结构,本实施例中,所述绝缘层6为ONO叠加的介质结构。 The insulating layer 6 may be a composition, oxide or nitride oxide nitrides, such as the ONO (oxide - nitride - oxide) structure or a medium ON (oxide - nitride) dielectric structure, in this embodiment, the insulating layer 6 is superposed ONO dielectric structure.

[0034] 请参阅图2A,在所述浮栅5、绝缘层6以及控制栅7依次堆叠形成的栅结构上表面以及侧面沉淀形成厚度均勻的氮化物8,所述氮化物8为氮化硅。 [0034] Please refer to FIGS. 2A, a uniform thickness of the nitride surface and a side surface 8 is formed on the gate precipitate structure of the floating gate 5, insulating layer 6 and the control gate 7 are sequentially stacked is formed, the nitride is silicon nitride 8 .

[0035] 请参阅图2B,在上述沉淀形成的氮化物8表面上沉积一层氧化物9 ; [0035] Please refer to Figure 2B, an oxide layer 9 is deposited on the surface of the nitride 8 is formed in said precipitation;

[0036] 所述浮栅5、绝缘层6以及控制栅7堆叠形成的栅结构在共源区3上方形成的间隙小于其在共漏区2上方形成的间隙,共源区3上方的间隙比较窄,共漏区2上方的间隙比较宽,因此进行沉淀形成所述氧化物9的时候,从所述浮栅5、绝缘层6以及控制栅7堆叠形成的栅结构两侧沉淀的氧化物9很快就将在共源区3上方的间隙填满,在较宽的共漏区2上方只是形成一层均勻的氧化物9。 [0036] The floating gate 5, a gap of the gate structure and the control gate insulating layer 6 is formed over the stack 7 common source region 3 is formed smaller than a gap formed above the common drain region 2, the gap above the common source region 3 Comparative 2 above the narrow gap, a common drain region is wide, thus precipitating the formed 9 when the oxide precipitated on both sides of the gate structure is formed from said floating gate 5, insulating layer 6 and the control gate 7 oxide stack 9 soon gap 3 filled above the common source region, but uniform oxide layer 9 formed over the wide common drain region 2.

[0037] 请参阅图2C,采用刻蚀方法去除覆盖在所述氮化物8上的氧化物9,由于共源区3 上方的间隙比较窄,在共源区3上方的间隙填满形成的氧化物9的高度远远高于在共漏区2上方形成的氧化物9的高度,因此当共漏区2上方的氧化物9被刻蚀去除完毕时,共源区3上方还有部分残留的氧化物9。 [0037] Please refer to Figure 2C, using an etching method for removing the nitride overlying the oxide 8, 9, since the relatively narrow gap over the common source region 3, to fill the gap 3 is formed above the common source regions oxide 9 was much higher than the height of the height of the oxide above the drain region 2 is formed co-9, and therefore when the oxide 2 over the common drain region 9 is removed by etching is completed, as well as the common source region above the part of the residual 3 oxide 9.

[0038] 进一步,参阅图2D,刻蚀去除在共漏区上方的氮化物8,由于在上述刻蚀去除氧化层9过程中,在共源区3上方的氮化物8上还有部分残留氧化物9,因此共源区3上方残留氧化物9以及氮化物8叠加形成的绝缘结构的厚度远远超过在共漏区2上方的氮化物8的厚度,于是对共源区3和共漏区2上方的氮化物进行刻蚀去除时,在共源区3上方,需先刻蚀去除共源区3上方残留的氧化物9再刻蚀去除氮化物8。 [0038] Further, refer to Figure 2D, the etching is removed above the common drain region 8 nitride, since the process of removing the oxide layer 9, there are some remaining oxide on the nitride 8 over the common source region 3 in the above etching was 9, a total of the thickness of oxide remaining over the source region 3 and the insulating structure 9 8 overlapped to form a nitride far exceed the thickness of the nitride over the common drain region 2 of 8, then to the common source and common drain region 3 when the nitride is etched away above 2, over the common source region 3, the etching must first remove residual oxide 3 over the common source region 9 and then etching the nitride 8 is removed. 因此,残留的氧化物9起到缓冲延迟刻蚀作用,当所述共漏区2上方的氮化物8刻蚀完毕,共源区3上方的氮化物8还未刻蚀完毕,从而保留了部分残留氮化物8。 Thus, the residual retardation oxide etching effect cushion 9, when the nitride 2 above the common drain region 8 is completed etched, the nitride 3 above the common source region 8 has not been completed etching, thereby leaving a portion The residue nitride 8.

[0039] 请参阅图2E及图2F,完成了上刻蚀工艺后,所述共漏区2上的底介电层4暴露出来,并在所述底介电层4上注入钴离子。 [0039] Referring to FIG. 2E and FIG. 2F, after completion of the etching process, the common drain region 2 of the bottom dielectric layer 4 is exposed, and cobalt ions implanted on the bottom dielectric layer 4. 然后进行化学反应,本实施例中,所述钴离子进行化学反应后形成二硅化钴10(CoSi2),二硅化钴10其电阻比较低,在含有二硅化钴10的表面连接漏极线11,使得漏极线11与漏极表面形成的连线阻抗将大大减小,从而可使得电路通过漏极线对上述制造的存储单元读取数据的速度得到极大改善。 Then a chemical reaction, in this embodiment, after forming the cobalt ions chemically reacting cobalt disilicide 10 (of CoSi2), cobalt disilicide relatively low resistance 10, is connected comprising cobalt disilicide surface 10 of the drain line 11, so that the surface of the drain 11 and the drain line formed wire resistance will be greatly reduced, so that the circuit can read the data line through the drain of the memory cell above production speed is greatly improved.

[0040] 由于本发明实施例中,所述共源区3上方含有部分残留的氮化物8,因此在注入Co 离子后,由于残留的氮化物8隔离,Co离子无法进入共源区3上的底介电层4,在后续进行化学反应过程中,无法形成二硅化钴10,避免存储在浮栅5中的电荷逃逸至共源区3上的底介电层4中,降低浮栅5数据保持能力的问题,从而大大提高了浮栅5的数据保持能力,在进行数据保持能力测试过程中,采用本实施例中的存储器制造方法取得了满意的效果,其良率为99. 3%。 [0040] Since the embodiment, over the common source region 3 containing nitride remaining portion 8, so after implantation Co ions, due to the remaining nitride spacer 8, Co ions can not enter the common source region 3 of the embodiment of the present invention bottom dielectric layer 4, in the course of subsequent chemical reaction, not formed cobalt disilicide 10, prevent the charge stored in the floating gate 5, to escape to the bottom dielectric layer 3, the common source region 4 to reduce the floating gate 5 data problems holding capacity, thereby greatly improving the data retention capability of the floating gate electrode 5, during the testing process the data holding capability, the memory employed in the manufacturing method of obtaining a satisfactory effect of the present embodiment, its yield was 99.3%.

[0041 ] 最后,请参阅图2F,在注入钴离子的底介电层4上形成金属连线即漏极线11,外部电路即可通过漏极线11对所述浮栅5进行读取数据,由于形成金属连线工艺为现有成熟工艺,在此不再详述。 [0041] Finally, referring to FIG 2F, is formed on the bottom dielectric layer of cobalt ion implanted metal wiring 4 that is the drain line 11, to an external circuit through the drain line 11 to said floating gate read data 5 , since the metal wiring process is a mature technology conventional, not further described herein.

[0042] 以上显示和描述了本发明的基本原理、主要特征和本发明的优点。 [0042] The above and described the principles of the invention, the main features and advantages of the present invention. 本行业的技术人员应该了解,本发明不受上述实施例的限制,上述实施例和说明书中描述的只是说明本发明的原理,在不脱离本发明精神和范围的前提下本发明还会有各种变化和改进,这些变化和改进都落入要求保护的本发明范围内。 The industry the art will appreciate, the present invention is not limited to the above embodiment, the above-described examples and embodiments described in the specification are only illustrative of the principles of the present invention, without departing from the spirit and scope of the present invention, the present invention also have the respective variations and modifications, changes and modifications which fall within the scope of the claimed invention. 本发明要求保护范围由所附的权利要求书及其等同物界定。 The scope of the invention as claimed by the appended claims and equivalents thereof defined.

Claims (7)

1. 一种存储器制造方法,其特征在于,包括如下步骤:在半导体基体上形成共源区和共漏区、底介电层、并在所述底介电层上依次堆叠形成浮栅、绝缘层以及控制栅;在所述浮栅、绝缘层以及控制栅堆叠形成的栅结构上表面以及侧面沉淀氮化物; 在所述氮化物表面上沉淀氧化物,以填满所述栅结构在共源区上方形成的间隙,其中, 所述栅结构在共源区上方形成的间隙小于其在共漏区上方形成的间隙; 去除部分氧化物,同时,在共源区上方的间隙还存留部分氧化物; 去除在所述共漏区上方的氮化物。 CLAIMS 1. A method of manufacturing a memory, characterized by comprising the steps of: forming a common source region and common drain regions, a bottom dielectric layer on a semiconductor substrate, and sequentially stacked floating gate is formed on the bottom dielectric layer, insulation and a control gate layer; and a side surface of a nitride precipitate on the gate structure of the floating gate, and a control gate stack insulating layer is formed; the oxide precipitate on the nitride surface to fill the gate structure common source a gap formed above the region, wherein the gate structure over the gap common source region is formed smaller than the gap formed above the common drain region; removing portions of the oxide, while the gap above the common source region and remain part of the oxide ; removing the nitride at the top of a common drain region.
2.如权利要求1所述的存储器制造方法,其特征在于,还包括如下步骤: 在所述共漏区上的底介电层中注入钴离子;将注入的钴离子反应形成钴化物; 在形成钴化物的底介电层上形成金属连线。 2. The method of manufacturing a memory according to claim 1, characterized by further comprising the steps of: a bottom dielectric layer of cobalt ions on the common drain region of injection; the cobalt ion implantation to form cobalt compound; in bottom dielectric layer is formed of cobalt compound is formed on the metal wiring.
3.如权利要求1所述的存储器制造方法,其特征在于:所述氮化物为氮化硅。 The method of manufacturing a memory according to claim 1, wherein: said nitride is silicon nitride.
4.如权利要求2所述的存储器制造方法,其特征在于:所述钴化物为二硅化钴。 4. A method of manufacturing a memory according to claim 2, wherein: said cobalt compound is cobalt disilicide.
5.如权利要求1所述的存储器制造方法,其特征在于:所述绝缘层为包含氧化物-氮化物-氧化物或包含氧化物-氮化物的介质结构。 5. The method of manufacturing a memory according to claim 1, wherein: said insulating layer comprising an oxide - nitride - oxide or an oxide comprising - a nitride dielectric structure.
6.如权利要求1所述的存储器制造方法,其特征在于:所述绝缘层为氧化物与氮化物的组合物、氧化物或氮化物。 Method of manufacturing a memory according to claim 1, wherein: said insulating layer is an oxide composition of the nitride, oxide or nitride.
7.如权利要求1所述的存储器制造方法,其特征在于:所述浮栅以及控制栅为多晶硅。 7. The method of manufacturing a memory according to claim 1, wherein: said floating gate and the control gate polysilicon.
CN 200910045245 2009-01-13 2009-01-13 Method for manufacturing memory CN101777517B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200910045245 CN101777517B (en) 2009-01-13 2009-01-13 Method for manufacturing memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200910045245 CN101777517B (en) 2009-01-13 2009-01-13 Method for manufacturing memory

Publications (2)

Publication Number Publication Date
CN101777517A true CN101777517A (en) 2010-07-14
CN101777517B true CN101777517B (en) 2012-01-25

Family

ID=42513915

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200910045245 CN101777517B (en) 2009-01-13 2009-01-13 Method for manufacturing memory

Country Status (1)

Country Link
CN (1) CN101777517B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6436765B1 (en) 2001-02-09 2002-08-20 United Microelectronics Corp. Method of fabricating a trenched flash memory cell
CN1898792A (en) 2003-12-31 2007-01-17 英特尔公司 Contactless flash memory array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6436765B1 (en) 2001-02-09 2002-08-20 United Microelectronics Corp. Method of fabricating a trenched flash memory cell
CN1898792A (en) 2003-12-31 2007-01-17 英特尔公司 Contactless flash memory array

Also Published As

Publication number Publication date Type
CN101777517A (en) 2010-07-14 application

Similar Documents

Publication Publication Date Title
US7626235B2 (en) NAND nonvolatile semiconductor memory device and method of manufacturing NAND nonvolatile semiconductor memory device
US5457063A (en) Method for fabricating a capacitor for a dynamic random access memory cell
US20120068242A1 (en) Semiconductor devices and methods of fabricating the same
US5240558A (en) Method for forming a semiconductor device
US6483146B2 (en) Nonvolatile semiconductor memory device and manufacturing method thereof
US20120058629A1 (en) Methods of manufacturing vertical semiconductor devices
US7115943B2 (en) Nonvolatile semiconductor memory device and manufacturing method thereof
US20060286749A1 (en) Method of fabricating non-volatile memory
US20100301404A1 (en) Semiconductor device and production method thereof
US7071061B1 (en) Method for fabricating non-volatile memory
US20050186739A1 (en) Flash memory device having poly spacers
US7313026B2 (en) Semiconductor device
US7049189B2 (en) Method of fabricating non-volatile memory cell adapted for integration of devices and for multiple read/write operations
US20080272434A1 (en) Non-volatile memory device and method of manufacturing the same
US20080048242A1 (en) Semiconductor device having load resistor and method of fabricating the same
JP2002280467A (en) Sonos flash memory element and its fabricating method
US6797557B2 (en) Methods and systems for forming embedded DRAM for an MIM capacitor
US20070238237A1 (en) Structure and method for a sidewall SONOS non-volatile memory device
US20040140510A1 (en) Semiconductor memory device having a gate insulation film and a manufacturing method thereof
US20080023751A1 (en) Integrated circuit memory system employing silicon rich layers
US5384272A (en) Method for manufacturing a non-volatile, virtual ground memory element
US6251725B1 (en) Method of fabricating a DRAM storage node on a semiconductor wafer
JP2003218242A (en) Non-volatile semiconductor memory device and method of manufacturing the same
CN102956554A (en) Separate gate type flash memory of embedded logic circuit and fabricating method thereof
US20100255670A1 (en) Nonvolatile semiconductor memory and method of manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C14 Granted