CN101777515A - Manufacturing method of semiconductor memory - Google Patents
Manufacturing method of semiconductor memory Download PDFInfo
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- CN101777515A CN101777515A CN200910045243A CN200910045243A CN101777515A CN 101777515 A CN101777515 A CN 101777515A CN 200910045243 A CN200910045243 A CN 200910045243A CN 200910045243 A CN200910045243 A CN 200910045243A CN 101777515 A CN101777515 A CN 101777515A
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Abstract
The invention discloses a manufacturing method of a semiconductor memory, comprising the following steps of: providing a semiconductor substrate with a memory unit zone and a peripheral circuit zone; forming a grid substance layer on the semiconductor substrate; forming a first masking film on the grid substance layer, wherein the first masking film shields the peripheral circuit zone and defines a grid allay in the memory unit zone; etching to form the grid allay by using the first masking film as a barrier layer; and carrying out anti-penetration (APT) injection by using the first masking film as the barrier layer. Therefore, different form the traditional method utilizing the grid allay as the barrier layer for the APT injection, the manufacturing method retains the masking film for defining the grid allay of the memory unit zone and uses the masking film as the barrier layer for the APT injection to reduce the association degree of the thickness of the grid allay and the APT injection, thereby reducing the thickness of the grid array according to other performance requirements of the memory unit zone, and then improving the integration level of the semiconductor memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of semiconductor memory.
Background technology
Semiconductor memory is the solid electronic device that utilizes the storing data information that semiconductor integrated circuit technique makes, and it is made of a large amount of memory cell and input, output circuit etc.Compare with magnetic storage, semiconductor memory has advantages such as access speed is fast, memory capacity is big, volume is little, and memory cell array and main peripheral logical circuit compatibility, can be manufactured on the same chip, and input/output interface is greatly simplified.Therefore, semiconductor memory has obtained very widely to use in electronic products such as computer, becomes the important composition parts of electronic product such as computer.
Fig. 1 has just provided a kind of part planar structure schematic diagram of semiconductor memory.As shown in the figure, semiconductor memory often comprises memory cell areas (cell area) 100 and periphery circuit region (peripheral area) 200.In memory cell areas 100, the memory cell array that mutually orthogonal word line WL (Word Line) and bit line BL (Bit Line) constitute; The read-write operation of logic transistor 201 control store cellular zones 100 memory cell of periphery circuit region 200.Usually, bit line BL is embedded among the Semiconductor substrate by ion implantation technology; Word line WL then is the grid array that forms by grid technology.Fig. 2 to Fig. 7 has just provided a kind of forming process of existing semiconductor memory, in above-described accompanying drawing, is along the given structural representation of A-A direction among Fig. 1 (a), and (b) is along the given structural representation of B-B direction among Fig. 1.
At first, as Fig. 2, provide Semiconductor substrate 10, it comprises memory cell areas 100 and periphery circuit region 200.Then as Fig. 3,100 carry out the ion injection in the storage element district, thereby form a plurality of impurity diffusion layers in Semiconductor substrate 10, then impurity diffusion layer are carried out the speedup oxidation, thereby form multiple bit lines BL; Certainly carrying out utilizing mask definition ion implanted region before ion injects, the speedup oxidation can utilize the heat treatment of uniform temperature and time to realize, these all are technology well-known to those skilled in the art, do not repeat them here.Finished the making of bit line BL, just can further carry out the making of grid structure, it comprises the grid array of memory cell areas 100 and the logic transistor grid of periphery circuit region 200, and concrete forming process is as follows:
As Fig. 4, on Semiconductor substrate, form ONO (silica-silicon-nitride and silicon oxide) layer; Then by silica, silicon nitride etch, remove in the ONO layer of periphery circuit region 200 silicon nitride and silicon oxide layer away from Semiconductor substrate, only keep silicon oxide layer on the Semiconductor substrate as the gate dielectric layer 12 of periphery circuit region 200, and the gate dielectric layer 11 that memory cell areas 100 remaining ONO layers are memory cell areas 100.Then,, on gate dielectric layer 11 and 12, form polysilicon layer 13, and utilize mask 14 in memory cell areas 100 definition grid arrays 15, in the position of periphery circuit region 200 definition logic transistor grids 16 as Fig. 5.So, as Fig. 6, be the barrier layer with mask 14, etching forms grid array 15 and logic transistor grid 16, then removes mask 14.Certainly be formed with sidewall structure toward contact on the grid 16 of logic transistor, it is well known to those skilled in the art, at this, repeat no more, and in order to simplify, also not shown among the figure.
At this moment, though finished the making of bit line BL and word line WL, tended to produce electric leakage between the consecutive storage unit and disturb, for this reason, need between memory cell, to carry out anti-penetration and inject (APT implantation, Anti-Punch Through implantation).As Fig. 7, memory cell areas 100 is carried out anti-penetration inject, thereby between consecutive storage unit, form anti-penetration injection region 101, disturb with the electric leakage that reduces between the consecutive storage unit.Certainly, periphery circuit region 200 also needs to carry out operations such as light dope injects, source leakage injection, and to form source, the drain region of logic transistor 201, it is well known to those skilled in the art, do not repeat them here, and in order to simplify, also not shown among the figure.As shown in the figure, in the APT injection process, grid array 15 is equivalent to the effect on barrier layer, prevent from that APT from injecting to penetrate memory cell, so grid array 15 must have certain thickness, injects the scope that can reach to bear APT.
Yet, in the manufacture process of semiconductor memory, more than have certain thickness grid array 15 and will bring following shortcoming:
At first, grid array 15 is thick more, and its profile is difficult to control more, promptly is difficult to keep the straight of each grid structure in the grid array 15 in etching process more, and then causes the short circuit between the adjacent two word line WL easily.
In addition, development along with semiconductor integrated circuit technique, the integrated level of semiconductor memory increases day by day, gap between the grid array 15 is also more and more littler, and its thickness can not reduce because of the APT injection technology thereupon, so, reciprocal proportional increase of the resistance value of each grid structure unit length and its width in the grid array 15, thereby have a strong impact on the performance of device, for semiconductor memory further granular or high integration brought obstacle.
Summary of the invention
Technical problem to be solved by this invention is the correlation degree that reduces between memory cell areas grid array thickness and anti-penetration (APT) injection, and then improves the integrated level of semiconductor memory.
For solving above technical problem, the invention provides a kind of manufacture method of semiconductor memory, comprising: the Semiconductor substrate with memory cell areas and periphery circuit region is provided; On described Semiconductor substrate, form grid substance layer; Form first mask on described grid substance layer, this first mask blocks periphery circuit region and defines grid array in memory cell areas; With described first mask is the barrier layer, and etching forms grid array; With described first mask is the barrier layer, carries out anti-penetration and injects.
Further, after carrying out the anti-penetration injection, also comprise: remove first mask; Form second mask on described grid substance layer, this second mask blocks memory cell areas and at the grid of peripheral circuit area definition logic transistor; With described second mask is the barrier layer, and etching forms the grid of logic transistor; Remove second mask.
Further, after forming grid substance layer, and before forming first mask, also comprise: form second mask on described grid substance layer, this second mask blocks memory cell areas and at the grid of peripheral circuit area definition logic transistor; With described second mask is the barrier layer, and etching forms the grid of logic transistor; Remove second mask.
Further, described grid substance layer comprises gate dielectric layer and position polysilicon layer thereon.
Further, described second mask is hard mask.
Further, described second mask is made of the nitride of silicon.
Further, described first mask is hard mask.
Further, described first mask is made of the nitride of silicon.
As seen, the manufacture method of above semiconductor memory is utilized the grid array in different mask independence define storage units district and the logic transistor grid of periphery circuit region, and the mask of reservation definition grid array is as the barrier layer of APT injection, with the thickness of minimizing grid array and the correlation degree of APT injection, thereby reduce the thickness of grid array according to other performance requirements of memory cell, and then improve the integrated level of semiconductor memory.
Description of drawings
Fig. 1 is a kind of part planar structure schematic diagram of semiconductor memory;
Fig. 2 to Fig. 7 is the manufacturing process schematic diagram of semiconductor memory in the existing technology;
Fig. 8 is the manufacturing process schematic diagram of the semiconductor memory that one embodiment of the invention provided;
The manufacturing process schematic diagram of the semiconductor memory that Fig. 9 is provided for the embodiment of the invention one;
The manufacturing process schematic diagram of the semiconductor memory that Figure 10 is provided for the embodiment of the invention two;
Figure 11 to Figure 18 is the manufacture process schematic diagram according to the semiconductor memory of the embodiment of the invention one.
Embodiment
For technical characterictic of the present invention is become apparent, below in conjunction with accompanying drawing and embodiment, the present invention will be further described.
In conventional semiconductor memory manufacture process; utilize same mask to come the grid array in define storage units district and the logic transistor grid of periphery circuit region; then utilize another mask protection periphery circuit region; and with the grid array of memory cell areas as the barrier layer, finish the anti-penetration between the memory cell (APT) injected.Because grid array in the APT injection process, has played the effect on barrier layer, so its thickness is had certain requirement.Yet the requirement on this thickness must influence the further raising of semiconductor memory integrated level.And if on grid array, form the barrier layer, just can share the effect on the barrier layer of grid array, and the correlation degree between the thickness that reduces grid array and the APT injection.Unnecessary operation certainly will to be increased but do like this.For this reason, the present inventor fully takes into account the utilization of mask, promptly utilizes two masks to come the grid array in define storage units district and the logic transistor grid of periphery circuit region respectively, and keeps the barrier layer of the mask of definition grid array as the APT injection.So, with respect to existing technology, neither increase the quantity of mask, do not increase process yet, and, carry out PROCESS FOR TREATMENT easilier according to their different performance requirement with the logic transistor grid separate processes of the grid array and the periphery circuit region of memory cell areas.Specifically, in the present invention, the barrier layer that the mask of definition grid array can be injected as APT, after finishing APT and injecting again with its removal, so, just can reduce the correlation degree that grid array and APT inject, thereby reduce the thickness of grid array according to other performance requirements.
Specifically please refer to Fig. 8, it is semiconductor memory manufacturing process schematic diagram that one embodiment of the invention provided.As shown in the figure, the manufacture method of this semiconductor memory comprises the steps:
S1: the Semiconductor substrate with memory cell areas and periphery circuit region is provided;
S2: on Semiconductor substrate, form grid substance layer;
S3: form first mask on grid substance layer, this first mask blocks periphery circuit region and defines grid array in memory cell areas;
S4: with first mask is the barrier layer, and etching forms grid array;
S5: with first mask is the barrier layer, carries out anti-penetration (APT) and injects.
As seen, in above step, utilizing first mask to define grid array, and after finishing the etching of grid array, do not removing first mask at once; But continuation is the barrier layer with first mask, carries out APT and injects.So, with respect to prior art, first mask has been shared grid array injects the barrier layer as APT effect greatly, make that the thickness of grid array and the correlation degree that APT injects are reduced greatly, thereby can reduce the thickness of grid array according to other performance requirements of memory cell, and then improve the integrated level of semiconductor memory.
In above step, the definition and the etching of memory cell areas grid array have been finished, and the definition of the logic transistor grid of periphery circuit region and etching utilize another mask to finish, so just, the processing of two kinds of grid structure branches of memory cell areas and periphery circuit region can being come is carried out PROCESS FOR TREATMENT easilier according to its performance requirement separately.And the definition of these two kinds of grid structures and etching order can be changed, so in following two embodiment, the grid array that has provided memory cell areas respectively is defined in preceding logic transistor grid with periphery circuit region and defines two kinds of situations the preceding.
Embodiment one:
Please refer to Fig. 9, in its given semiconductor memory manufacturing process schematic diagram, the definition of memory cell areas grid array be etched in before, the definition of periphery circuit region logic transistor grid be etched in after, specific as follows:
S11: the Semiconductor substrate with memory cell areas and periphery circuit region is provided;
S12: on Semiconductor substrate, form grid substance layer;
S13: form first mask on grid substance layer, this first mask blocks periphery circuit region and defines grid array in memory cell areas;
S14: with first mask is the barrier layer, and etching forms grid array;
S15: with first mask is the barrier layer, carries out anti-penetration (APT) and injects;
S16: remove first mask;
S17: form second mask on grid substance layer, this second mask blocks memory cell areas and at the grid of peripheral circuit area definition logic transistor;
S18: with second mask is the barrier layer, and etching forms the grid of logic transistor;
S19: remove second mask.
Embodiment two:
Please refer to Figure 10, in its given semiconductor memory manufacturing process schematic diagram, the definition of periphery circuit region logic transistor grid be etched in before, the definition of memory cell areas grid array be etched in after, specific as follows:
S21: the Semiconductor substrate with memory cell areas and periphery circuit region is provided;
S22: on Semiconductor substrate, form grid substance layer;
S23: form second mask on grid substance layer, this second mask blocks memory cell areas and at the grid of peripheral circuit area definition logic transistor;
S24: with second mask is the barrier layer, and etching forms the grid of logic transistor;
S25: remove second mask;
S26: form first mask on grid substance layer, this first mask blocks periphery circuit region and defines grid array in memory cell areas;
S27: with first mask is the barrier layer, and etching forms grid array;
S28: with first mask is the barrier layer, carries out anti-penetration (APT) and injects;
S29: remove first mask.
In order to allow above process become apparent, be example with embodiment one below, contrast Figure 11 to Figure 12 is described in detail, and in the accompanying drawing of the following stated, (a) be along the given structural representation of A-A direction among Fig. 1, and (b) be along the given structural representation of B-B direction among Fig. 1:
At first, as Figure 11, provide the Semiconductor substrate 10 with memory cell areas 100 and periphery circuit region 200 (step S11).
Then, as Figure 12, form grid substance layer 20 (step S12) on Semiconductor substrate, this grid substance layer 20 comprises gate dielectric layer 21,23 and position polysilicon layer 22 thereon usually.As shown in the figure, in memory cell areas 100, gate dielectric layer 21 often is ONO (silica-silicon-nitride and silicon oxide) structure, with the savings electric charge, realizes the storage of data; And at periphery circuit region 200, gate dielectric layer 23 is generally silicon oxide layer.Simple its forming process of describing: at first on Semiconductor substrate 10, form ono dielectric layer 21; Then by silica, silicon nitride etch, remove in the periphery circuit region ONO layer away from the silicon nitride and the silicon oxide layer of Semiconductor substrate, only keep silicon oxide layer on the Semiconductor substrate as gate dielectric layer 23; Afterwards, deposit spathic silicon layer 22 on gate dielectric layer 21,23.
Then, as Figure 13, form first mask 30 on grid substance layer 20, this first mask 30 blocks periphery circuit region 200 and defines grid array 40 (step S13) in memory cell areas 100.So, can be the barrier layer just with first mask 30, etching forms grid array 40 (step S14) as shown in figure 14.Keeping first mask 30, is the barrier layer with it, as Figure 15, carries out APT and injects (step S15).Like this, the APT that first mask 30 has been shared grid array 40 injects the task on barrier layer, makes the thickness of grid array 40 no longer be subject to APT and injects, and carries out APT and injects needed mask but also can omit.
After finishing the APT injection,, remove first mask 30 (step S16) as Figure 16.Then, as Figure 17, form second mask 50 on grid substance layer 20, this second mask 50 blocks memory cell areas 100 and defines the grid 60 (step S17) of logic transistors at periphery circuit region 200.Then, as Figure 18, be the barrier layer with second mask 50, etching forms the grid 60 (step S18) of logic transistor; Remove second mask 50 (step S19) afterwards, finish the definition and the etching of the grid of periphery circuit region 200 logic transistors.
In above step, first mask 30 and second mask 50 can be selected hard mask for use, and it can be made of the nitride of silicon, inject the influence for memory cell well to stop APT.
In addition, before the manufacturing of carrying out grid structure (grid 60 that comprises grid array 40 and logic transistor), need make bit line BL in the memory cell areas 100 of Semiconductor substrate 10, to constitute memory cell arrays jointly with grid array 40, and the manufacture craft of bit line BL is well known to those skilled in the art, and does not repeat them here.And after the manufacturing of finishing grid structure (grid 60 that comprises grid array 40 and logic transistor), also need to carry out some subsequent techniques, comprising: logic transistor source, leakage are mixed; The formation of interlayer dielectric layer (ILD); The photoetching of contact hole and etching; The deposits tungsten connector also carries out the chemico-mechanical polishing of tungsten; The sputter of metal interconnection layer, photoetching and etching, the deposition of passivation dielectric layer, photoetching and etching or the like.These all are technology well-known to those skilled in the art, and those skilled in the art certainly as can be known, and according to the number of plies of required metal interconnection, some steps wherein need repeatedly repeat, and do not repeat them here.
The concrete implementation procedure of embodiment two is similar to embodiment one, and those skilled in the art can obtain the detailed implementation process of this embodiment two according to the narration of embodiment one, do not repeat them here.
In sum, above embodiment utilizes the grid array in different mask independence define storage units district and the logic transistor grid of periphery circuit region, and keeps the barrier layer of the mask of definition grid array as the APT injection.So, with respect to prior art, neither increase the quantity of mask, do not increase process yet, and, carry out PROCESS FOR TREATMENT easilier according to its performance requirement separately with the grid array of the memory cell areas of different structure and the logic transistor grid separate processes of periphery circuit region.Specifically, the barrier layer of the mask of grid array as the APT injection will be defined, after finishing APT and injecting again with its removal, to reduce the correlation degree that grid array thickness and APT inject, thereby reduce the thickness of grid array according to other performance requirements, and then improve the integrated level of semiconductor memory.
, be not that protection scope of the present invention should be as the criterion with the scope that claims are contained in order to qualification the present invention below only for for example.
Claims (8)
1. the manufacture method of a semiconductor memory is characterized in that, comprising:
Semiconductor substrate with memory cell areas and periphery circuit region is provided;
On described Semiconductor substrate, form grid substance layer;
Form first mask on described grid substance layer, this first mask blocks periphery circuit region and defines grid array in memory cell areas;
With described first mask is the barrier layer, and etching forms grid array;
With described first mask is the barrier layer, carries out anti-penetration and injects.
2. the manufacture method of semiconductor memory according to claim 1 is characterized in that, after carrying out the anti-penetration injection, also comprises:
Remove first mask;
Form second mask on described grid substance layer, this second mask blocks memory cell areas and at the grid of peripheral circuit area definition logic transistor;
With described second mask is the barrier layer, and etching forms the grid of logic transistor;
Remove second mask.
3. the manufacture method of semiconductor memory according to claim 1 is characterized in that, after forming grid substance layer, and before forming first mask, also comprises:
Form second mask on described grid substance layer, this second mask blocks memory cell areas and at the grid of peripheral circuit area definition logic transistor;
With described second mask is the barrier layer, and etching forms the grid of logic transistor;
Remove second mask.
4. the manufacture method of semiconductor memory according to claim 1 is characterized in that, described grid substance layer comprises gate dielectric layer and position polysilicon layer thereon.
5. according to the manufacture method of claim 2 or 3 described semiconductor memories, it is characterized in that described second mask is hard mask.
6. the manufacture method of semiconductor memory according to claim 5 is characterized in that, described second mask is made of the nitride of silicon.
7. the manufacture method of semiconductor memory according to claim 1 is characterized in that, described first mask is hard mask.
8. the manufacture method of semiconductor memory according to claim 5 is characterized in that, described first mask is made of the nitride of silicon.
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| CN200910045243A CN101777515A (en) | 2009-01-13 | 2009-01-13 | Manufacturing method of semiconductor memory |
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| CN200910045243A CN101777515A (en) | 2009-01-13 | 2009-01-13 | Manufacturing method of semiconductor memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017252A (en) * | 2015-12-15 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Integrated circuit structure and method with solid-state diffusion |
| CN110890328A (en) * | 2018-09-11 | 2020-03-17 | 长鑫存储技术有限公司 | Method for forming semiconductor memory |
-
2009
- 2009-01-13 CN CN200910045243A patent/CN101777515A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017252A (en) * | 2015-12-15 | 2017-08-04 | 台湾积体电路制造股份有限公司 | Integrated circuit structure and method with solid-state diffusion |
| CN107017252B (en) * | 2015-12-15 | 2020-01-10 | 台湾积体电路制造股份有限公司 | Integrated circuit structure with solid phase diffusion and method |
| US10861937B2 (en) | 2015-12-15 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure and method with solid phase diffusion |
| US11749720B2 (en) | 2015-12-15 | 2023-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure and method with solid phase diffusion |
| CN110890328A (en) * | 2018-09-11 | 2020-03-17 | 长鑫存储技术有限公司 | Method for forming semiconductor memory |
| CN110890328B (en) * | 2018-09-11 | 2022-03-18 | 长鑫存储技术有限公司 | Method for forming semiconductor memory |
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Application publication date: 20100714 |