CN101776933B - Cold and warm starting decision circuit, device and switching equipment - Google Patents
Cold and warm starting decision circuit, device and switching equipment Download PDFInfo
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- CN101776933B CN101776933B CN2009102601149A CN200910260114A CN101776933B CN 101776933 B CN101776933 B CN 101776933B CN 2009102601149 A CN2009102601149 A CN 2009102601149A CN 200910260114 A CN200910260114 A CN 200910260114A CN 101776933 B CN101776933 B CN 101776933B
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Abstract
The invention discloses a cold and warm starting decision circuit, a device and switching equipment. The circuit comprises a resistor R1, a capacitor C1, a phase reverser U3, a first logic device and a second logic device, wherein the resistor R1 and the capacitor C1 form a charging circuit, the first logic device is used for outputting low level signals to the second logic device when the first input end of the first logic device receives high level signals and the second input end of the first logic device receives low level signals or high level signals skipped through low level, or the first logic device is used for outputting high level signals to the second logic device when the first input end of the first logic device receives low level signals and the second input end of the first logic device receives high level signals, and the second logic device respectively outputs high level signals used as warm starting signals and low level signals used as cold starting signals according to the output of the first logic device, the power supply voltage and the output of the phase reverser. The invention adopts the hardware design of the combination of few logic devices and charging circuits, and has high stability and accurate decision results.
Description
Technical field
The present invention relates to the control field of cold start-up warm start, relate in particular to a kind of decision circuit, device and switch of cold and hot startup.
Background technology
Cold start-up is meant at electronic equipment under the situation that non-transformer is supplied with; A kind of Starting mode that obtains the power supply power supply and start; And warm start is meant electronic equipment each chip in the direct reset circuit under not electric down situation; And after the completion that resets, get into a kind of Starting mode of normal operation once more.In electronic equipment now, basically all can support these two kinds of reset operations simultaneously.Such as: the power initiation button of PC belongs to cold start-up, and CTRL+ALT+DEL belongs to warm start.These two kinds of Starting mode; Can adopt different initialization operations to system respectively, cold start-up needs system according to starting flow process completely all parts to be carried out initialization ability operate as normal, and it is just passable that warm start then only need be carried out initialization to those chips that carried out resetting; If can correctly discern this two kinds of Starting mode; Will make the start-up course of system obtain simplifying, make warm start more a lot of soon, help improving overall efficiency than the toggle speed of cold start-up.
The recognition methods of existing relatively several kinds of cold and hot startups commonly used is following:
First kind is the internal memory notation; During warm start; Internal memory can not be reset, if CPU is writing a zone bit in internal memory after the cold start-up, then this zone bit just can not be eliminated when carrying out warm start; Cold start-up then this zone bit then can be eliminated, and CPU just can judge that this time starting is cold start-up or warm start through this zone bit like this.
This detection method exists certain risk, because the inherent characteristics of running software, for fear of the running software fault; In order to tackle this shortcoming, general design is to add to feed the dog circuit, and the feeding-dog signal that provides that lets software not stop is exactly supplied with the chip that resets; Make the chip that resets know that thereby CPU is current also at the normal operation CPU that can not reset, in case can't provide this feeding-dog signal but software goes wrong the time, the chip that the resets CPU that will automatically reset; The resetting to restart and belong to warm start of this moment, but when software goes wrong will the maloperation internal memory; Cause this cold and hot startup zone bit to be rewritten, thus the disconnected cold and hot startup type of erroneous judgement.And the uncertainty of internal memory itself and failure rate also are also to be higher than general device, so should design have bigger instability.
Second kind is the method for CPLD self-initialize; This method is utilized the own SDRAM construction characteristic of some CPLD; Make its only at power supply electrifying the time (during cold start-up) pay initial value just for certain register of CPLD; And after startup, rewrite this value through CPU, startup is cold start-up or warm start to differentiate this time.
The recognition methods of this cold and hot startup equally with first method can receive that the CPU program run is gone wrong and causes the risk of maloperation.
The third is to postpone to go up electrical method: utilize the electric capacity charging principle; Delay powers on; So that to postpone the skip signal (this signal only in cold start-up time just can occur) of back power supply at reseting period, and utilize this signal to come cold and hot startup zone bit of initialization (as: initialization value is 0).After the completion that resets; CPU just can confirm that this time startup is cold start-up through reading this sign; And CPU should change into 1 by cold and hot startup zone bit through software setting more subsequently, so that CPU can learn that this zone bit is 1 during next warm start, thereby knowing this time to start is warm start.
The same participation that all needs CPU of this detection method with first and second kind; Increased the uncertainty of judging; And the power supply delay circuit utilizes the electric capacity charging principle to realize, can make the power supply signal after the delay too mild and unstable, is difficult for by correct stable collection and judgement.
Summary of the invention
The embodiment of the invention provides a kind of decision circuit that uses cold and hot startup hard-wired, simple in structure, in order to realize stablizing, the warm start and the cold start-up of judgment device exactly.
The decision circuit of a kind of cold and hot startup that the embodiment of the invention provides comprises:
Resistance R 1 and capacitor C 1, said resistance R 1 one ends connect power supply voltage signal, and the other end is through said capacitor C 1 ground connection;
Phase inverter U3, its input end is used to receive reset signal;
First logical device, its first input end is connected with the output terminal of phase inverter U3, and second input end is connected with the intermediate point of resistance R 1 with capacitor C 1; Be used for receiving high level signal when its first input end; And when its second input end receives low level signal or the high level signal after the low level redirect, the output low level signal, or receive low level signal when its first input end; And when its second input end receives high level signal, the output high level signal;
Second logical device; Its first input end links to each other with the output terminal of first logical device; Second input end links to each other with power supply voltage signal; The 3rd input end links to each other with the output terminal of phase inverter U3, is used for when its first input end receives low level signal, and output is as the low level signal of cold start-up signal; Perhaps receive high level signal when its first input end, and its second input end receives high level signal, when rising edge appearred in its 3rd input end signal, output was as the high level signal of heat enable signal.
A kind of device that carries out cold and hot start-up control that the embodiment of the invention provides comprises the decision circuit of the said cold and hot startup that the embodiment of the invention provides.
A kind of switch that the embodiment of the invention provides comprises the aforementioned device that carries out cold and hot start-up control.
The beneficial effect of the embodiment of the invention comprises:
In the decision circuit of the cold and hot startup that the embodiment of the invention provides, device and the switch; Cold and hot startup decision circuit is through adopting the hardware designs of a small amount of logical device and charging circuit combination; When being implemented in cold start-up and warm start, export various signals respectively, and carry out cold and hot startup judgement in the prior art and need CPU or compare with the scheme that software is participated in control; Owing to can not receive the influence that CPU or software running process are made mistakes; Its stable height and result of determination are accurate, and one-piece construction is simple, realize easily.
Description of drawings
The circuit diagram of the decision circuit of the cold and hot startup that Fig. 1 provides for the embodiment of the invention;
The sequential chart of each signal in the decision circuit of the cold and hot startup that Fig. 2 provides for the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of the decision circuit of a kind of cold and hot startup provided by the invention is carried out detailed explanation.
The decision circuit of a kind of cold and hot startup that the embodiment of the invention provides has used a spot of logical device to realize, in the decision process of hot and cold startup, does not need CPU or software to participate in.
The decision circuit of the cold and hot startup that the embodiment of the invention provides comprises a resistance R 1,1, one phase inverter U3 of capacitor C, first logical device and second logical device; Wherein:
Resistance R 1 and capacitor C 1, resistance R 1 one ends connect power supply voltage signal, and the other end is through capacitor C 1 ground connection;
Phase inverter U3, its input end is used to receive reset signal;
First logical device, its first input end is connected with the output terminal of phase inverter U3, and second input end is connected with the intermediate point of resistance R 1 with capacitor C 1; Be used for receiving high level signal when its first input end; And when its second input end receives low level signal or the high level signal after the low level redirect, the output low level signal, or receive low level signal when its first input end; And when its second input end receives high level signal, the output high level signal;
Second logical device; Its first input end links to each other with the output terminal of first logical device; Second input end links to each other with power supply voltage signal; The 3rd input end links to each other with the output terminal of phase inverter U3, is used for when its first input end receives low level signal, and output is as the low level signal of cold start-up signal; Perhaps receive high level signal when its first input end, and its second input end receives high level signal, when rising edge appearred in its 3rd input end signal, output was as the high level signal of heat enable signal.
In the embodiment of the invention; First logical device for example can adopt the Sheffer stroke gate rest-set flip-flop or can realize other logical devices of identity logic function, and second logical device for example can adopt d type flip flop or can realize other logical devices of identity logic function.Can adopt the logical block combination that can realize above-mentioned first logical device and the second logical device logic function simultaneously, the embodiment of the invention is not done qualification to this yet.
Below, be the not gate rest-set flip-flop with first logical device, second logical device is that d type flip flop is decision circuit and the principle of work thereof that example describes the cold and hot startup that the embodiment of the invention provides.
As shown in Figure 1, the decision circuit of the cold and hot startup that the embodiment of the invention provides specifically comprises the charging circuit that logical device phase inverter U3, Sheffer stroke gate rest-set flip-flop and d type flip flop and electric capacity and resistance are formed.Wherein:
The input end of phase inverter U3 is used for receiving the Reset signal that resets;
The S input end of Sheffer stroke gate rest-set flip-flop U1 is electrically connected with the output terminal of phase inverter U3;
The R input end of Sheffer stroke gate rest-set flip-flop U1 is electrically connected with the intermediate point of resistance R 1 and capacitor C 1;
Resistance R 1 one ends link to each other with power supply voltage signal, and the other end is through capacitor C 1 ground connection;
The output terminal of the R input end Sheffer stroke gate rest-set flip-flop of d type flip flop links to each other, and the D input end of d type flip flop links to each other with power supply voltage signal, and the input end of clock of d type flip flop links to each other with the output terminal of phase inverter U3; The Q output terminal of d type flip flop is used to export the signal value of cold start-up or warm start.
In the decision circuit of above-mentioned cold and hot startup:
The effect of phase inverter is that reset signal RESET is carried out anti-phase, generates the U1_S signal, inputs to the S input end of Sheffer stroke gate rest-set flip-flop U1;
Resistance R 1 is after power supply electrifying with the effect of the charging circuit that capacitor C 1 is formed, and forms the R input end that a U1_R signal inputs to the Sheffer stroke gate rest-set flip-flop, and is as shown in Figure 2, this U1_R signal from be 0 continued the very of short duration time after, saltus step becomes 1.
of Sheffer stroke gate rest-set flip-flop exports U2_R signal and inputs to the R input end of d type flip flop; The U2 signal is as shown in Figure 2.
The D input end of d type flip flop links to each other with power supply voltage signal VDD signal, and the U2_D signal among Fig. 1 between VDD signal input part to the D input end is identical with the VDD signal.
The CLK input end of d type flip flop links to each other with the output terminal of phase inverter U3, and the signal U2_CLK signal between the CLK input end in U3 output terminal to the d type flip flop among Fig. 1 is identical with U1_S.
Below in conjunction with the sequential of each signal in the decision circuit of cold and hot startup shown in Figure 2, the principle of work of the decision circuit of the cold and hot startup that the embodiment of the invention provides is described.
In embodiments of the present invention; Carry out key that cold and hot startup judges and be to cause effective reset signal RESET (cold start-up) at power supply electrifying and accomplish electric situation under the not appearance and when producing effective reset signal RESET (warm start), producing and export a different marking signal respectively is cold start-up or warm start with differentiation with having powered on.
As shown in Figure 2, above-mentioned decision process can be divided into following four-stage:
Phase one: power supply electrifying, cold start-up stage;
Power supply one powers on, and power supply voltage signal VDD promptly is continuously 1;
In power supply electrifying, the RESET signal can from 0 when electrification reset finishes redirect be 1;
No matter be in cold start-up stage or warm start stage; No matter that is to say is to reset owing to what cold start-up triggered; What still warm start triggered resets; The RESET signal all can occur becoming earlier to become for 1 stage after 0, and is 0 lasting time to be generally for example 150ms (also crying reset time during this period of time) of a fixing value.
In this stage, behind the RESET signal process phase inverter U3, the waveform of the U1_S signal of generation is just in time opposite with the RESET signal, and it is 1 that the U1_S signal begins in cold start-up, resets after the end, and redirect is 0;
Charging circuit as shown in Figure 2, that resistance R 1 and resistance R 2 are formed makes the U1_R signal of R input end input of Sheffer stroke gate rest-set flip-flop not be one and is continuously 1 signal, but one has continued the of short duration time after (for example being 1ms) by 0 saltus step again becomes 1 signal.
The truth table of following table 1 right and wrong door rest-set flip-flop:
Table 1
The embodiment of the invention has been utilized the characteristics of Sheffer stroke gate rest-set flip-flop just; Exactly under S is input as 1 situation; R is 0 situation as long as occurred; Then no matter the input of back R is 0 or 1; Output
will be 0 always; Only if S be input as 0, R be input as 1,
just can export 1, when
is output as zero; D type flip flop also can correspondingly export 0; Be the judgement sign of cold start-up, therefore, the charging circuit that need form by R1 and C1; According to supply voltage, forming one is 1 signal U1_R from 0 redirect.
In the cold start-up stage; Because the U1_S signal is 1; It is 0 that the U1_R signal begins; Be 1 then, according to above-mentioned table 1,
of Sheffer stroke gate rest-set flip-flop output is 0 always;
The D input end of d type flip flop connects power supply voltage signal VDD, therefore remains 1 in the cold start-up stage; According to following table 2 is the truth table 2 of d type flip flop; Can find out the signal 0 of
output identification cold start-up of d type flip flop.
Table 2
Subordinate phase, cold start-up stage finish, before warm start begins.
After cold start-up was accomplished, as long as power supply is not electric down, resetting afterwards all was warm start.
After the cold start-up stage finished, as shown in Figure 2, the VDD signal was continuously 1;
Capacitor C 1 charging is accomplished in the phase one, and the U1_R signal is continuously 1;
Reset after the completion, the RESET signal is 1, and beginning up to warm start can redirect be 0; Correspondingly, the U1_S signal is 0 in this stage;
Truth table 1 according to Sheffer stroke gate rest-set flip-flop U1; When the S input end is 0; The R input end is 1 o'clock, and
is output as 1; Just d type flip flop R input end U2_R becomes 1;
The U2_D signal is that the VDD signal also is 1 in this stage, and just the D input end of d type flip flop is 1; From truth table 2; Can find out; D type flip flop is when fixed level;
output terminal output of d type flip flop remains unchanged, and is maintained 0; That is to say, in subordinate phase, the still signal 0 of cold start-up of d type flip flop output.
Three phases, warm start stage;
In this stage, the VDD signal is continuously 1;
Because capacitor C 1 charging is accomplished in the phase one, the U1_R signal remains 1;
Reset signal RESET signal is 0 from 1 redirect, continues the 150ms (reset time) that sets;
Correspondingly, the U1_S signal is 1 from 0 redirect, a rising edge occurs, continues the 150ms that sets.
According to truth table 1, this stage of R input end of Sheffer stroke gate rest-set flip-flop U1 is 1; The S input end is 1 in this stage; Therefore,
output terminal of Sheffer stroke gate rest-set flip-flop U1 is 1 for remaining unchanged;
The signal U2_R of the R input end input of d type flip flop is 1; The signal U2_D of the D input end input of d type flip flop is 1; And rising edge has appearred in the U1_S signal of CLK signal input part input when warm start begins; Truth table 2 according to d type flip flop can know that d type flip flop can be exported signal 1, just identifies the signal of warm start.
After stage, warm start finish, before warm start begins next time;
As can be seen from Figure 2, after warm start finished, the U1_R signal remained 1, and the U1_S signal is 0, and this moment, the output of Sheffer stroke gate rest-set flip-flop 1; What just the R input end of d type flip flop was imported is signal 1; The signal U2_D of the D input end input of d type flip flop also is 1; And the clock signal of CLK input end input is a fixed level; Therefore, the output of d type flip flop meeting can keep consistent with the output of phase III, i.e. the id signal 1 of heat outputting startup.
As can be seen from Figure 2, began before warm start begins in cold start-up, the sign that d type flip flop all can be exported cold start-up is a signal 0; As long as warm start occurs; Then as long as power supply is not electric down, d type flip flop can be exported signal 1 always, reaches the purpose of judging cold start-up and warm start.
In the decision circuit of the cold and hot startup that the embodiment of the invention provides, the capacitance of the resistance value of resistance R 1 and capacitor C 1 need satisfy following formula:
t＝RC*Ln[(V
1-V
0)/(V
1-V
t)]；
In the following formula: t is that the voltage of capacitor C 1 rises to the duration of charging that the Sheffer stroke gate rest-set flip-flop is identified as the maximum voltage value of signal 0 from 0V;
R is the resistance value of resistance R 1;
C is the capacitance of capacitor C 1;
V
0Initial voltage value (being 0) for capacitor C 1;
V
1Be supply voltage value;
V
tBe identified as the maximum voltage value of signal 0 for the Sheffer stroke gate rest-set flip-flop.
Because not gate rest-set flip-flop U1 can be identified as the signal below the 0.8V voltage signal 0 usually, and the signal more than the 0.8V voltage is identified as signal 1, therefore, above-mentioned V
tGeneral value is 0.8V;
In the specific implementation, can jump to short reaction time of high level from low level according to the Sheffer stroke gate rest-set flip-flop, the charging circuit that R1 and C1 are formed for example is set to 1ms to the duration of charging of capacitor C 1 from 0V to 0.8V.
Suppose that supply voltage is 3.3V, with V
0=0; V
1=3.3V; V
t=0.8V; In the value substitution following formula of t=0.001s, the product of resistance value R that obtains capacitance C and the resistance R 1 of capacitor C 1 need satisfy: R*C=0.0036.If choosing resistance R 1 is the resistance of 10000 Ω, then capacitor C 1 need just can satisfy the requirement of 1ms time with the electric capacity of 0.36 microfarad.
Certainly; The charging circuit of being made up of R1 and C1 in the decision circuit of the cold and hot startup that the embodiment of the invention provides also can adopt the mode of other charging circuits commonly used to realize, for example between capacitor C 1 and ground; Increase modes such as inductance L, the embodiment of the invention does not limit this.
The capacitance of resistance value and capacitor C 1 through above-mentioned adjustment resistance R 1; The U1_R signal that can control the cold start-up stage is 0 duration length; But in actual environment, because influences such as capacitance-resistance error, power supply shakes, the U1_R signal can be an extremely unsettled signal usually.Therefore; The inventor is when this circuit of design; Consider the R end that the U1_R signal is connected to Sheffer stroke gate rest-set flip-flop U1, again the U2_R signal of not gate rest-set flip-flop U1 output is connected to the R input end of d type flip flop U2, rather than directly the U1_R signal is connected to the input R of d type flip flop U2.Can know the description of Sheffer stroke gate rest-set flip-flop like the front; For Sheffer stroke gate rest-set flip-flop U1; The U1_S signal of its S input end input remained 1 o'clock; To occur be 0 situation as long as the U1_R signal of its R input end input has; Then no matter back R is 0 or 1; Its
output terminal output signal will remain 0 always, so the main effect of U1 is exactly the instability that is used for eliminating the U1_R signal, prevents that unsettled signal from causing final misjudgment.
The embodiment of the invention also provides a kind of control device of cold and hot startup, comprises the decision circuit of the described cold and hot startup of the embodiment of the invention, is used for carrying out corresponding reset operation according to the cold start-up of the decision circuit of hot and cold startup output or the signal of warm start.
The control device of the above-mentioned cold and hot startup that the embodiment of the invention provides can be applied to the equipment that all support cold and hot startup, like switch, router and PC etc.
The embodiment of the invention also provides a kind of switch, is provided with the control device of above-mentioned cold and hot startup in this switch.
In the decision circuit of the cold and hot startup that the embodiment of the invention provides, through the hardware designs that adopts a small amount of logical device and charging circuit to make up, when being implemented in cold start-up and warm start; Export various signals respectively; With carry out cold and hot startup judgement in the prior art and need CPU or compare with the scheme that software is participated in control owing to can not receive the influence that CPU or software running process are made mistakes, its stable height and result of determination are accurate; And one-piece construction is simple, realizes easily.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. the decision circuit of a cold and hot startup is characterized in that, comprising:
Resistance R 1 and capacitor C 1, said resistance R 1 one ends connect power supply voltage signal, and the other end is through said capacitor C 1 ground connection;
Phase inverter U3, its input end is used to receive reset signal;
First logical device, its first input end is connected with the output terminal of phase inverter U3, and second input end is connected with the intermediate point of resistance R 1 with capacitor C 1; Be used for receiving high level signal when its first input end; And when its second input end receives low level signal or the high level signal after the low level redirect, the output low level signal, or receive low level signal when its first input end; And when its second input end receives high level signal, the output high level signal;
Second logical device; Its first input end links to each other with the output terminal of first logical device; Second input end links to each other with power supply voltage signal; The 3rd input end links to each other with the output terminal of phase inverter U3, is used for when its first input end receives low level signal, and output is as the low level signal of cold start-up signal; Perhaps receive high level signal when its first input end, and its second input end receives high level signal, when rising edge appearred in its 3rd input end signal, output was as the high level signal of heat enable signal.
2. circuit as claimed in claim 1 is characterized in that, said first logical device is the Sheffer stroke gate rest-set flip-flop, and its first input end is the S input end, and its second input end is the R input end.
3. circuit as claimed in claim 1 is characterized in that, said second logical device is a d type flip flop, and its first input end is the R input end, and its second input end is the D input end, and its 3rd input end is a clock CLK input end.
4. circuit as claimed in claim 1 is characterized in that, in the charging circuit of resistance R 1 and capacitor C 1 composition, the resistance value of the capacitance of capacitor C 1, resistance R 1 satisfies formula:
t＝RC*Ln[(V
1-V
0)/(V
1-V
t)]；
In the following formula: t is that capacitor C 1 voltage rises to the duration of charging that first logical device is identified as the maximum voltage value of signal 0 from 0V;
R is the resistance value of resistance R 1;
C is the capacitance of capacitor C 1;
V
0Initial voltage value for capacitor C 1;
V
1Be supply voltage value;
V
tIt is the maximum voltage value that first logical device is identified as signal 0.
5. circuit as claimed in claim 1 is characterized in that, also comprises inductance, is connected between said electric capacity and the ground.
6. a device that carries out cold and hot start-up control is characterized in that, comprises the decision circuit like each described cold and hot startup of claim 1-5.
7. a switch is characterized in that, comprises the device that carries out cold and hot start-up control as claimed in claim 6.
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| CN103182996B (en) * | 2011-12-31 | 2015-07-15 | 上海汽车集团股份有限公司 | Device for identifying cold-heat start of system and automobile |
| US9191185B2 (en) * | 2014-01-27 | 2015-11-17 | Qualcomm Incorporated | Differential bang-bang phase detector using standard digital cells |
| CN106627435A (en) * | 2016-12-06 | 2017-05-10 | 上汽通用汽车有限公司 | Method and device for providing steady voltage |
| CN106696996B (en) * | 2017-01-23 | 2018-10-12 | 株洲中车时代电气股份有限公司 | A kind of train fault report method and system |
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|---|---|---|---|---|
| CN1540503A (en) * | 2003-04-23 | 2004-10-27 | 华为技术有限公司 | System of capable of identifying cold boot and warm boot, and method for quickenning speed of starting up system |
| CN1627269A (en) * | 2003-12-12 | 2005-06-15 | 华为技术有限公司 | Method for recognizing cold booting or warm booting system |
| CN101008900A (en) * | 2007-01-31 | 2007-08-01 | 华为技术有限公司 | Method and device for distinguish cool start and hot start |
| CN101046702A (en) * | 2006-03-31 | 2007-10-03 | 鸿富锦精密工业（深圳）有限公司 | Start control device and method for micro-controller |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540503A (en) * | 2003-04-23 | 2004-10-27 | 华为技术有限公司 | System of capable of identifying cold boot and warm boot, and method for quickenning speed of starting up system |
| CN1627269A (en) * | 2003-12-12 | 2005-06-15 | 华为技术有限公司 | Method for recognizing cold booting or warm booting system |
| CN101046702A (en) * | 2006-03-31 | 2007-10-03 | 鸿富锦精密工业（深圳）有限公司 | Start control device and method for micro-controller |
| CN101008900A (en) * | 2007-01-31 | 2007-08-01 | 华为技术有限公司 | Method and device for distinguish cool start and hot start |
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