CN101776827A - Pixel array, polymer stable alignment LCD panel and optoelectronic device - Google Patents
Pixel array, polymer stable alignment LCD panel and optoelectronic device Download PDFInfo
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- CN101776827A CN101776827A CN201010102372A CN201010102372A CN101776827A CN 101776827 A CN101776827 A CN 101776827A CN 201010102372 A CN201010102372 A CN 201010102372A CN 201010102372 A CN201010102372 A CN 201010102372A CN 101776827 A CN101776827 A CN 101776827A
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Abstract
The invention provides a pixel array, a polymer stable alignment LCD panel and an optoelectronic device; wherein the pixel array comprises multiple scanning lines, multiple data lines and multiple sub-pixels. The sub-pixels are respectively electrically connected with corresponding scanning lines and data lines and each sub-pixel arranged in n array comprises a first switch, a second switch, a first pixel electrode, a second pixel electrode and a third switch. The first switch and the second switch are electrically connected with the n scanning line and the m data line. The first pixel electrode is electrically connected with the first switch. The second pixel electrode is electrically connected with a signal output terminal of the second switch and the first pixel electrode is provided with a first opening located above the signal output terminal. The third switch is electrically with the (n+1) scanning line and the second pixel electrode and the second pixel electrode is provided with a second opening located above an electrical levitated terminal of the third switch.
Description
Technical field
The invention relates to a kind of pel array, and particularly relevant for a kind of pel array, polymer-stabilized alignment liquid crystal display panel and electrooptical device with good display quality.
Background technology
Along with LCD constantly develops towards large-sized demonstration specification, in order to overcome the visual angle problem under the large scale demonstration, the wide viewing angle technology of display panels also must ceaselessly improve and break through.Wherein, multidomain vertical alignment type (Multi-domain Vertical Alignment, MVA) (Polymer stabilized alignment, PSA) display panels is existing common wide viewing angle technology for display panels and polymer-stabilized alignment.In order to improve the colour cast problem (color washout) in the display panels, having into, rank type multidomain vertical alignment type (Advanced-MVA) display panels is suggested, it mainly is that each sub-pixel area is divided into main viewing area (main display region) and sub-viewing area (sub-display region), and through suitable circuit design and driving method, make main viewing area and sub-viewing area in the same sub-pixel have different cross-pressures respectively, to improve the colour cast problem.In the prior art, the design concept that each sub-pixel area is divided into main viewing area and sub-viewing area is applied in the polymer-stabilized alignment liquid crystal display panel.
Fig. 1 is a kind of equivalent circuit diagram of pel array, and Fig. 2 is the synoptic diagram of single sub-pixel among Fig. 1.Please refer to Fig. 1 and Fig. 2, pel array 100 comprises a plurality of sub-pixel P1, and each sub-pixel P1 comprises a first film transistor T FT1, one second thin film transistor (TFT) TFT2, one the 3rd thin film transistor (TFT) TFT3, the first pixel electrode ITO1 that is electrically connected with the first film transistor T FT1 and the second pixel electrode ITO2 that is electrically connected with the second thin film transistor (TFT) TFT2.The first pixel electrode ITO1 can and form one first storage capacitors Cs1 with common line COM1 coupling, and the first pixel electrode ITO1 can and form one first liquid crystal capacitance CLC1 with a common electrode (indicating) coupling on the subtend substrate (as colored optical filtering substrates).Similarly, the second pixel electrode ITO2 can and form one second storage capacitors Cs2 with common line COM2 coupling, and the second pixel electrode ITO2 can and form one second liquid crystal capacitance CLC2 with common electrode (indicating) coupling on the subtend substrate (as colored optical filtering substrates).
From Fig. 1 and Fig. 2 as can be known, with sub-pixel P1 that sweep trace SL (n-1) is electrically connected in, the grid G 1 of the first film transistor T FT1 and the second thin film transistor (TFT) TFT2, G2 can be electrically connected with sweep trace SL (n-1), and the grid G 3 of the 3rd thin film transistor (TFT) TFT3 can be electrically connected with next bar sweep trace SL (n).In addition, the source S 3 of the 3rd thin film transistor (TFT) TFT3 is electrically connected with the second pixel electrode ITO2, and the drain D 3 of the 3rd thin film transistor (TFT) TFT3 and the first pixel electrode ITO1 are coupled into the first capacitor C cs-a, and the common line COM1 of the drain D 3 of the 3rd thin film transistor (TFT) TFT3 and first pixel electrode ITO1 below is coupled into the second capacitor C cs-b.When applying a high voltage (Vgh) when sweep trace SL (n-1), image data can see through data line DL (m-1), DL (m) and write in the sub-pixel that is connected with sweep trace SL (n-1), at this moment, the first pixel electrode ITO1 is identical with the voltage of the second pixel electrode ITO2.Then, when applying a high voltage when sweep trace SL (n), the first capacitor C cs-a and the second capacitor C cs-b can make the voltage of the voltage of the first pixel electrode ITO1 and the second pixel electrode ITO2 different.
Because the drain D 2 of the second thin film transistor (TFT) TFT2 can stride across the first pixel electrode ITO1 and be connected with the second pixel electrode ITO2, therefore just produce a stray capacitance Cx1 between the drain D 2 of the second thin film transistor (TFT) TFT2 and the first pixel electrode ITO1.In addition, because the drain D 3 of the 3rd thin film transistor (TFT) TFT3 can stride across the second pixel electrode ITO2, therefore just produce a stray capacitance Cx2 between the drain D 3 of the 3rd thin film transistor (TFT) TFT3 and the second pixel electrode ITO2.Stray capacitance Cx1, Cx2 can make the voltage differences of the first pixel electrode ITO1 and the second pixel electrode ITO2 draw back amplitude to reduce, cause the colour cast problem to improve effectively.Hold above-mentionedly, how to avoid among the sub-pixel P1 stray capacitance Cx1, Cx2, its necessity is arranged in fact for the influence of display quality.
Summary of the invention
The invention provides a kind of pel array, polymer-stabilized alignment liquid crystal display panel (PSA-LCDpanel) and electrooptical device, it has good display quality.
The invention provides a kind of pel array, it comprises multi-strip scanning line, many data lines and a plurality of sub-pixel.Data line and sweep trace are staggered to define a plurality of subpixel area.Subpixel configuration is in subpixel area, each sub-pixel respectively with sweep trace wherein and wherein a data line be electrically connected, and each sub-pixel that is arranged in the n row comprises one first switch, a second switch, one first pixel electrode, one second pixel electrode and one the 3rd switch.First switch and second switch are electrically connected with n bar sweep trace and m bar data line, and second switch has a signal output part.First pixel electrode is electrically connected with first switch.Second pixel electrode is electrically connected with the signal output part of second switch, and wherein first pixel electrode has at least one first opening that is positioned at the signal output part top.The 3rd switch is electrically connected with (n+1) the bar sweep trace and second pixel electrode, and the 3rd switch has an electrical floating terminal, and second pixel electrode has at least one second opening that is positioned at top, electrical floating terminal.
In an embodiment of the present invention, aforesaid arrangement of subpixels becomes multiple row, and the sub-pixel that is arranged in n row is electrically connected with n bar sweep trace and (n+1) bar sweep trace.
In an embodiment of the present invention, first pixel electrode and second pixel electrode that is arranged in the sub-pixel of n row is positioned between n bar sweep trace and (n+1) bar sweep trace.
In an embodiment of the present invention, each first switch that is arranged in the n row is a first film transistor, first drains and the first film transistor has that a first grid that is electrically connected with n bar sweep trace, first source electrode and that is electrically connected with data line wherein be electrically connected with first pixel electrode.
In an embodiment of the present invention, each second switch that is arranged in the n row is one second thin film transistor (TFT), and second thin film transistor (TFT) have a second grid that is electrically connected with n bar sweep trace, one with second source electrode and aforesaid signal output part that data line is electrically connected wherein.
In an embodiment of the present invention, each the 3rd switch that is arranged in the n row is one the 3rd thin film transistor (TFT), and the 3rd thin film transistor (TFT) has the 3rd grid that is electrically connected with (n+1) bar sweep trace, the 3rd source electrode that is electrically connected with second pixel electrode and aforesaid electrical floating terminal.
In an embodiment of the present invention, aforesaid electrical floating terminal extends to first pixel electrode below.
In an embodiment of the present invention, aforesaid pel array can further comprise the many common lines that are electrically connected to each other, and is distributed in each first pixel electrode and each second pixel electrode below.
In an embodiment of the present invention, aforesaid each common line extends along column direction respectively, and the common line of part that is distributed in below first pixel electrode has first branch that at least one is positioned at first opening below, and the common line of part that is distributed in below second pixel electrode has second branch that at least one is positioned at second opening below.
In an embodiment of the present invention, aforesaid second branch is positioned at below, electrical floating terminal.
In an embodiment of the present invention, aforesaid each first pixel electrode comprises one first electrode part, one second electrode part and one first connecting portion.First connecting portion is between first electrode part and second electrode part, so that first electrode part and second electrode part are separated by two first strip openings that lay respectively at the first connecting portion both sides, wherein first electrode part is connected with second electrode part through first connecting portion.
In an embodiment of the present invention, the area summation of the aforesaid first strip opening is A1, and the overlapping area summation of first pixel electrode and signal output part is A2, and opening ratio A1/ (A1+A2) is greater than 91%.
In an embodiment of the present invention, aforesaid each second pixel electrode comprises a third electrode portion, one the 4th electrode part and one second connecting portion, second connecting portion is between third electrode portion and the 4th electrode part, so that third electrode portion and the 4th electrode part are separated by two second strip openings that lay respectively at the second connecting portion both sides, wherein third electrode portion is connected with the 4th electrode part through second connecting portion.
In an embodiment of the present invention, the area summation of the aforesaid second strip opening is A3, and the overlapping area summation of second pixel electrode and electrical floating terminal is A4, and opening ratio A3/ (A3+A4) is greater than 93%.
In an embodiment of the present invention, aforesaid each first pixel electrode comprises one first electrode part, one second electrode part and a plurality of first connecting portion, first connecting portion is between first electrode part and second electrode part, so that first electrode part and second electrode part are separated by at least one first strip opening between first connecting portion, wherein first electrode part is connected with second electrode part through first connecting portion.
In an embodiment of the present invention, the area of the aforesaid first strip opening is A1, and the overlapping area summation of first pixel electrode and signal output part is A2, and opening ratio A1/ (A1+A2) is greater than 91%.
In an embodiment of the present invention, aforesaid each second pixel electrode comprises a third electrode portion, one the 4th electrode part and a plurality of second connecting portion, second connecting portion is between third electrode portion and the 4th electrode part, so that third electrode portion and the 4th electrode part are separated by at least one second strip opening between second connecting portion, wherein third electrode portion is connected with the 4th electrode part through second connecting portion.
In an embodiment of the present invention, the area of the aforesaid second strip opening is A3, and the overlapping area summation of second pixel electrode and electrical floating terminal is A4, and opening ratio A3/ (A3+A4) is greater than 93%.
The present invention provides a kind of polymer-stabilized alignment liquid crystal display panel (PSA-LCD panel) in addition, and it comprises one first substrate, one second substrate, two polymkeric substance stable alignment layers and a liquid crystal layer.First substrate has aforesaid pel array, and second substrate is disposed at first substrate top, and two polymkeric substance stable alignment layers are disposed at respectively on first substrate and second substrate.Liquid crystal layer is disposed between the polymer-stabilized alignment layer.
The present invention provides a kind of electrooptical device again, and it comprises aforesaid pel array or polymer-stabilized alignment liquid crystal display panel.
Based on above-mentioned, since the present invention in sub-pixel signal output part and electrically adopt open design above the floating terminal, therefore the stray capacitance between first pixel electrode and the signal output part and second pixel electrode can be reduced effectively with stray capacitance between the electrical floating terminal.
Description of drawings
Fig. 1 is a kind of equivalent circuit diagram of pel array;
Fig. 2 is the synoptic diagram of single sub-pixel among Fig. 1;
Fig. 3 is the synoptic diagram of the pel array of first embodiment of the invention;
Fig. 4 is the schematic layout pattern of the pel array of first embodiment of the invention;
Fig. 5 is the synoptic diagram of the pel array of second embodiment of the invention;
Fig. 6 is the schematic layout pattern of the pel array of second embodiment of the invention;
Fig. 7 is the synoptic diagram of polymer-stabilized alignment liquid crystal display panel of the present invention;
Fig. 8 is the synoptic diagram of electrooptical device of the present invention.
Drawing reference numeral:
100,200,200 ': pel array
P1, P2: sub-pixel
SL, SL (n), SL (n+1), SL (n+2): sweep trace
DL, DL (m), DL (m+1): data line
R: subpixel area
TFT1, TFT2, TFT3: on-off element
G1, G2, G3: grid
S1, S2, S3: source electrode
D1, D2, D3: drain electrode
D2 ': signal output part
D3 ': electrical floating terminal
AP1: first opening
AP2: second opening
Ccs-a: first electric capacity
Ccs-b: second electric capacity
Cs1, Cs2: storage capacitors
Cx1, Cx2: stray capacitance
CLC1, CLC2: liquid crystal capacitance
ITO1: first pixel electrode
E1: first electrode part
E2: second electrode part
C1: first connecting portion
ITO2: second pixel electrode
E3: third electrode portion
E4: the 4th electrode part
C2: second connecting portion
COM, COM1, COM2: common line
300: polymer-stabilized alignment liquid crystal display panel
310: the first substrates
320: the second substrates
330,340: the polymer-stabilized alignment layer
350: liquid crystal layer
400: electrooptical device
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
[first embodiment]
Fig. 3 is the synoptic diagram of the pel array of first embodiment of the invention, and Fig. 4 is layout (layout) synoptic diagram of the pel array of first embodiment of the invention.Please refer to Fig. 3 and Fig. 4, the pel array 200 of present embodiment comprises multi-strip scanning line SL (only showing sweep trace SL (n), SL (n+1), SL (n+2) among Fig. 3 and Fig. 4), many data line DL (only showing data line DL (m), DL (m+1) among Fig. 3 and Fig. 4) and a plurality of sub-pixel P2.Aforesaid data line DL and sweep trace SL are interlaced with each other, and defining a plurality of subpixel area R, and each sub-pixel P2 is disposed at respectively in the subpixel area R.It should be noted that the sub-pixel P2 that only shows part among Fig. 3 and Fig. 4, and the quantity of sub-pixel P2 arranged into an array can be done suitable variation according to the image analytic degree of required demonstration.
Each sub-pixel P2 respectively with sweep trace SL wherein and wherein a data line DL be electrically connected.In the present embodiment, sub-pixel P2 is arranged in multiple row, and the sub-pixel P2 that is arranged in n row is electrically connected with n bar sweep trace SL (n) and (n+1) bar sweep trace SL (n+1).In detail, each sub-pixel P2 that is arranged in the n row comprises one first switching TFT 1, a second switch TFT2, one first pixel electrode ITO1, one second pixel electrode ITO2 and one the 3rd switching TFT 3.First switching TFT 1 and second switch TFT2 are electrically connected with n bar sweep trace SL (n) and m bar data line DL (m), and second switch TFT2 has a signal output part D2 '.The first pixel electrode ITO1 is electrically connected with first switching TFT 1.The second pixel electrode ITO2 is electrically connected with the signal output part D2 ' of second switch TFT2, and wherein the first pixel electrode ITO1 has at least one first opening AP1 that is positioned at signal output part D2 ' top.In the present embodiment, the first pixel electrode ITO1 and the second pixel electrode ITO2 that is arranged among the sub-pixel P2 of n row for example is positioned between n bar sweep trace SL (n) and (n+1) bar sweep trace SL (n+1).In addition, the 3rd switching TFT 3 is electrically connected with (n+1) bar sweep trace SL (n+1) and the second pixel electrode ITO2, and the 3rd switching TFT 3 has an electrical floating terminal D3 ', and the second pixel electrode ITO2 has at least one second opening AP2 that is positioned at electrical floating terminal D3 ' top.
From Fig. 3 and Fig. 4 as can be known, each first switching TFT 1 that is arranged in the n row is a first film transistor, and the first film transistor has a first grid G1, one first source S 1 and one first drain D 1.First grid G1 is electrically connected with n bar sweep trace SL (n), and first source S 1 is electrically connected with data line DL wherein, and first drain D 1 then is electrically connected with the first pixel electrode ITO1.In addition, each second switch TFT2 that is arranged in the n row is one second thin film transistor (TFT), and second thin film transistor (TFT) has a second grid G2, second source S 2 and aforesaid second drain D 2.Second grid G2 is electrically connected with n bar sweep trace SL (n), and second source S 2 is electrically connected with data line DL wherein.Second drain D 2 that it should be noted that second thin film transistor (TFT) is aforesaid signal output part D2 '.Each the 3rd switching TFT 3 that is arranged in the n row is one the 3rd thin film transistor (TFT), and the 3rd thin film transistor (TFT) has one the 3rd grid G 3, the 3rd source S 3 and the 3rd drain D 3.The 3rd grid G 3 is electrically connected with (n+1) bar sweep trace SL (n+1), and the 3rd source S 3 is electrically connected with the second pixel electrode ITO2.The 3rd drain D 3 that it should be noted that the 3rd thin film transistor (TFT) is aforesaid electrical floating terminal D3 '.
As shown in Figure 4, each first pixel electrode ITO1 comprises one first electrode part E1, one second electrode part E2 and a plurality of first connecting portion C1, the first connecting portion C1 is between the first electrode part E1 and the second electrode part E2, so that the first electrode part E1 and the second electrode part E2 are separated by at least one first strip opening AP1 between the first connecting portion C1, wherein the first electrode part E1 is connected with the second electrode part E2 through the first connecting portion C1.In addition, each second pixel electrode ITO2 comprises an E3 of third electrode portion, one the 4th electrode part E4 and a plurality of second connecting portion C2, the second connecting portion C2 is between E3 of third electrode portion and the 4th electrode part E4, so that E3 of third electrode portion and the 4th electrode part E4 are separated by at least one second strip opening AP2 between the second connecting portion C2, wherein the E3 of third electrode portion is connected with the 4th electrode part E4 through the second connecting portion C2.Hold above-mentionedly, present embodiment does not limit quantity and the shape of the first connecting portion C1 and the second connecting portion C2.
In the present embodiment, first drain D 1 is electrically connected with the first electrode part E1, and signal output part D2 ' extends between the first electrode part E1 and the second electrode part E2, and is electrically connected with the E3 of third electrode portion.In addition, the 3rd source S 3 is electrically connected with the 4th electrode part E4, and electrically floating terminal D3 ' extends between E3 of third electrode portion and the 4th electrode part E4, and the end of electrical floating terminal D3 ' extends to the below of the second electrode part E2 of the first pixel electrode ITO1.In other words, electrically floating terminal D3 ' can be overlapped with the first pixel electrode ITO1, to be coupled into one first capacitor C cs-a.
For example, the area of the aforesaid first strip opening AP1 is A1, and the overlapping area summation of the first pixel electrode ITO1 and signal output part D2 ' is A2, and opening ratio A1/ (A1+A2) is for example greater than 91%.In addition, the area of the aforesaid second strip opening AP2 is A3, and the overlapping area summation of the second pixel electrode ITO and electrical floating terminal D3 ' is A4, and opening ratio A3/ (A3+A4) is for example greater than 93%.
Because the first pixel electrode ITO1 has the design of the first opening AP1, therefore the overlapping area summation of the first pixel electrode ITO1 and signal output part D2 ' can decline to a great extent because of the first opening AP1, and then reduces the stray capacitance Cx1 between the first pixel electrode ITO1 and the signal output part D2 '.In addition, because the second pixel electrode ITO2 has the design of the second opening AP2, therefore the second pixel electrode ITO2 can decline to a great extent because of the second opening AP2 with the overlapping area summation of electrical floating terminal D3 ', and then reduces the stray capacitance Cx2 between the second pixel electrode ITO2 and the electrical floating terminal D3 '.As stray capacitance Cx1, when Cx2 is lowered, the voltage differences of the first pixel electrode ITO1 and the second pixel electrode ITO2 is drawn back amplitude just can be increased, and therefore can solve the colour cast problem effectively.
Can know from Fig. 4 and to learn that the pel array 200 of present embodiment can further comprise many common line COM that are electrically connected to each other that these common line COM are distributed in each first pixel electrode ITO1 and each second pixel electrode ITO2 below.In detail, the common line COM of each bar extends along column direction respectively, and the common line COM of part that is distributed in below the first pixel electrode ITO1 has first BR1 of branch that at least one is positioned at first opening AP1 below, and the common line COM of part that is distributed in below the second pixel electrode ITO has second BR2 of branch that at least one is positioned at second opening AP2 below.It should be noted that second BR2 of branch is positioned at electrical floating terminal D3 ' below.In other words, electrically floating terminal D3 ' can be overlapped with second BR2 of branch, to be coupled into one second capacitor C cs-b.
[second embodiment]
Fig. 5 is the synoptic diagram of the pel array of second embodiment of the invention, and Fig. 6 is the schematic layout pattern of the pel array of second embodiment of the invention.Please refer to Fig. 5 and Fig. 6, the pel array 200 of the pel array 200 ' of present embodiment and first embodiment is similar, being in the pattern of the first pixel electrode ITO1 and the second pixel electrode ITO2 of the two main difference.
From Fig. 5 and Fig. 6 as can be known, each of present embodiment first pixel electrode ITO1 comprises one first electrode part E1, one second electrode part E2 and one first connecting portion C1.The first connecting portion C1 is between the first electrode part E1 and the second electrode part E2, so that the first electrode part E1 and the second electrode part E2 are separated by two first strip opening AP1 that lay respectively at the first connecting portion C1 both sides, wherein the first electrode part C1 is connected with the second electrode part E2 through the first connecting portion E1.In addition, each second pixel electrode ITO2 comprises an E3 of third electrode portion, one the 4th electrode part E4 and one second connecting portion C2, the second connecting portion C2 is between E3 of third electrode portion and the 4th electrode part E4, so that E3 of third electrode portion and the 4th electrode part E4 are separated by two second strip opening AP2 that lay respectively at the second connecting portion C2 both sides, wherein the E3 of third electrode portion is connected with the 4th electrode part E4 through the second connecting portion C2.
For example, the area summation of the aforesaid first strip opening AP1 is A1, and the overlapping area summation of the first pixel electrode ITO1 and signal output part D2 ' is A2, and opening ratio A1/ (A1+A2) is for example greater than 91%.In addition, the area summation of the aforesaid second strip opening AP2 is A3, and the overlapping area summation of the second pixel electrode ITO2 and electrical floating terminal D3 ' is A4, and opening ratio A3/ (A3+A4) is for example greater than 93%.
In the pel array 200 ' of Fig. 2 and Fig. 6, stray capacitance Cx2 between the stray capacitance Cx1 between the first pixel electrode ITO1 and the signal output part D2 ' and the second pixel electrode ITO2 and the electrical floating terminal D3 ' can be reduced equally effectively, so the colour cast problem can achieve a solution.
[the 3rd embodiment]
Fig. 7 is the synoptic diagram of polymer-stabilized alignment liquid crystal display panel of the present invention.Please refer to Fig. 7, the polymer-stabilized alignment liquid crystal display panel 300 of present embodiment comprises one first substrate 310, one second substrate 320, two polymkeric substance stable alignment layers 330,340 and a liquid crystal layer 350.First substrate 310 has the pel array (200 or 200 ') among aforementioned first embodiment or second embodiment, second substrate 320 is disposed at first substrate, 310 tops, and two polymkeric substance stable alignment layers 330,340 are disposed at respectively on first substrate 310 and second substrate 320.In addition, liquid crystal layer 350 is disposed between the two polymkeric substance stable alignment layers 330,340.It should be noted that, liquid crystal layer 350 employing on making includes can be by the liquid crystal material of the monomer of energy source polymerization, when energy source (as ultraviolet light) when being applied in liquid crystal layer 350, these can be distinguished polymerization on the surface of first substrate 310 and second substrate 320 by the monomer of energy source polymerization, to form two polymkeric substance stable alignment films 330,340.
Fig. 8 is the synoptic diagram of electrooptical device of the present invention.Please refer to Fig. 8, present embodiment also proposes a kind of electrooptical device 400, and it comprises pel array (200 or 200 ') among aforementioned first embodiment or second embodiment or the polymer-stabilized alignment liquid crystal display panel 300 among Fig. 7.And the type of electrooptical device comprises the panel in portable product (as mobile phone, video camera, camera, mobile computer, game machine, wrist-watch, music player, electronic mail transceiver, map navigator, digital photo or similar products like), video and audio product (as audio-visual projector or similar products like), screen, TV, billboard, the projector etc.
In sum, the present invention in sub-pixel signal output part and electrically adopt open design above the floating terminal, therefore the stray capacitance between first pixel electrode and the signal output part and second pixel electrode can be reduced effectively with stray capacitance between the electrical floating terminal.
Claims (21)
1. a pel array is characterized in that, described pel array comprises:
The multi-strip scanning line;
Many data lines, staggered with described sweep trace to define a plurality of subpixel area;
A plurality of sub-pixels are disposed in the described subpixel area, each described sub-pixel respectively with sweep trace wherein and wherein a data line be electrically connected, each the described sub-pixel that wherein is arranged in the n row comprises:
One first switch;
One second switch, described first switch and described second switch are electrically connected with n bar sweep trace and m bar data line, and described second switch has a signal output part;
One first pixel electrode is electrically connected with described first switch;
One second pixel electrode is electrically connected with the described signal output part of described second switch, and wherein said first pixel electrode has at least one first opening that is positioned at described signal output part top; And
One the 3rd switch is electrically connected with (n+1) bar sweep trace and described second pixel electrode, and wherein said the 3rd switch has an electrical floating terminal, and described second pixel electrode has at least one second opening that is positioned at top, described electrical floating terminal.
2. pel array as claimed in claim 1 is characterized in that described arrangement of subpixels becomes multiple row, and the sub-pixel that is arranged in n row is electrically connected with n bar sweep trace and (n+1) bar sweep trace.
3. pel array as claimed in claim 1 is characterized in that, described first pixel electrode and described second pixel electrode that are arranged in the sub-pixel of n row are positioned between n bar sweep trace and (n+1) bar sweep trace.
4. pel array as claimed in claim 1, it is characterized in that, each described first switch that is arranged in the n row is a first film transistor, first drains and described the first film transistor has that a first grid that is electrically connected with n bar sweep trace, first source electrode and that is electrically connected with data line wherein be electrically connected with described first pixel electrode.
5. pel array as claimed in claim 1, it is characterized in that, each the described second switch that is arranged in the n row is one second thin film transistor (TFT), and described second thin film transistor (TFT) have a second grid that is electrically connected with n bar sweep trace, one with second source electrode and described signal output part that data line is electrically connected wherein.
6. pel array as claimed in claim 1, it is characterized in that, each described the 3rd switch that is arranged in the n row is one the 3rd thin film transistor (TFT), and described the 3rd thin film transistor (TFT) has the 3rd grid that is electrically connected with (n+1) bar sweep trace, the 3rd source electrode that is electrically connected with described second pixel electrode and a described electrical floating terminal.
7. pel array as claimed in claim 1 is characterized in that, described electrical floating terminal extends to described first pixel electrode below.
8. pel array as claimed in claim 1 is characterized in that, described pel array more comprises the many common lines that are electrically connected to each other, and is distributed in each described first pixel electrode and each described second pixel electrode below.
9. pel array as claimed in claim 8, it is characterized in that, each described common line extends along column direction respectively, the common line of part that is distributed in described first pixel electrode below has first branch that at least one is positioned at described first opening below, and the common line of part that is distributed in below described second pixel electrode has second branch that at least one is positioned at described second opening below.
10. pel array as claimed in claim 9 is characterized in that, described second branch is positioned at below, described electrical floating terminal.
11. pel array as claimed in claim 1 is characterized in that, each described first pixel electrode comprises:
One first electrode part;
One second electrode part; And
One first connecting portion, between described first electrode part and described second electrode part, so that described first electrode part and described second electrode part are separated by two first strip openings that lay respectively at the described first connecting portion both sides, wherein said first electrode part sees through described first connecting portion and is connected with described second electrode part.
12. pel array as claimed in claim 11 is characterized in that, the area summation of the described first strip opening is A1, and the overlapping area summation of described first pixel electrode and described signal output part is A2, and opening ratio A1/ (A1+A2) is greater than 91%.
13. pel array as claimed in claim 1 is characterized in that, each described second pixel electrode comprises:
One third electrode portion;
One the 4th electrode part; And
One second connecting portion, between described third electrode portion and described the 4th electrode part, so that described third electrode portion and described the 4th electrode part separated by two second strip openings that lay respectively at the described second connecting portion both sides, wherein said third electrode portion sees through described second connecting portion and is connected with described the 4th electrode part.
14. pel array as claimed in claim 13 is characterized in that, the area summation of the described second strip opening is A3, and the overlapping area summation of described second pixel electrode and described electrical floating terminal is A4, and opening ratio A3/ (A3+A4) is greater than 93%.
15. pel array as claimed in claim 1 is characterized in that, each described first pixel electrode comprises:
One first electrode part;
One second electrode part; And
A plurality of first connecting portions, between described first electrode part and described second electrode part, so that described first electrode part and described second electrode part are separated by at least one first strip opening between described first connecting portion, wherein said first electrode part sees through described first connecting portion and is connected with described second electrode part.
16. pel array as claimed in claim 15 is characterized in that, the area of the described first strip opening is A1, and the overlapping area summation of described first pixel electrode and described signal output part is A2, and opening ratio A1/ (A1+A2) is greater than 91%.
17. pel array as claimed in claim 1 is characterized in that, each described second pixel electrode comprises:
One third electrode portion;
One the 4th electrode part; And
A plurality of second connecting portions, between described third electrode portion and described the 4th electrode part, so that described third electrode portion and described the 4th electrode part separated by at least one second strip opening between described second connecting portion, wherein said third electrode portion sees through described second connecting portion and is connected with described the 4th electrode part.
18. pel array as claimed in claim 17 is characterized in that, the area of the described second strip opening is A3, and the overlapping area summation of described second pixel electrode and described electrical floating terminal is A4, and opening ratio A3/ (A3+A4) is greater than 93%.
19. a polymer-stabilized alignment liquid crystal display panel is characterized in that, described polymer-stabilized alignment liquid crystal display panel comprises:
One first substrate has pel array as claimed in claim 1;
One second substrate is disposed at described first substrate top;
Two polymkeric substance stable alignment layers are disposed at respectively on described first substrate and described second substrate; And
One liquid crystal layer is disposed between the described polymer-stabilized alignment layer.
20. an electrooptical device is characterized in that, described electrooptical device comprises the described pel array of claim 1.
21. an electrooptical device is characterized in that, described electrooptical device comprises the described polymer-stabilized alignment liquid crystal display panel of claim 19.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010102372A CN101776827A (en) | 2010-01-22 | 2010-01-22 | Pixel array, polymer stable alignment LCD panel and optoelectronic device |
| CN2010102361171A CN101908539B (en) | 2010-01-22 | 2010-07-22 | Pixel array, polymer stable alignment liquid crystal display panel and photoelectronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010102372A CN101776827A (en) | 2010-01-22 | 2010-01-22 | Pixel array, polymer stable alignment LCD panel and optoelectronic device |
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| CN101776827A true CN101776827A (en) | 2010-07-14 |
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| CN201010102372A Pending CN101776827A (en) | 2010-01-22 | 2010-01-22 | Pixel array, polymer stable alignment LCD panel and optoelectronic device |
| CN2010102361171A Active CN101908539B (en) | 2010-01-22 | 2010-07-22 | Pixel array, polymer stable alignment liquid crystal display panel and photoelectronic device |
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| CN2010102361171A Active CN101908539B (en) | 2010-01-22 | 2010-07-22 | Pixel array, polymer stable alignment liquid crystal display panel and photoelectronic device |
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| CN (2) | CN101776827A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014059690A1 (en) * | 2012-10-18 | 2014-04-24 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display device |
| CN104460128A (en) * | 2013-09-13 | 2015-03-25 | 三星显示有限公司 | Liquid crystal display |
| WO2015143739A1 (en) * | 2014-03-27 | 2015-10-01 | 深圳市华星光电技术有限公司 | Display apparatus and method for displaying images thereof |
| CN107958910A (en) * | 2017-12-21 | 2018-04-24 | 惠科股份有限公司 | Active switch array base palte and its manufacture method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103454823B (en) * | 2013-09-09 | 2016-01-06 | 深圳市华星光电技术有限公司 | A kind of array base palte and display panels |
| CN106842743B (en) * | 2017-02-09 | 2019-11-15 | 深圳市华星光电技术有限公司 | A kind of liquid crystal pixel circuit and liquid crystal display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06268188A (en) * | 1993-03-11 | 1994-09-22 | Sony Corp | Amplification type image sensing element |
| CN1306557C (en) * | 2004-07-27 | 2007-03-21 | 友达光电股份有限公司 | Thin film transistor array base plate and its repairing method |
-
2010
- 2010-01-22 CN CN201010102372A patent/CN101776827A/en active Pending
- 2010-07-22 CN CN2010102361171A patent/CN101908539B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014059690A1 (en) * | 2012-10-18 | 2014-04-24 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display device |
| CN104460128A (en) * | 2013-09-13 | 2015-03-25 | 三星显示有限公司 | Liquid crystal display |
| WO2015143739A1 (en) * | 2014-03-27 | 2015-10-01 | 深圳市华星光电技术有限公司 | Display apparatus and method for displaying images thereof |
| CN107958910A (en) * | 2017-12-21 | 2018-04-24 | 惠科股份有限公司 | Active switch array base palte and its manufacture method |
| CN107958910B (en) * | 2017-12-21 | 2020-06-12 | 惠科股份有限公司 | Active switch array substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101908539B (en) | 2012-05-23 |
| CN101908539A (en) | 2010-12-08 |
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