CN101771038A - Integrated circuit structure - Google Patents
Integrated circuit structure Download PDFInfo
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- CN101771038A CN101771038A CN200910141838A CN200910141838A CN101771038A CN 101771038 A CN101771038 A CN 101771038A CN 200910141838 A CN200910141838 A CN 200910141838A CN 200910141838 A CN200910141838 A CN 200910141838A CN 101771038 A CN101771038 A CN 101771038A
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- Prior art keywords
- layer
- earth connection
- dielectric layer
- holding wire
- integrated circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/003—Coplanar lines
Abstract
An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.
Description
Technical field
The present invention relates to integrated circuit, and be particularly related to stacked co-planar waveguide (stacked coplanarwave-guides).
Background technology
Waveguide (wave-guides) is the very critical elements in the microwave circuit applications.It provides the interior bonds situation between interior active device of microwave circuit and the passive device.Waveguide is for being widely used in a kind of transmission line in monocrystalline microwave integrated circuit (the monolithic microwave integrated circuit) application.
For the monocrystalline microwave integrated circuit is used, waveguide adopts co-planar waveguide mode (coplanarwave-guides) to exist usually, wherein earth connection in same waveguide and holding wire are formed in the same level, and this plane is parallel to the surface of the semiconductor substrate that is positioned at its below usually.The making flow process of co-planar waveguide is compatible in the manufacturing process of integrated circuit now.Moreover it also can be formed on the same substrate that is provided with complementary metal oxide semiconductor circuit (CMOS circuit), so waveguide also easily is integrated among the complementary metal oxide semiconductor circuit.
Please refer to Fig. 1, show a kind of known co-planar waveguide 2, it has comprised a holding wire 4 and several earth connections 6 that are positioned at earth connection 6 symmetrical sides.Holding wire 4 is positioned on the par plane with earth connection 6.Co-planar waveguide 2 is formed on a high-k (high-k) dielectric layer 10, and dielectric layer with high dielectric constant 10 is formed on the protective layer (passivation layer) 12.14 belows that are positioned at co-planar waveguide 2 of dielectric layer between metal layers wherein are formed with several plain conductors within the dielectric layer between metal layers 14.16 belows that are positioned at dielectric layer between metal layers 14 of substrate.
As shown in Figure 1, known co-planar waveguide 2 is in forming top film layer and be away from substrate 16 relatively, so its energy loss in substrate 16 in is less than co-planar waveguide 2 is formed in arbitrary rete below the dielectric layer with high dielectric constant situation is set.Yet the microwave wavelength of being transmitted is usually much larger than the vertical range between 16 of co-planar waveguide 2 and substrates.For instance, the electromagnetic wavelength in silicon dioxide dielectric layers is about 3000 microns (under 50GHz).For lower frequency, wavelength will be bigger.Above-mentioned wavelength far surpasses the total film thickness of rete 10,12,14 and other similar retes.Therefore, by co-planar waveguide 2 being arranged in the top film layer for the increase of above-mentioned distance compared to the wavelength of microwave signal, and thereby limited by increasing vertical range to reach the effect that reduces energy loss relatively for little.
In addition, known co-planar waveguide 2 as shown in Figure 1 also has other following shortcomings.The thickness T of earth connection 6 is determined by the fabrication schedule of each chip, thereby is had less adjustment space.So also limited characteristic adjustment for co-planar waveguide 2.Therefore, just need to solve waveguiding structure of foregoing problems and forming method thereof.
Summary of the invention
In view of this, the invention provides a kind of integrated circuit structure, to solve aforesaid known problem.
According to an embodiment, integrated circuit structure of the present invention comprises:
The semiconductor substrate; One interconnect structure is positioned on this semiconductor substrate;
One first dielectric layer, be positioned on this semiconductor substrate and this interconnect structure within; One second dielectric layer, be positioned within this interconnect structure and this first dielectric layer on; An and waveguide.Above-mentioned waveguide comprises: one first rete is positioned at this first dielectric layer; And one second rete, be positioned at this second dielectric layer, wherein this first rete is close to this second rete.
According to another embodiment, integrated circuit structure of the present invention comprises:
The semiconductor substrate; A plurality of dielectric layers; An and waveguide.Above-mentioned dielectric layer comprises: a plurality of dielectric layer between metal layers were positioned on this semiconductor-based end, one second dielectric layer between metal layers that wherein said a plurality of dielectric layer between metal layers comprise dielectric layer between a first metal layer and are positioned at dielectric layer top between this first metal layer; And a protective layer, be positioned on this dielectric layer between metal layers.Above-mentioned waveguide comprises: a holding wire; One first earth connection; And one second earth connection, be positioned at a symmetrical side of this holding wire that this first earth connection is set.In one embodiment, one of this holding wire, this first earth connection and this second earth connection extend among described a plurality of dielectric layer interior one first dielectric layer or one second dielectric layer at least.
The present invention has well solved aforesaid problems of the prior art, is convenient to the characteristic impedance of wider adjustment waveguide, and has improved the power factor of waveguide.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is a profile, has shown a known co-planar waveguide, and it adopts the CMOS inclusive routine made, and wherein waveguide is formed at a top dielectric that is positioned on the high dielectric constant layer;
Fig. 2 A and Fig. 2 B are a profile and a stereogram, have shown the waveguide according to one embodiment of the invention respectively, and wherein waveguide comprises several stack portion that are positioned at different retes;
Fig. 3 is a profile, shows the waveguide according to another embodiment of the present invention, and wherein plain conductor portion and the interlayer thing portion in the waveguide has different in width;
Fig. 4 has shown a plurality of analog results, and wherein the attenuation losses of waveguide is depicted as the function of holding wire thickness;
Fig. 5 has shown a plurality of analog results, and wherein the quality factor of waveguide are depicted as the function of holding wire thickness;
Fig. 6 has shown a plurality of analog results, and wherein the characteristic impedance of waveguide is depicted as the function of holding wire thickness;
Fig. 7 has shown a plurality of analog results, and wherein the characteristic impedance of waveguide is depicted as the function of the spacing of holding wire and earth connection; And
Fig. 8-Figure 11 shows the enforcement situation of a plurality of waveguides, and holding wire has different thickness with earth connection in it.
Description of reference numerals in the above-mentioned accompanying drawing is as follows:
2～co-planar waveguide;
4～holding wire;
6～earth connection;
10～dielectric layer with high dielectric constant;
12～protective layer;
14～dielectric layer between metal layers;
16～substrate;
30～semiconductor substrate;
31～contact is inserted and is fastened;
32～integrated circuit (IC) apparatus;
33～interlayer dielectric layer;
34～interconnect structure;
35～plain conductor;
37～interlayer thing;
40～co-planar waveguide;
42～holding wire;
The plain conductor portion of 42_M2,42_M1～holding wire;
The interlayer thing portion of 42_V2,42_V1～holding wire;
44～earth connection;
50～dielectric layer;
51～weld pad;
The spacing of S～holding wire and earth connection;
The thickness of T～earth connection;
The thickness of T '～holding wire;
The width of W1～plain conductor portion and interlayer thing portion.
Embodiment
The invention provides novel co-planar waveguide, and by hereinafter describing and cooperating accompanying drawing such as Fig. 2 A-Figure 11 to explain orally a plurality of embodiment of co-planar waveguide of the present invention, wherein same numeral has been represented identical components.
Please refer to Fig. 2 A and Fig. 2 B, show the profile and the stereogram of the integrated circuit structure that includes a waveguiding structure in one embodiment of the invention respectively.At first provide by as the made semiconductor substrate 30 of common semi-conducting materials such as silicon or SiGe.Then form the integrated circuit (IC) apparatus 32 that includes CMOS (Complementary Metal Oxide Semiconductor) (CMOS) device, be depicted as a MOS transistor as representative at this.Integrated circuit (IC) apparatus 32 can be formed at the surface of semiconductor substrate 30.34 of interconnect structures are formed on the semiconductor substrate 30.Interconnect structure 34 comprises several plain conductors 35 and interlayer thing 37 that connect integrated circuit 32 in the composition, and interconnect structure 34 then can link integrated circuit 32 and the weld pad (not shown) that is positioned at the top surface of each semiconductor chip
Co-planar waveguide 40 is formed within the interconnect structure 34.Co-planar waveguide 40 comprises holding wire 42 and several earth connections 44 that are positioned at the symmetrical side of holding wire 42.At least holding wire 42 and earth connection 44 one of them comprise the more than one rete that piles up, and these pile up rete and lay respectively within the dielectric layer.Several dielectric layers at co-planar waveguide 40 places are dielectric layer 50 at this label.In one embodiment, dielectric layer 50 comprises dielectric layer between metal layers (IMD), its by as have dielectric constant and be lower than as 3.5 low dielectric constant dielectric materials or be lower than 2.5 utmost point low dielectric constant dielectric materials and formed.In other embodiments, these dielectric layers 50 comprise one or more undoped silicon glass (USG) rete, and it is also formed by low dielectric constant dielectric materials.These undoped silicon glass retes also are positioned at the below of a protective layer.In other embodiments, these dielectric layers 50 comprise a protective layer that is formed on the undoped silicon glass rete, and this protective layer preferably has the dielectric constant more than or equal to 3.9.
According to its set dielectric layer 50 positions, co-planar waveguide 40 can comprise the formed multiple different materials of the multiple distinct methods of employing.For instance, in the time of in co-planar waveguide 40 is formed at dielectric layer between metal layers and undoped silex glass rete, co-planar waveguide 40 can have by known singly to be inlayed or one one of the formed copper product of dual-damascene technics (in holding wire 42 or the earth connection 44 one one).Known to known, the execution of above-mentioned mosaic technology is included in and forms opening in the dielectric layer, inserts metal material in opening, and implements cmp to remove opening steps such as metal material in addition.
On the other hand, one one that is formed at the interior co-planar waveguide 40 of protective layer then can comprise aluminium, tungsten, silver or analog material, and it can and follow this metallic diaphragm of etching with the formation intended shape by deposition one metallic diaphragm.For instance, Fig. 3 shows co-planar waveguide 40 and has comprised a top film layer that is formed in protective layer 50 end faces, and wherein the top film layer of co-planar waveguide 40 and weld pad 51 are positioned at a same rete and form simultaneously.
Co-planar waveguide 40 can comprise two or more retes that pile up mutually, wherein the co-planar waveguide theca interna can be arranged in arbitrary rete of interconnect structure 34, for example for being used to form in the weld pad rete of weld pad, being formed with that contact is inserted in the interlayer dielectric layer 33 of fastening 31 (please refer to Fig. 2 A) and/or rete in arbitrary dielectric layer of 33 of soldering pad layer and interlayer dielectric layers, but do not limited the present invention with above-mentioned enforcement situation.Please refer to Fig. 2 A and Fig. 3, shown a top rete and a bottom rete, though co-planar waveguide 40 can comprise more multiple film layer.Each rete in the co-planar waveguide 40 mainly comprises several interlayer thing portions (via portion) of several plain conductor portions (metalline portion) and below thereof, wherein the plain conductor portion of holding wire 42 has comprised parts such as 42_M2 and 42_M1, and the interlayer thing portion of plain conductor 42 comprises parts such as 42_V2 and 42_V1.In one embodiment, 42_M2 of plain conductor portion and 42_M1 and interlayer thing part 42_V2 and 42_V1 have same widths W1, thereby holding wire 42 is for having an integral wire of rectangle section.In another embodiment, the 42_M2 of plain conductor portion and 42_M1 and the interlayer thing 42_V2 of portion and 42_V1 have different width W 1 and W2 respectively.Similarly, earth connection 44 also can be several metallic diaphragms to be formed, and the different portions in the earth connection 44 also can have identical or different width.
It should be noted that holding wire 42 and earth connection 44 extend in the more than one rete, thickness that can be by increasing holding wire 42 and earth connection 44 is to form preferable waveguide.Fig. 4 shows an analog result, has shown the functional relation of between thickness T ' of loss loss (attenuation loss) and holding wire 42 in the waveguide (please refer to Fig. 2 A, wherein thickness T ' obtains by measurement signal line 42 from top to bottom).Shown the increase along with thickness T ' in Fig. 4, the loss loss also reduces for it.On the other hand, Fig. 5 then shows an analog result, has shown the increase along with thickness T ', and the quality factor of waveguide (quality factor) can be improved.
In addition, also observed by adjusting holding wire 42 and or the thickness of earth connection 44 and can adjust the characteristic impedance (characteristic impedance) of co-planar waveguide 40.For instance, as shown in Figure 6, along with the increase of holding wire 42 thickness T ', the characteristic impedance of co-planar waveguide 40 also reduces thereupon.In the above-described embodiments, also can be for thickness T ' adjustment in conjunction with the adjustment of other sizes, the for example adjustment of the width W 1 of holding wire 42 and the interval S between between holding wire 42 and earth connection 44 (please refer to Fig. 2 A) is so that the characteristic impedance of wider adjustment waveguide.For instance, Fig. 7 shows when the width W 1 of holding wire 42 reduces, and has also reduced the characteristic impedance of co-planar waveguide 40, and when between the interval S increase of 44 of holding wire 42 and earth connections, will increase its characteristic impedance.
Fig. 8 and Fig. 9 show other embodiment of the integrated circuit structure that comprises co-planar waveguide of the present invention, and wherein holding wire 42 can more extend among the metal layer of varying number with earth connection 44.Please refer to Fig. 8, earth connection 44 extends within a plurality of metal layers, and holding wire 42 then only is formed within the relative top rete of these metallic diaphragms.Please refer to Fig. 9, earth connection 44 extends within a plurality of metal layers, and holding wire 42 is formed within the middle relatively rete of these layer of metallized film.Holding wire 42 also can only form within the relative bottom film layer in these metal layers at earth connection 44 places.In other embodiments, holding wire 42 can extend within the more metal layer than earth connection 44, and earth connection 44 only be formed at the relative top of these metal layers at holding wire place, relatively in the middle of or relatively among the metal/dielectric rete of bottom as Figure 10 and shown in Figure 11.Please refer to Figure 10, earth connection 44 extends in the less layer of metallized film than holding wire 42, and can be positioned at one or more top metallization retes at holding wire 42 places.Perhaps, as shown in figure 11, earth connection can only form in the middle of one or more within these metallization/dielectric film layers of holding wire 42 places in the rete.In other embodiments, earth connection 44 can only form in the one or more relative bottom film layer of metallization/dielectric film layer at holding wire 42 places.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking appended the scope that claim defined.
Claims (15)
1. integrated circuit structure comprises:
The semiconductor substrate;
One interconnect structure is positioned on this semiconductor substrate;
One first dielectric layer, be positioned on this semiconductor substrate and this interconnect structure within;
One second dielectric layer, be positioned within this interconnect structure and this first dielectric layer on; And
One waveguide comprises:
One first rete is positioned at this first dielectric layer; And
One second rete is positioned at this second dielectric layer, and wherein this first rete is close to this second rete.
2. integrated circuit structure as claimed in claim 1, wherein this waveguide also comprises a holding wire and is positioned at one first earth connection and one second earth connection of the symmetrical side of this holding wire.
3. integrated circuit structure as claimed in claim 2, wherein this holding wire has a thickness that is different from or is same as this first earth connection and this second earth connection.
4. integrated circuit structure as claimed in claim 3, wherein this holding wire has the thickness less than this first earth connection and this second earth connection.
5. integrated circuit structure as claimed in claim 4, wherein this first earth connection and this second earth connection extend within a plurality of layer of metallized film, and wherein this holding wire is positioned at the relative top layer of described a plurality of layer of metallized film and is not positioned at the relative bottom of described a plurality of layer of metallized film or the relative intermediate layer that this holding wire is positioned at described a plurality of metallic diaphragms and the relative top layer that is not positioned at described a plurality of metallic diaphragms or to bottom or this holding wire being positioned at the relative bottom of described a plurality of layer of metallized film and not being positioned at the relative top layer of described a plurality of layer of metallized film.
6. integrated circuit structure as claimed in claim 3, wherein this holding wire has the thickness greater than this first earth connection and this second earth connection.
7. integrated circuit structure as claimed in claim 6; Wherein this holding wire extends within a plurality of layer of metallized film, and wherein this first earth connection is positioned at the relative top layer of described a plurality of layer of metallized film with this second earth connection and is not positioned at the relative bottom of described a plurality of layer of metallized film or this first earth connection and this second earth connection are positioned at the relative intermediate layer of described a plurality of layer of metallized film and are not positioned at the relative top layer of described a plurality of layer of metallized film or bottom or this first earth connection and this second earth connection are positioned at the relative bottom of described a plurality of layer of metallized film and are not positioned at the relative top layer of described a plurality of layer of metallized film relatively.
8. integrated circuit structure as claimed in claim 1, wherein this second dielectric layer is a protective layer.
9. integrated circuit structure as claimed in claim 1, wherein this first rete and this second rete all comprise a plain conductor portion and an interlayer thing portion that is positioned at this plain conductor subordinate side.
10. integrated circuit structure comprises:
The semiconductor substrate;
A plurality of dielectric layers comprise:
A plurality of dielectric layer between metal layers were positioned on this semiconductor-based end, one second dielectric layer between metal layers that wherein said a plurality of dielectric layer between metal layers comprise dielectric layer between a first metal layer and are positioned at dielectric layer top between this first metal layer; And
One protective layer is positioned on this dielectric layer between metal layers; And
One waveguide comprises:
One holding wire;
One first earth connection; And
One second earth connection is positioned at a symmetrical side of this holding wire that this first earth connection is set;
Wherein one of this holding wire, this first earth connection and this second earth connection extend among described a plurality of dielectric layer interior one first dielectric layer or one second dielectric layer at least.
11. integrated circuit structure as claimed in claim 10, wherein this second dielectric layer is a protective layer, and this first dielectric layer is a dielectric layer with low dielectric constant.
12. integrated circuit structure as claimed in claim 10, wherein this second dielectric layer is a undoped silicon glass layer, and this first dielectric layer is a dielectric layer with low dielectric constant.
13. integrated circuit structure as claimed in claim 10, wherein this second dielectric layer is a protective layer, and this first dielectric layer is a undoped silicon glass layer.
14. integrated circuit structure as claimed in claim 10, wherein this holding wire has being same as or is different from a thickness of this first earth connection and this second earth connection.
15. integrated circuit structure as claimed in claim 10, wherein this holding wire, this first earth connection and this second earth connection all comprise a plain conductor portion and an interlayer thing portion that is positioned at this plain conductor subordinate side.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/345,283 US8058953B2 (en) | 2008-12-29 | 2008-12-29 | Stacked coplanar waveguide having signal and ground lines extending through plural layers |
| US12/345,283 | 2008-12-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101771038A true CN101771038A (en) | 2010-07-07 |
| CN101771038B CN101771038B (en) | 2012-05-23 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101418381A Active CN101771038B (en) | 2008-12-29 | 2009-05-26 | Integrated circuit structure |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US8058953B2 (en) |
| CN (1) | CN101771038B (en) |
| TW (1) | TWI415327B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068651A (en) * | 2016-12-30 | 2017-08-18 | 上海集成电路研发中心有限公司 | Transmission line structure and preparation method thereof on a kind of piece |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8058953B2 (en) * | 2008-12-29 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked coplanar waveguide having signal and ground lines extending through plural layers |
| US9362606B2 (en) | 2013-08-23 | 2016-06-07 | International Business Machines Corporation | On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures |
| US9462396B2 (en) * | 2013-10-09 | 2016-10-04 | Starkey Laboratories, Inc. | Hearing assistance coplanar waveguide |
| US9511778B1 (en) | 2014-02-12 | 2016-12-06 | XL Hybrids | Controlling transmissions of vehicle operation information |
| US9484246B2 (en) | 2014-06-18 | 2016-11-01 | Globalfoundries Inc. | Buried signal transmission line |
| TWI652514B (en) * | 2015-01-06 | 2019-03-01 | 聯華電子股份有限公司 | Waveguide structure and manufacturing method thereof |
| US9478508B1 (en) * | 2015-06-08 | 2016-10-25 | Raytheon Company | Microwave integrated circuit (MMIC) damascene electrical interconnect for microwave energy transmission |
| TWI636617B (en) * | 2016-12-23 | 2018-09-21 | 財團法人工業技術研究院 | Electromagnetic wave transmitting board differential electromagnetic wave transmitting board |
| US11515609B2 (en) * | 2019-03-14 | 2022-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transmission line structures for millimeter wave signals |
| CN110931440A (en) * | 2019-12-10 | 2020-03-27 | 中国电子科技集团公司第五十八研究所 | Radio frequency signal vertical transmission structure and preparation method thereof |
| US11888204B2 (en) * | 2022-05-09 | 2024-01-30 | Nxp B.V. | Low loss transmission line comprising a signal conductor and return conductors having corresponding curved arrangements |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS60134440A (en) * | 1983-12-23 | 1985-07-17 | Hitachi Ltd | Semiconductor integrated circuit device |
| US5408053A (en) * | 1993-11-30 | 1995-04-18 | Hughes Aircraft Company | Layered planar transmission lines |
| CN1072395C (en) * | 1997-04-18 | 2001-10-03 | 庄晴光 | Dual modes microwave/mm wave integrated circuit sealing pack |
| JP2001308609A (en) * | 2000-04-21 | 2001-11-02 | Oki Electric Ind Co Ltd | Coplanar line |
| US6465367B1 (en) | 2001-01-29 | 2002-10-15 | Taiwan Semiconductor Manufacturing Company | Lossless co-planar wave guide in CMOS process |
| US6490379B2 (en) | 2001-05-07 | 2002-12-03 | Corning Incorporated | Electrical transmission frequency of SiOB |
| DE102004022177B4 (en) * | 2004-05-05 | 2008-06-19 | Atmel Germany Gmbh | A method for producing a coplanar line system on a substrate and a device for transmitting electromagnetic waves produced by such a method |
| KR100731544B1 (en) * | 2006-04-13 | 2007-06-22 | 한국전자통신연구원 | Multi-metal coplanar waveguide |
| US8058953B2 (en) * | 2008-12-29 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked coplanar waveguide having signal and ground lines extending through plural layers |
-
2008
- 2008-12-29 US US12/345,283 patent/US8058953B2/en not_active Expired - Fee Related
-
2009
- 2009-05-15 TW TW098116133A patent/TWI415327B/en not_active IP Right Cessation
- 2009-05-26 CN CN2009101418381A patent/CN101771038B/en active Active
-
2011
- 2011-10-14 US US13/273,815 patent/US8274343B2/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068651A (en) * | 2016-12-30 | 2017-08-18 | 上海集成电路研发中心有限公司 | Transmission line structure and preparation method thereof on a kind of piece |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101771038B (en) | 2012-05-23 |
| US20120094480A1 (en) | 2012-04-19 |
| US8274343B2 (en) | 2012-09-25 |
| US20100164653A1 (en) | 2010-07-01 |
| TWI415327B (en) | 2013-11-11 |
| TW201025719A (en) | 2010-07-01 |
| US8058953B2 (en) | 2011-11-15 |
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