CN101770438A - Control system and method for storage access - Google Patents
Control system and method for storage access Download PDFInfo
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- CN101770438A CN101770438A CN200810187747A CN200810187747A CN101770438A CN 101770438 A CN101770438 A CN 101770438A CN 200810187747 A CN200810187747 A CN 200810187747A CN 200810187747 A CN200810187747 A CN 200810187747A CN 101770438 A CN101770438 A CN 101770438A
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Abstract
The invention relates to control system and method for storage access, wherein the control system comprises an access command temporary storage device of a system storage, a storage access and concurrent processing device, an access command temporary storage device of a dynamic storage and a command control device of the dynamic storage, wherein the access command temporary storage device of the system storage is used for temporarily storing an access command of the system storage; the storage access and concurrent processing device is used for decoding the access command of a current system storage so as to generate the access command of the dynamic storage and carrying out priority processing on the access command of the dynamic storage so as to generate the access command of the dynamic storage with the priority; the access command temporary storage device of the dynamic storage is used for temporarily storing the access command of the dynamic storage; and the command control device of the dynamic storage is used for accepting the access command of the dynamic storage and carrying out priority processing on the access command of the dynamic storage so as to generate the access command of the dynamic storage with the priority and generate a control command accessed by the dynamic storage according to the priority.
Description
Technical field
The present invention relates to the technical field of DYNAMIC MEMORY ACCESS, be specifically related to a kind of control system and method that is used for the synchronous dynamic random access memory access.
Background technology
Because the progress of semiconductor technology, the operating speed of dynamic storage also improve gradually.In past 20 years, the operating speed of dynamic storage is promoted to several GHz by several MHz, and the delay cycle number of the data access of stable storage body also increases gradually.For example the delay cycle number of the data access of the stable storage body of SDR is 3-5, and the delay cycle number of the data access of the stable storage body of DDR-II and DDR-III is 12-25.
Computer system or image processing system can comprise a plurality of system bus master control sets.Each system bus master control set has specific function, and for example: picture decoding, picture coding, image playback, message is decoded, message playbacks, direct memory access (DMA) functions such as (DMA).Because each system bus master control set is carried out its specific function, therefore its access size to storer is to operate under different addresses and command format simultaneously with the address, therefore the DYNAMIC MEMORY ACCESS order meeting that is produced by the system bus master control set different bank that is used in dynamic storage carries out access, even a plurality of memory bank carries out access.Owing to there are a plurality of system bus master control sets can the execute store access, and the address of its access dynamic storage has nothing in common with each other, and therefore is difficult in and finds the dynamic page identical with last memory access commands in the current storage access command.
Fig. 1 is to the synoptic diagram of different page or leaf accesses in known DDR (the Double data rate double data rate (DDR)) memory access commands.It reads for the A memory bank (BAa) to storer carries out secondary, reads each time and is reading of eight data of burst type.When moment T0, Memory Controller is to the A memory bank output precharge command of this storer.Behind 3 clocks, when moment T3, Memory Controller is to the A memory bank output activation command of this storer.These 3 clocks then determine according to the tRP=3 in this storer description.Behind 3 clocks, when moment T6, Memory Controller is to the A memory bank output reading order of this storer.These 3 clocks also determine according to the tRCD=3 in this storer description.Through behind 3 clocks (CL=3), when moment T9, this storer is exported corresponding data (A1～A8) at its data bus.Because second behavior of reading is that page or leaf inequality reads in the A memory bank to storer, thus Memory Controller when moment T11 to this storer output precharge command, when moment T14, export activation command.The activation command sequential of same bank is to determine according to the tRC=11 in the specifications.As shown in Figure 1, this storer is exported corresponding data (A9～A16), need about 24 clock period to finish reading of two eight data of burst type altogether by its data bus when moment T19.The mode of this access memory is lost time and is inefficent very much.
At the problems referred to above, Fig. 2 carries out access for known use interlace mode to the DDR storer synoptic diagram.It once reads respectively for A memory bank (BAa) and the B memory bank (BAb) to storer, reads each time and is reading of eight data of burst type.When moment T0, Memory Controller is to the A memory bank output precharge command of this storer.When moment T2, Memory Controller is to the B memory bank output precharge command of this storer.When moment T3, Memory Controller is to the A memory bank output activation command of this storer.When moment T5, Memory Controller is to the B memory bank output activation command of this storer, and this activation command belongs to different memory banks with first previous activation command, so be not subjected to the restriction of tRC=11 in the description.When moment T6, Memory Controller is to the A memory bank output reading order of this storer.When moment T9, the A memory bank of this storer is exported corresponding data (A1～A8) at the data bus of this storer.Because through behind 3 clocks (CL=3), when moment T13, this storer is exported corresponding data (B1～B8) at its data bus, so when moment T10, Memory Controller needs about 18 clock period to finish reading of two eight data of burst type to the B memory bank output reading order of this storer altogether.Though the comparable Fig. 1 of this kind mode saves a plurality of clock period; yet because the uncontinuity of data address; system usually can the close storer in access address; be that system usually can carry out repeatedly access to the not same page of the same memory bank of storer; so this probability to the different bank interlaced mode as Fig. 2 is not high; particularly in complication system, therefore the control system of known storage access still has many shortcomings and necessity of being improved is arranged.
Summary of the invention
The object of the present invention is to provide a kind of system of synchronous memories access, can reduce delay and promote whole access speed, thereby obtain preferable system effectiveness.
Another object of the present invention is to provide a kind of system of synchronous memories access, thereby can produce more current DYNAMIC MEMORY ACCESS order, thereby obtain preferable system effectiveness with this dynamic storage of interlace mode access.
According to feature of the present invention, the present invention proposes a kind of control system of storage access, it comprises system memory access order apparatus for temporary storage, memory access commands parallel processing apparatus, reaches the dynamic storage command control apparatus.This system memory access order apparatus for temporary storage is in order to temporary a plurality of system memory access orders.This memory access commands parallel processing apparatus is connected to this system memory access order apparatus for temporary storage in order to a system memory access order is decoded, to produce a plurality of DYNAMIC MEMORY ACCESS orders.DYNAMIC MEMORY ACCESS order apparatus for temporary storage is positioned at this memory access commands parallel processing apparatus, in order to temporary these a plurality of current DYNAMIC MEMORY ACCESS orders, in order to accept these a plurality of DYNAMIC MEMORY ACCESS orders, and these a plurality of current DYNAMIC MEMORY ACCESS orders are carried out priority treatment, to export a plurality of DYNAMIC MEMORY ACCESS orders with right of priority.This dynamic storage command control apparatus is connected to this memory access commands parallel processing apparatus, and from acquire a priority the DYNAMIC MEMORY ACCESS order after handling of memory access commands parallel processing apparatus, and the control command of sending at least one DYNAMIC MEMORY ACCESS is in order given at least one dynamic storage.
According to another feature of the present invention, the present invention proposes a kind of sort method of DYNAMIC MEMORY ACCESS order, it uses the right of priority of bank information table with a plurality of memory banks of writing down at least one storer, each memory bank is according to the right of priority that successively gives service time from high to low, this method comprises: (A) current system memory access order is decoded, to produce these a plurality of current DYNAMIC MEMORY ACCESS orders, wherein, each current DYNAMIC MEMORY ACCESS order corresponds at least one DYNAMIC MEMORY ACCESS order of a dynamic memory body; (B) which has the highest right of priority to judge the affiliated memory bank of a plurality of current DYNAMIC MEMORY ACCESS orders at present, sort with current DYNAMIC MEMORY ACCESS order, sort corresponding to the right of priority in this bank information table according to the memory bank of this current DYNAMIC MEMORY ACCESS order; (C) memory bank under a plurality of current DYNAMIC MEMORY ACCESS order of the highest right of priority is exported a DYNAMIC MEMORY ACCESS order.(D) whether the temporary DYNAMIC MEMORY ACCESS command set of judging the memory bank of present highest priority is empty, if not then get back to step (C), if then arrive step (E); (E) judge whether the DYNAMIC MEMORY ACCESS order under the present system memory access order has got, if not then get back to step (B), if then arrive step (A).
Description of drawings
Fig. 1 is to the synoptic diagram of different page or leaf accesses in the known DDR memory access commands.
Fig. 2 is the known use interlace mode synoptic diagram to the DDR storage access.
Fig. 3 is the block diagram of the control system of storage access of the present invention.
Fig. 4 is the process flow diagram of the sort method of DYNAMIC MEMORY ACCESS order of the present invention.
Fig. 5 (A) and Fig. 5 (B) are the synoptic diagram of the embodiment of the sort method of DYNAMIC MEMORY ACCESS order of the present invention.
Fig. 6 is the synoptic diagram of another embodiment of the sort method of DYNAMIC MEMORY ACCESS order of the present invention.
Fig. 7 is known a plurality of system memory access orders, the synoptic diagram of the DYNAMIC MEMORY ACCESS clock that is produced.
Fig. 8 is the synoptic diagram of embodiment of the sort method of known DYNAMIC MEMORY ACCESS order.
Fig. 9 is the synoptic diagram of another embodiment of the sort method of DYNAMIC MEMORY ACCESS order of the present invention.
The main element symbol description
Bank information table 322
System memory access order apparatus for temporary storage 310
Memory access commands parallel processing apparatus 320
DYNAMIC MEMORY ACCESS order apparatus for temporary storage (memory bank grouping) 321
Dynamic storage command control apparatus 340
DYNAMIC MEMORY ACCESS order apparatus for temporary storage 341
System bus arbitration device 350
System bus master control set 370
Sense data apparatus for temporary storage 390
Write data apparatus for temporary storage 395
The row address of dynamic storage " a " Ra
The column address of dynamic storage " a " Ca
The row address of dynamic storage " b " Rb
The column address of dynamic storage " b " Cb
Embodiment
See also Fig. 3, be the block diagram of the control system of storage access of the present invention, this control system 300 comprises system memory access order apparatus for temporary storage 310, memory access commands parallel processing apparatus 320, dynamic storage command control apparatus 340, system bus arbitration device 350, sense data apparatus for temporary storage 390 and writes data apparatus for temporary storage 395.
This system bus arbitration device 350 is accepted the memory access commands of at least one the system bus master control set 370 on the system bus 360, corresponding at least one system memory access order.These a plurality of system memory access orders can be the memory access commands of linear address mode memory access command or two-dimensional address pattern (starting the X address, Y address, X length and Y length).
This system memory access order apparatus for temporary storage 310 is connected to this system bus 360, with temporary a plurality of system memory access orders.
This memory access commands parallel processing apparatus 320 is connected to this system memory access order apparatus for temporary storage 310, so that a current system memory access order is decoded, to produce a plurality of DYNAMIC MEMORY ACCESS orders.
These a plurality of DYNAMIC MEMORY ACCESS orders are temporary in DYNAMIC MEMORY ACCESS order apparatus for temporary storage 321 earlier.The access command of 320 pairs of these a plurality of dynamic memory bodies of this DYNAMIC MEMORY ACCESS order parallel processing apparatus, when carrying out the selected processing of right of priority, with this current system memory access order is the border, and the selected processing of right of priority is carried out in these a plurality of current DYNAMIC MEMORY ACCESS orders of this current system memory access order.Can use the bank information table when carrying out the selected processing of right of priority, decide the memory access commands right of priority of the memory bank of each DYNAMIC MEMORY ACCESS order.
The access time of the affiliated dynamic memory body of DYNAMIC MEMORY ACCESS orders successively and gives from high to low right of priority before this previous system memory access commands of this bank information table 322 record a plurality of.Carry out priority treatment according to this bank information table 321, wherein, have highest priority from original (reset mode or timeout mode) or least-recently-used memory bank.
Dynamic storage command control apparatus 340 is connected to this memory access commands parallel processing apparatus 320 and at least one dynamic storage 380, in order to receiving these a plurality of current DYNAMIC MEMORY ACCESS orders, and memory access commands parallel processing apparatus 320 is required the access command of next dynamic storage.And the memory access commands parallel processing apparatus can be according to the right of priority output DYNAMIC MEMORY ACCESS order of each dynamic memory body, to DYNAMIC MEMORY ACCESS order apparatus for temporary storage 341.
This dynamic storage command control apparatus 340 according to the order of the memory access commands of DYNAMIC MEMORY ACCESS order apparatus for temporary storage 341, sends the DYNAMIC MEMORY ACCESS order to dynamic storage 380.
This sense data apparatus for temporary storage 390 is connected to this dynamic storage command control apparatus 340 and this system bus 360, with temporary data of being read by this dynamic storage 380.This writes data apparatus for temporary storage 395 and is connected to this dynamic storage command control apparatus 340 and this system bus 360, with the temporary data of desiring to write this dynamic storage 380.Thus quickening access speed, and then promote the usefulness of this control system 700 to this dynamic storage 380.
This memory access commands parallel processing apparatus 320 is according to these a plurality of current DYNAMIC MEMORY ACCESS orders after sorting, to being stored in this sense data apparatus for temporary storage 390 and this data that write data apparatus for temporary storage 395 sort, with these a plurality of current DYNAMIC MEMORY ACCESS orders after symbol and the corresponding ordering.
Fig. 4 is the process flow diagram of the sort method of DYNAMIC MEMORY ACCESS order of the present invention, it uses the right of priority of bank information table 322 with a plurality of memory banks of writing down at least one dynamic storage 380, wherein, each memory bank quilt is according to the right of priority that successively gives service time from high to low.See also Fig. 5, Fig. 5 is the synoptic diagram of the embodiment of the sort method of DYNAMIC MEMORY ACCESS order of the present invention.Shown in Fig. 5 (A), the right of priority 323 of the memory bank A～D of this at least one storer 380 of bank information table 322 record, wherein the few more representative right of priority of numeral is high more, according to access time of a plurality of memory banks of this at least one dynamic storage 380 successively, give right of priority from high to low.Promptly in this bank information table 322, memory bank B is used at first, so have highest priority.
At first in step (A), 320 pairs of current system memory access orders of this memory access commands parallel processing apparatus are decoded, to produce these a plurality of current DYNAMIC MEMORY ACCESS orders, wherein, each current DYNAMIC MEMORY ACCESS order is carried out access corresponding to a memory bank of dynamic storage 380.
Shown in Fig. 5 (A), 320 pairs of system memory access orders of this memory access commands parallel processing apparatus are decoded, produce corresponding a plurality of current DYNAMIC MEMORY ACCESS order respectively, and it is should a plurality of current DYNAMIC MEMORY ACCESS orders be temporary in this DYNAMIC MEMORY ACCESS order apparatus for temporary storage 321, and affiliated dynamic memory body grouping is temporary wherein.
This first system memory access order produces the current DYNAMIC MEMORY ACCESS order (501,502) that memory bank A and memory bank B are read 32 bytes after decoding.This second system memory access order produces the current DYNAMIC MEMORY ACCESS order (511,512,513,514) of memory bank B, memory bank A, memory bank C and memory bank D being read 32 bytes respectively after decoding.The information that is stored in this moment in this dynamic memory body information table 322 is the information of the memory bank access priority under the previous DYNAMIC MEMORY ACCESS order, and its information represents each memory bank by information before and after the time of precharge, activation and access.The characteristic of dynamic storage be to same memory bank not the access command of same page the clock period standard of strong (harsh) is arranged, based on this characteristic, be important techniques very so utilize previous memory bank access information successively, to promote the usefulness of storage access.
In step (B), judge that A dynamic memory body access command collects or B dynamic memory body access command collection which has higher right of priority.This step decides according to the bank information that bank information table 322 is write down.
Shown in Fig. 5 (A), this current DYNAMIC MEMORY ACCESS order (501,502) memory bank A and memory bank B are read 32 bytes, and the DYNAMIC MEMORY ACCESS order that has highest priority in present bank information table 322 in the memory bank that memory bank B is write down, so this current DYNAMIC MEMORY ACCESS order (501,502) higher right of priority belongs to this B dynamic memory body access command collection (502), promptly enters step (C) and step (D).Got the access command of all B dynamic memory bodies when dynamic storage command control apparatus 340, can reenter in the step (B).Selecting the next one again has the memory bank of highest priority.
Next A dynamic memory body access command collection (501) is left in the first system memory access order.So enter again in the step (B), select A dynamic memory body access command to collect (501) automatically and be the highest dynamic memory body of the next one (Bank-A) access command collection (501).This memory command parallel processing apparatus 320, current DYNAMIC MEMORY ACCESS order (501 to the DYNAMIC MEMORY ACCESS command set of this first system storage, 502) sort, sort corresponding to the right of priority in this bank information table 322 according to the memory bank of this current DYNAMIC MEMORY ACCESS order.When priority treatment is carried out in 320 pairs of these a plurality of DYNAMIC MEMORY ACCESS orders of this memory command parallel processing apparatus, with this current system memory access order is the border, and priority treatment is carried out in these a plurality of current DYNAMIC MEMORY ACCESS orders (501,502) in this current system memory access order.Promptly these memory command parallel processing apparatus 320 elder generations are to these a plurality of current DYNAMIC MEMORY ACCESS orders (501 of this first system memory access order, 502) carry out after priority treatment finishes, just can be to these a plurality of current DYNAMIC MEMORY ACCESS orders (511 of this next one system memory access order, 512,513,514) carrying out right of priority selects to handle.
Because in this bank information table 322, the right of priority of memory bank B is higher than the right of priority of memory bank A, so when this memory command parallel processing apparatus 320 carried out priority treatment, the right of priority of current DYNAMIC MEMORY ACCESS order 502 can be higher than the right of priority of current DYNAMIC MEMORY ACCESS order 501.
Because the current DYNAMIC MEMORY ACCESS order (501 that this first system memory access order is produced, 502) all belong to this first system dynamic memory access command collection, the DYNAMIC MEMORY ACCESS command set that the second system memory access order is produced, will be after the priority treatment of finishing the current DYNAMIC MEMORY ACCESS order that the first system memory access order produced, reset the information of bank information table 322 again, and carry out the priority treatment of the DYNAMIC MEMORY ACCESS command library of its DYNAMIC MEMORY ACCESS command set.
After priority treatment was finished in the current DYNAMIC MEMORY ACCESS order that 320 pairs of these first system memory access orders of this memory command parallel processing apparatus are produced, this memory command parallel processing apparatus 320 can upgrade the priority ranking of the memory bank in this bank information table 322.At this moment, shown in Fig. 5 (B),, be exactly memory bank D so have the memory bank of highest priority because memory bank D has become the memory bank that was used the earliest.
This second system memory access order produces the current DYNAMIC MEMORY ACCESS order (511,512,513,514) of memory bank B, memory bank A, memory bank C and memory bank D being read 32 bytes respectively after decoding.Because current DYNAMIC MEMORY ACCESS order (511,512,513,514) memory bank B, memory bank A, memory bank C and memory bank D are read 32 bytes, this current DYNAMIC MEMORY ACCESS order (511,512,513,514) belong to the DYNAMIC MEMORY ACCESS command set of this current system memory access order.
Priority treatment is carried out in a plurality of current DYNAMIC MEMORY ACCESS orders of this of 320 pairs of these second system memory access orders of this memory command parallel processing apparatus (511,512,513,514).In this bank information table 322, memory bank right of priority height ordering respectively is memory bank D, memory bank C, memory bank B and memory bank A.Shown in Fig. 5 (B), after this memory command parallel processing apparatus 320 carries out priority treatment, the right of priority of current DYNAMIC MEMORY ACCESS order 514 is the highest, next is current DYNAMIC MEMORY ACCESS order 513, secondly be current DYNAMIC MEMORY ACCESS order 511 again, and the right of priority of current DYNAMIC MEMORY ACCESS order 512 is minimum.
Fig. 6 is the synoptic diagram of another embodiment of the sort method of DYNAMIC MEMORY ACCESS order of the present invention.As shown in Figure 6, the right of priority of a recording storage body C and memory bank D in this bank information table 322, because memory bank A and memory bank B be not before by access, so its right of priority field record " T ", overtime or to represent it not by access, this moment, the bank information table represented that memory bank A and memory bank B have the highest preferential memory bank, select memory bank A or memory bank B all can earlier.320 pairs the 3rd memory access commands of this memory access commands parallel processing apparatus are decoded, produce corresponding a plurality of current DYNAMIC MEMORY ACCESS order (611 respectively, 612,613,614), and should a plurality of current DYNAMIC MEMORY ACCESS orders (611,612,613,614) be temporary in this DYNAMIC MEMORY ACCESS order apparatus for temporary storage 321, wherein, be memory bank A, memory bank B, memory bank C and memory bank D in regular turn according to the result after the memory bank priority treatment.
As shown in Figure 6, this current DYNAMIC MEMORY ACCESS order (613,614) memory bank C and memory bank D are read 32 bytes, if and the DYNAMIC MEMORY ACCESS command library of memory bank C and memory bank D respectively and the memory bank DYNAMIC MEMORY ACCESS order of in this bank information table 322, being write down be same page, just the DYNAMIC MEMORY ACCESS order of memory bank C and memory bank D need not done the dynamic storage order that dynamic storage precharge and dynamic storage start at present, so can be with current DYNAMIC MEMORY ACCESS order (613,614) belong to the DYNAMIC MEMORY ACCESS command set of highest priority, wherein, select memory bank C or memory bank D all can earlier.As Fig. 7 is another example, and the A data base of storer is read, and this is read as reading of eight data of burst type.For the second time the A memory bank of this storer and B memory bank being carried out two-dimensional memory reads, be read as for the second time the A memory bank is carried out the reading of six data of burst type, B memory bank (Bank-B) is carried out the reading of six data of burst type, the A memory bank is carried out the reading of six data of burst type, the B memory bank is carried out the reading of six data of burst type, the A memory bank is carried out the reading of six data of burst type, at last the B memory bank carried out reading of six data of burst type, promptly in the DYNAMIC MEMORY ACCESS result who does not use when resetting the DYNAMIC MEMORY ACCESS order.As Fig. 8 is another example, and the A memory bank of storer is read, and this is read as reading of eight data of burst type.For the second time the A memory bank of this storer and B memory bank being carried out two-dimensional memory reads, be read as for the second time the A memory bank is carried out the reading of six data of burst type, the B memory bank is carried out the reading of six data of burst type, the A memory bank is carried out the reading of six data of burst type, the B memory bank is carried out the reading of six data of burst type, the A memory bank is carried out the reading of six data of burst type, at last the B memory bank carried out reading of six data of burst type, the DYNAMIC MEMORY ACCESS result after promptly using the known technology algorithm to sort.As Fig. 9 is another example, and the A memory bank of storer is read, and this is read as reading of eight data of burst type.For the second time the A memory bank of this storer and B memory bank being carried out two-dimensional memory reads, be read as for the second time the A memory bank is carried out the reading of six data of burst type, the B memory bank is carried out the reading of six data of burst type, the A memory bank is carried out the reading of six data of burst type, the B memory bank is carried out the reading of six data of burst type, the A memory bank is carried out the reading of six data of burst type, at last the B memory bank carried out reading of six data of burst type, the DYNAMIC MEMORY ACCESS result after promptly using this algorithm to sort.When moment T0, Memory Controller is to the A memory bank output precharge command of this storer.When moment T2, Memory Controller is to the B memory bank output precharge command of this storer.When moment T3, Memory Controller is to the A memory bank output activation command of this storer.When moment T5, Memory Controller is to the B memory bank output activation command of this storer, and the previous activation command of this activation command and elder generation belongs to different bank, so be not subjected to the restriction of tRC=11 in the description.When moment T6, Memory Controller is to the A memory bank output reading order of this storer.The rest may be inferred, no longer describes in detail.
In other embodiment, when the right of priority of the DYNAMIC MEMORY ACCESS command set of 320 pairs of dynamic memory bodies of this memory command parallel processing apparatus is handled, also can sort according to the access byte population size of current DYNAMIC MEMORY ACCESS order.
As shown in the above description, how known technology does not disclose to DYNAMIC MEMORY ACCESS order and sorts, and then the lower delay of acquisition, memory command parallel processing apparatus 320 of the present invention is according to the right of priority in the bank information table 322, earlier to the order of triangular web memory access, DYNAMIC MEMORY ACCESS order at least one dynamic memory body is decoded, and these a plurality of DYNAMIC MEMORY ACCESS orders are carried out priority treatment, and then produce more current DYNAMIC MEMORY ACCESS order with this dynamic storage 380 of interlace mode access, postpone to promote whole access speed in order to reduce, and obtain better system effectiveness.
From the above, no matter the present invention all shows it be different from the feature of known technology, have practical value with regard to purpose, means and effect.But it should be noted that above-mentioned many embodiment only give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claims are described, but not only limits to the foregoing description.
Claims (16)
1. the control system of a storage access comprises:
System memory access order apparatus for temporary storage is in order to temporary a plurality of system memory access orders;
The memory access commands parallel processing apparatus, be connected to this system memory access order apparatus for temporary storage, in order to a current system memory access order is decoded, and then a plurality of current DYNAMIC MEMORY ACCESS order of access is carried out in generation to memory bank, and be temporary in the DYNAMIC MEMORY ACCESS order apparatus for temporary storage, and priority treatment is carried out in these a plurality of current DYNAMIC MEMORY ACCESS orders;
The dynamic storage command control apparatus, be connected to this memory access commands parallel processing apparatus and dynamic storage, in order to receive through these a plurality of current DYNAMIC MEMORY ACCESS orders after the aforementioned priority processing, and then according to the order that obtains these a plurality of current DYNAMIC MEMORY ACCESS orders, the control command of sending this DYNAMIC MEMORY ACCESS is to this dynamic storage; And
The sense data apparatus for temporary storage is connected to this dynamic storage command control apparatus and this system bus, in order to temporary data of being read by this dynamic storage, as the order rearrangement use of system storage order data.
2. control system according to claim 1, it further comprises:
The system bus arbitration device is accepted the memory access commands of the system bus master control set on this system bus, and then produces these corresponding a plurality of system memory access orders.
3. control system according to claim 2, it further comprises:
Write the data apparatus for temporary storage, be connected to this dynamic storage command control apparatus and this system bus, with the temporary data of desiring to write this dynamic storage.
4. control system according to claim 1, wherein, these a plurality of system memory access orders can be linear address mode memory access command or two-dimensional address mode memory access command.
5. control system according to claim 4, wherein, the DYNAMIC MEMORY ACCESS order that this system memory access command decode is a memory bank.
6. control system according to claim 1, wherein, when this memory access commands parallel processing apparatus carries out the aforementioned priority processing to these a plurality of DYNAMIC MEMORY ACCESS orders, with this current system memory access order is the border, and then aforementioned priority is carried out in these a plurality of current DYNAMIC MEMORY ACCESS orders of this current system memory access order handle.
7. control system according to claim 6, wherein, this dynamic storage is a synchronous dynamic random access memory.
8. according to 7 described control system of claim the, wherein, this synchronous dynamic random access memory has a plurality of memory banks.
9. control system according to claim 1, wherein, this memory access commands parallel processing apparatus further comprises the bank information table, with write down a plurality of before the order of memory bank under the DYNAMIC MEMORY ACCESS order access before a plurality of in the system memory access orders.
10. control system according to claim 9, wherein, a plurality of preceding DYNAMIC MEMORY ACCESS order in these a plurality of preceding system memory access orders of this bank information table record is to the priority of a plurality of memory bank access time, and then appointment right of priority from high to low.
11. control system according to claim 10, wherein, when this memory access commands parallel processing apparatus to this a plurality of current DYNAMIC MEMORY ACCESS orders of this in current system memory access order carry out aforementioned priority when handling, carry out aforementioned priority according to this bank information table and handle also and then export to the dynamic storage command control apparatus, wherein, this memory access commands parallel processing apparatus is set at least-recently-used memory bank has highest priority, when memory bank does not have new system memory access order that this memory bank is carried out access above the schedule time that sets, this this memory bank of memory access commands parallel processing apparatus is set to overtime memory bank, when new dynamic storage order was carried out access to this memory bank, this memory access commands parallel processing apparatus was set at this memory bank the memory bank with this highest priority.
12. the sort method of a DYNAMIC MEMORY ACCESS order, it uses the right of priority of bank information table with a plurality of memory banks in the record dynamic storage, these a plurality of memory banks successively give this different right of priority respectively according to service time, and this sort method comprises:
(A) current system memory access order is decoded, to produce these a plurality of current DYNAMIC MEMORY ACCESS orders, wherein, each this current DYNAMIC MEMORY ACCESS order is carried out access to the memory bank in this dynamic storage;
(B) judge that these a plurality of current DYNAMIC MEMORY ACCESS orders in present this dynamic memory body have highest priority;
(C) output has the current DYNAMIC MEMORY ACCESS order in the dynamic memory body of this highest priority, and then upgrade right of priority table in this memory bank, judge that again these a plurality of current DYNAMIC MEMORY ACCESS orders in present which dynamic memory body have this highest priority, affiliated a plurality of current DYNAMIC MEMORY ACCESS order is all exported and is finished in this system storage; And
(D) a plurality of current DYNAMIC MEMORY ACCESS order affiliated in the next system storage is sorted.
13. sort method according to claim 12, wherein, in step (B) and step (C), according to the access length scale of this current DYNAMIC MEMORY ACCESS order and the first order of priority of carrying out this dynamic memory body afterwards of use of this memory bank.
14. sort method according to claim 13, wherein, the access time of a plurality of preceding DYNAMIC MEMORY ACCESS memory banks that order uses before this bank information table record is somebody's turn to do in a plurality of system memory access orders successively, access length population size according to current DYNAMIC MEMORY ACCESS order has programmable weight again, and then gives this right of priority from high to low.
15. sort method according to claim 13, wherein, the memory bank and the memory bank page number that a plurality of preceding DYNAMIC MEMORY ACCESS order before this bank information table record is somebody's turn to do in a plurality of system memory access orders is used, if the memory bank page number in this current DYNAMIC MEMORY ACCESS order and bank information epiphase then give this highest priority simultaneously.
16. sort method according to claim 12, wherein, this dynamic storage is a synchronous dynamic random access memory.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102404652A (en) * | 2010-09-10 | 2012-04-04 | 高通创锐讯通讯科技(上海)有限公司 | Double data rate (DDR) buffer Ethernet network package method for optical line terminal (OLT) or optical network unit (ONU) chip in Ethernet passive optical network (EPON) |
| CN102693195A (en) * | 2011-03-24 | 2012-09-26 | 凌阳科技股份有限公司 | Access system and method of memory by utilizing frequency width of optimal synchronous memory |
| CN105409229A (en) * | 2014-05-28 | 2016-03-16 | 索尼公司 | Information processing apparatus, information processing method, and program |
| CN105938418A (en) * | 2015-03-06 | 2016-09-14 | 爱思开海力士有限公司 | Memory system and operation method thereof |
| CN105988951A (en) * | 2015-02-12 | 2016-10-05 | 瑞昱半导体股份有限公司 | Memory controller and related control method |
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| US6683816B2 (en) * | 2001-10-05 | 2004-01-27 | Hewlett-Packard Development Company, L.P. | Access control system for multi-banked DRAM memory |
| WO2004068349A1 (en) * | 2003-01-27 | 2004-08-12 | Matsushita Electric Industrial Co., Ltd. | Memory control device |
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| CN102404652A (en) * | 2010-09-10 | 2012-04-04 | 高通创锐讯通讯科技(上海)有限公司 | Double data rate (DDR) buffer Ethernet network package method for optical line terminal (OLT) or optical network unit (ONU) chip in Ethernet passive optical network (EPON) |
| CN102693195A (en) * | 2011-03-24 | 2012-09-26 | 凌阳科技股份有限公司 | Access system and method of memory by utilizing frequency width of optimal synchronous memory |
| CN105409229A (en) * | 2014-05-28 | 2016-03-16 | 索尼公司 | Information processing apparatus, information processing method, and program |
| CN105988951A (en) * | 2015-02-12 | 2016-10-05 | 瑞昱半导体股份有限公司 | Memory controller and related control method |
| CN105988951B (en) * | 2015-02-12 | 2019-10-15 | 瑞昱半导体股份有限公司 | Memory Controller and relevant control method |
| CN105938418A (en) * | 2015-03-06 | 2016-09-14 | 爱思开海力士有限公司 | Memory system and operation method thereof |
| CN105938418B (en) * | 2015-03-06 | 2020-05-08 | 爱思开海力士有限公司 | Storage system and operation method thereof |
| CN106681804A (en) * | 2015-11-10 | 2017-05-17 | 慧荣科技股份有限公司 | Storage device and task execution method thereof, and host corresponding to the storage device and task execution method thereof |
| CN106681804B (en) * | 2015-11-10 | 2020-05-19 | 慧荣科技股份有限公司 | Storage device, host corresponding to storage device and task execution method thereof |
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