CN101764616B - Sigma-delta modulator with width input range - Google Patents

Abstract

The invention discloses a sigma-delta modulator (SDM) with a width input range. The sigma-delta modulator (SDM) is characterized by comprising over 2 stages of integrators, wherein an output signal of each integrator is the sum of an input signal and the output signal of a previous time unit system; the sigma-delta modulator at least comprises n integrators, wherein n is greater than or equal to 2; in every two integrators, the output signal end of the preceding stage of the integrator is connected with the input signal end of the post stage of the integrator; the current output feedback signal end of the post stage of the integrator is connected with the input signal end of the preceding stage of the integrator; and the output feedback signal end of a system is connected with the input signal end of each stage of the integrator. Compared with the SDM with the conventional structure, the SDM with the structure of the invention can greatly increase the stable input range of signals on the basis of ensuring the overall performance of the SDM.

Description

A kind of sigma-delta modulator with wide input range

Technical field

The present invention relates to ∑-sigma-delta modulator in the IC design (SDM) technical field, particularly on the basis that guarantees ∑-sigma-delta modulator overall performance, increase a kind of ∑-sigma-delta modulator of signal stabilization input range with wide input range.

Background technology

∑-sigma-delta modulator technology has the characteristic of noise shaping, can the noise harmonic that produce in the quantizing process be pushed away toward high frequency band, and then reach the digital-to-analogue conversion of high-res, so ∑-sigma-delta modulator technology is widely used in many fields.

Along with the SDM exponent number increases, the noise shaping effect will be that significantly overall performance is good more more, but when the exponent number of SDM during greater than second order, can cause stable problem, cause stablizing input range and receive very big restriction.

Along with the SDM exponent number increases, stable input range is more little, when recovering stablizing signal outside the input range; Do not reach the recovery index of requirement, even can not recover fully, thereby cause distorted signals; As shown in Figure 1; Thereby can have a strong impact on the performance of system,, thereby can make systematic function more stable if therefore can enlarge input range.

Summary of the invention

The present invention is directed to above-mentioned technical problem, proposed a kind of ∑-sigma-delta modulator with wide input range, the SDM of this structure compares with the SDM of traditional structure, can on the basis that guarantees the SDM overall performance, increase considerably the signal stabilization input range.

Technical scheme of the present invention is following:

A kind of ∑-sigma-delta modulator with wide input range is characterized in that: the integrator by more than 2 grades is formed, and the output signal of integrator is input signal and previous chronomere system output signal sum.

Said ∑-sigma-delta modulator is made up of n integrator at least, wherein n＞2;

The output signal end of the previous stage integrator in per 2 integrators is connected with the input signal end of back one-level integrator; The current output feedback signal end of back one-level integrator is connected with the input signal end of previous stage integrator, and system's output feedback signal end is connected with each grade integrator input signal end.

The input signal of the 1st grade of integrator is: current output signal * feedback factor (b of input signal (X)-the 2nd grade integrator ₁)-system output signal (Y) * feedback factor (c ₁);

The input signal of the 2nd to n-1 level integrator is respectively: [the 1st grade of integrator output signal (y ₁) * gain coefficient (a ₁Output signal * feedback factor (b of)-3rd level integrator ₂)-system output signal (Y) * feedback factor (c ₂)] ..., [(n-2) level integrator output signal (y _N-2) * gain coefficient (a _N-2Output signal * feedback factor (b of)-n level integrator _N-1)-system output signal (Y) * feedback factor (c _N-1)];

The input signal of n level integrator is: n-1 level integrator output signal (y _N-1) * gain coefficient (a _N-1)-system output signal (Y) * feedback factor (c _n);

The final output signal of system (Y) is n level integrator output signal (y _n) and quantizing noise input signal (E) sum.

In the SDM structure of the present invention, the feedback loop (b between every grade of integrator _m, b _M-1M=1 ..., n) overlap mutually, compare with traditional SDM structure, on the basis that guarantees the SDM overall performance, reduced the complexity of SDM circuit, increased considerably the stable input range of signal.

Beneficial effect of the present invention is following:

SDM with structure of the present invention compares with the SDM of traditional structure, can on the basis that guarantees the SDM overall performance, increase considerably the signal stabilization input range.

Description of drawings

Fig. 1 is the signal waveform sketch map of various recovery extent

Fig. 2 is the structural representation of the present invention 3 rank SDM

Fig. 3 is applied to the structured flowchart of DAC for SDM of the present invention

Fig. 4 is the structural representation of original SDM

Specific embodiment

A kind of ∑-sigma-delta modulator with wide input range is characterized in that: the integrator by more than 2 grades is formed, and the output signal of integrator is input signal and previous chronomere system output signal sum.

Said ∑-sigma-delta modulator is made up of n integrator at least, wherein n＞2;

The output signal end of the previous stage integrator in per 2 integrators is connected with the input signal end of back one-level integrator; The current output feedback signal end of back one-level integrator is connected with the input signal end of previous stage integrator, and system's output feedback signal end is connected with each grade integrator input signal end.

As shown in Figure 2, native system is composed in series by three integrator unit.

The input signal of first order integrator is made up of three parts: input signal (X), current output signal * feedback factor (b of second level integrator ₁), system output signal (Y) * feedback factor (c ₁).

The input signal of second level integrator is made up of three parts: first order integrator output signal (y ₁) * gain coefficient (a ₁), output signal * feedback factor (b of third level integrator ₂), system output signal (Y) * feedback factor (c ₂).

The input signal of third level integrator is made up of two parts: second level integrator output signal (y ₂) * gain coefficient (a ₂), system output signal (Y) * feedback factor (c ₃).

The final output signal of system (Y) is third level integrator output signal (y ₃) import (E) sum with quantizing noise.

The SDM of different structure has a great difference to the compacting ability of noise, and three rank SDM rational in infrastructure can exceed structure fully to capability of restraining noise and owe rational five rank SDM.

In the present embodiment 3 rank SDM structures, the feedback loop (b between every grade of integrator ₁, b ₂) overlap mutually, compare with traditional SDM structure, reached the overall performance of traditional 5 rank SDM.On the basis that guarantees the SDM overall performance, reduced the complexity of SDM circuit, increased considerably the stable input range of signal.

3 rank ∑-sigma-delta modulator framework according to having said structure draws equation:

${\mathrm{<figure-callout\; id="1"\; label="y"\; filenames="H2009102164166E00022.png"\; state="\{\{state\}\}">y</figure-callout>}}_1=(X-b_1{y}_{2}z-c_{1}Y)\frac{z^{-1}}{1-z^{-1}}$

$y_2=(a_1{y}_1-b_2{y}_{3}z-c_{2}Y)\frac{z^{-1}}{1-z^{-1}}$

$y_3=(a_2{y}_2-c_{3}Y)\frac{z^{-1}}{1-z^{-1}}$

Y＝y ₃+E

Thereby draw:

$Y=\frac{a_1{a}_2}{z^3+(a_2{b}_2+a_1{\mathrm{<figure-callout\; id="1"\; label="b"\; filenames="H2009102164166E00022.png"\; state="\{\{state\}\}">b</figure-callout>}}_1+c_3-3)z^2[a_2(c_2-b_2)+(c_3-1)a_1{b}_1-2c_3+3]z+c_3-a_2{c}_2+a_1{a}_2{c}_1-1}X$

$+\frac{z^3+(a_2{b}_2+a_1{b}_1-3)z^2+(3-a_1{b}_1-a_2{b}_2)z-1}{z^3+(a_2{b}_2+a_1{\mathrm{<figure-callout\; id="1"\; label="b"\; filenames="H2009102164166E00022.png"\; state="\{\{state\}\}">b</figure-callout>}}_1+c_3-3)z^2+[a_2(c_2-b_2)+(c_3-1)a_1{b}_1-2c_3+3]z+c_3-a_2{c}_2+a_1{a}_2{c}_1-1}E$

Signal transfer function $S_{\mathrm{TF}}=\frac{Y\left(z\right)}{X\left(z\right)}$

$=\frac{a_1{a}_2}{z^3+(a_2{b}_2+a_1{\mathrm{<figure-callout\; id="1"\; label="b"\; filenames="H2009102164166E00022.png"\; state="\{\{state\}\}">b</figure-callout>}}_1+c_3-3)z^2+[a_2(c_2-b_2)+(c_3-1)a_1{b}_1-2c_3+3]z+c_3-a_2{c}_2+a_1{a}_2{c}_1-1}$

Noise transfer function $N_{\mathrm{TF}}=\frac{Y\left(z\right)}{E\left(z\right)}$

$=\frac{z^3+(a_2{b}_2+a_1{b}_1-3)z^2+(3-a_1{b}_1-a_2{b}_2)z-1}{z^3+(a_2{b}_2+a_1{\mathrm{<figure-callout\; id="1"\; label="b"\; filenames="H2009102164166E00022.png"\; state="\{\{state\}\}">b</figure-callout>}}_1+c_3-3)z^2+[a_2(c_2-b_2)+(c_3-1)a_1{b}_1-2c_3+3]z+c_3-a_2{c}_2+a_1{a}_2{c}_1-1}$

Among Fig. 2-3, wherein, X is the signal input, and E is the quantizing noise input, y ₁Be first order output, y ₂Be second level output, y ₃Be third level output, Y is the final output of system, a ₁, a ₂Be the gain coefficient of every inter-stage, b ₁, b ₂, c ₁, c ₂, c ₃Be feedback factor, z ^-1Represent that a unit interval postpones.

Can find out that the output signal is by S _TF(z) X and N _TF(z) E forms.

Because the gain coefficient a between each joint of cascade ₁, a ₂Non-vanishing, signal transfer function is always a low pass or all-pass filter, if coefficient selecting is suitable, noise transfer function can form a high pass filter that satisfies application request.Therefore; Input signal will be by complete reservation through signal transfer function, and quantization error is during through noise transfer function, and quantization error will be concentrated and push away toward high band; The quantizing noise of low-frequency band will be attenuated; Make the output signal not receive the interference of quantization error, thereby make the output signal close, reach the purpose of noise shaping with input signal in low-frequency band.

In codec (CODEC), utilize ∑-sigma-delta modulator to realize high accuracy high-performance digital to analog converter (DAC) with structure of the present invention.

Original structure SDM is as shown in Figure 4, in system, uses for many years, and its degree of stability and overall performance were accepted by system in very long a period of time.Through matlab emulation and FPGA test, can obtain comparative analysis with this structure SDM each item index.

Selecting amplitude is 1; Frequency is 1K-20K; Frequency amplification is that normal signal (sine wave) and the improper signal (sawtooth waveforms) of 1K is as the matlab test signal; Respectively signal to noise ratio (snr) and the stability of original structure SDM and structure SDM of the present invention are added up, statistics is compared analysis, as shown in table 1.

SDM	SNR (DB)	Normal signal initial value (10 -3)	Normal signal recovery value (10 -3)	Improper signal initial value (10 -3)	Improper signal recovery value (10 -3)
						Former SDM	100.94	2.16	6.66	2.16	6.86
SDM of the present invention	101.22	0.9	3.07	0.9	2.87

Table 1

According to the matlab simulation result, can draw as drawing a conclusion:

The complete irreclaimable situation of signal does not appear in the SDM test of 1 original structure.Recovery effects to normal signal slightly is better than improper signal.SNR is big, and stability better;

Stability and the SNR of 2 native system structure SDM are better than original structure SDM;

Original structure SDM and structure SDM of the present invention are carried out the FPGA test, system signal noise ratio and distortion factor plus noise (THD+N) are analyzed through audio analyzer, as shown in table 2.

SDM	SNR (DB)	THD+N (the full width of cloth) (DB)	THD+N (half range) (DB)
				Former SDM	88	-81	-77
SDM of the present invention	89	-81	-77

Table 2

According to the FPGA test result, can draw as drawing a conclusion:

SDM of the present invention has reached the overall performance of former SDM.

According to matlab emulation and FPGA test result, can draw as drawing a conclusion:

In the present embodiment, structure SDM of the present invention compares with former SDM, on the basis that guarantees the SDM overall performance, has reduced the complexity of SDM circuit, has increased considerably the stable input range of signal.

Claims (1)

1. ∑-sigma-delta modulator with wide input range, it is characterized in that: the integrator by more than 2 grades is formed, and the output signal of integrator is input signal and previous chronomere system output signal sum;

Said ∑-sigma-delta modulator is made up of n integrator at least, wherein n＞2;

The output signal end of the previous stage integrator in per 2 integrators is connected with the input signal end of back one-level integrator; The current output feedback signal end of back one-level integrator is connected with the input signal end of previous stage integrator, and system's output feedback signal end is connected with each grade integrator input signal end;

The input signal of the 1st grade of integrator is: current output signal * feedback factor (b of input signal (X)-the 2nd grade integrator ₁)-system output signal (Y) * feedback factor (c ₁);

The input signal of the 2nd to n-1 level integrator is respectively: [the 1st grade of integrator output signal (y ₁) * gain coefficient (a ₁Output signal * feedback factor (b of)-3rd level integrator ₂)-system output signal (Y) * feedback factor (c ₂)] ..., [(n-2) level integrator output signal (y _N-2) * gain coefficient (a _N-2Output signal * feedback factor (b of)-n level integrator _N-1)-system output signal (Y) * feedback factor (c _N-1)];

The input signal of n level integrator is: n-1 level integrator output signal (y _N-1) * gain coefficient (a _N-1)-system output signal (Y) * feedback factor (c _n);

The final output signal of system (Y) is n level integrator output signal (y _n) and quantizing noise input signal (E) sum.

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