CN101442296B - Digital decimation filter - Google Patents

Digital decimation filter Download PDF

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CN101442296B
CN101442296B CN 200710124780 CN200710124780A CN101442296B CN 101442296 B CN101442296 B CN 101442296B CN 200710124780 CN200710124780 CN 200710124780 CN 200710124780 A CN200710124780 A CN 200710124780A CN 101442296 B CN101442296 B CN 101442296B
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filter
decimation
digital
power
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CN101442296A (en )
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周化雨
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深圳Tcl工业研究院有限公司
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Abstract

The invention provides a digital decimation filter. The digital decimation filter comprises a CIC filter with a cascaded cosine prefilter, a compensating filter and an FIR filter which are connected sequentially. The digital decimation filter has the advantages that the digital decimation filter brings small passband landing, outputs small power of quantization noise; and the mode does not bring the increase of power consumption or brings very small increase of power consumption.

Description

一种数字抽取滤波器 A digital decimation filter

技术领域 FIELD

[0001] 本发明涉及滤波器,尤其涉及一种数字抽取滤波器。 [0001] The present invention relates to a filter, in particular to a digital decimation filter. 背景技术 Background technique

[0002] 数字抽取滤波器(Digital Decimation Filter)被应用于基于Σ -Δ调制的模数转换器(ADC)中。 [0002] The digital decimation filter (Digital Decimation Filter) modulation is applied to Σ -Δ analog to digital converter (ADC) based. 基于Σ -Δ调制的模数转换器使用过采样,噪声成形,数字抽取滤波器, 来获得较高的信噪比。 Based on Σ -Δ modulation analog to digital converter oversampling, noise shaping, digital decimation filter, to obtain a higher signal to noise ratio. 使用过采样是因为,随着倍数R的增加,量化噪声谱与信号谱重叠的分量越来越少。 Oversampling is because, with increasing multiple of R, the quantization noise spectrum signal spectrum overlapping with fewer components. 噪声成形使噪声能量集中到高频部分。 That the noise shaping to a high frequency portion of the noise energy is concentrated. 数字低通抽取滤波器在频带η/R < I ω I ^ π内消除量化噪声,而信号分量没有改变,因此提高了信噪比。 A digital decimation low-pass filter in the frequency band η / R <I ω I ^ [pi] to eliminate the quantization noise, the signal component does not change, thus improving the signal to noise ratio. 数字抽取滤波器不仅可以使用于基于Σ -Δ调制的ADC中,还可以使用于数字下变频器(DDC)和数字上变频器(DUC)中。 Digital decimation filter based not only can be used for (the DUC) in the ADC Σ -Δ modulation, may also be used in a digital converter (DDC) and the digital converter.

[0003] 数字抽取滤波器的目的是为了使过采样速率为fs的数字信号通过滤波和下采样恢复到Nyquist速率fN的信号,并同时尽量只保留|ω|彡π/R内的信号,而滤出带外噪声。 [0003] The purpose of the digital decimation filter is to make the oversampling rate fs of the digital signal to the signal Nyquist rate fN restored by filtering and downsampling, and as far as possible while retaining only | [omega] | signals within San π / R, and filtered off band noise. 它实际上就充当噪声成型后的截止频率为|ω|向彡π/R的低通滤波器的角色。 After the cut-off frequency it is actually acts as a noise shaping | [omega] | San role to a low pass filter π / R's. R又称为样本速率改变因子,R= fs/fN。 R also known as sample rate change factor, R = fs / fN. 由Nyquist采样定理,则我们感兴趣的模拟信号最大频率fc 彡fN/2 = fs/2R,当归一化fs/2 为Ji,则ω c 彡π /R,其中ω c = 2 π fc。 The maximum frequency fc of an analog signal fN San by the sampling theorem Nyquist, then we are interested / 2 = fs / 2R, the normalization fs / 2 is Ji, then ω c San π / R, where ω c = 2 π fc.

[0004] 级联积分梳状(Cascaded htegrator-Comb,简写为CIC)滤波器有结构简单的特点(当使用积分-抽取-微分的结构时,没有乘法运算),因此一般在前端使用低阶的CIC 滤波器。 [0004] The cascaded integrator-comb (Cascaded htegrator-Comb, abbreviated as CIC) filter has a simple structural features (when using the integral - extraction - structural differential, no multiplication), and therefore generally used in the low-order front end CIC filter. 当经过Cic滤波器后,速率下降Rl倍。 When the filter after Cic, Rl fold rate decreases. 在较低速率时,可以使用通带内波动小,阻带衰减很快的HR滤波器。 At lower rates, you can fluctuate within a small passband, stopband attenuation HR filter quickly. 这样的HR滤波器的抽头数较多,但由于工作在低速率下,因此带来的复杂度的增加不大。 Such a filter tap number HR more, but due to work at a low rate, so little to bring increased complexity.

[0005] N阶的CIC滤波器为H(Z) = ((ΐ-ζΐ/α-ζ—1),,其中N是阶数。在数字抽取滤波器的前端使用CIC滤波器的原因是实现简单,但使用nR结构时没有乘法,而且当N较大时,它的旁瓣衰减较大。一般情况下,抽取因子R是2的L幂次,即R = 2l,则CIC滤波器的传递函数可写为孖(ζ) = (1 + γ (1 +厂2广…(1 + 1广。因此CIC滤波器可以实现为级联的滤波-2倍抽取形式。 [0005] N is the order of the CIC filter H (Z) = ((ΐ-ζΐ / α-ζ-1) ,, where N is the order. Reason decimation filter in the digital front end is implemented using the CIC filter simple structure without using multiplication nR, and when large N, which is large sidelobe attenuation. typically, R is the decimation factor L is a power of 2, i.e., R = 2l, the transmission of the CIC filter Margin function can be written as (ζ) = (1 + γ (1 + 2 factory wide ... (1 + 1 wide. Thus CIC decimation filter may be implemented in the form of minus two times the filter cascade.

[0006] 一般度量抽取滤波器性能,有两个指标:(1)通带降落:有用信号带宽(感兴趣频带)内滤波器的最大衰减。 [0006] Usually decimation filter performance metric, there are two indicators: (1) the passband Landing: maximum attenuation of the useful signal bandwidth (a frequency band of interest) within the filter. (¾混叠误差:折叠到有用信号带宽内的衰减量。混叠误差是比较关键的一项。模拟信号在被抽样后,会以抽样频率fs为中心周期性重复出现频谱,当抽样速率下降到fs/R,则会以fs/R为中心周期性重复出现频谱。因此抽取R倍后,在Rfs/ Rf。,kfs/R+f。]的频带会混叠到感兴趣的频带中,其中k= 1,2,...,LR/2」。当归一化fj2为π,则[2k/R-co。Jk/R+co。]的频带会混叠到感兴趣的频带中,这些频带被称为混叠 (¾ aliasing errors: folded attenuation bandwidth of the useful signal aliasing errors are more critical an analog signal after being sampled, the sampling frequency fs will be periodically repeated spectrum centered, when the sampling rate decreases. to fs / R, the center will be periodically repeated at frequency spectrum fs / R is therefore the decimation is R times, the Rfs / Rf., kfs / R + f.] in a frequency band will be aliased into the frequency band of interest, where k = 1,2, ..., LR / 2. "is the normalized fj2 [pi], then [2k / R-co.Jk / R + co.] will be aliased into the frequency band of the frequency band of interest, these bands are known as aliasing

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[0007] CIC滤波器的通带下降较大,通带下降的增加导致了带宽的减小。 [0007] CIC filter passband large drop, resulting in an increase in drop passband bandwidth is reduced. 一般在抽取后增加一个补偿滤波器来补偿通带的下降。 After taking a general increase in compensation filter passband drop compensation. 高阶的CIC滤波器的阻带衰减较大,但是通带的降落也较大,引起带宽减小,通过补偿后能使通带比较平坦,但同时会放大阻带。 Higher order CIC filter stopband attenuation is large, but the pass band is large drop, bandwidth reduction caused by the relatively flat passband can be compensated, but will stop band amplification. 阶数越高,通 The higher the order, through

3带需要补偿的越多,引起阻带的放大越大,而且高阶的CIC滤波器的补偿滤波器的通带波动很大,引起补偿后的CIC滤波器的通带的波动也很大。 3 to be compensated with more, causing greater stopband enlarged, and a large compensation filter passband higher order CIC filter, causing the compensated CIC filter passband is also a great fluctuation. 增大补偿滤波器的抽头数可以改善通带的波动,但代价是复杂度的增加。 Increasing the number of taps of the compensation filter passband fluctuation can be improved, but the expense of increased complexity.

[0008] 请参阅图1,现有的数字抽取滤波器包括CIC滤波器和级联的余弦预滤波器。 [0008] Referring to FIG. 1, a conventional digital decimation filter comprises a cosine filter and a pre-filter cascaded CIC. 现有的数字抽取滤波将级联的余弦预滤波器放在CIC滤波器后,但是现有的数字抽取滤波的缺点在于:没有对其进行通带降落的补偿,因此通带降落较大。 After conventional digital decimation filtering the pre-filter in a cascade of the CIC filter cosine, but the disadvantages of the prior digital decimation filter are: passband not be compensated landing, landing so large passband.

发明内容 SUMMARY

[0009] 本发明的目的在于提供一种数字抽取滤波器,旨在解决现有的数字抽取滤波器的没有对其进行通带降落的补偿,通带降落较大的问题。 [0009] The object of the present invention is to provide a digital decimation filter, to solve the conventional compensated digital decimation filter passband without its landing, landing passband major problems.

[0010] 本发明的技术方案是这样实现的,本发明的数字抽取滤波器包括带级联的余弦预滤波器的Cic滤波器、补偿滤波器和HR滤波器,所述带级联的余弦预滤波器的CIC滤波器、补偿滤波器和HR滤波器依次相连,所述补偿滤波器通过“频率采样法”生成,且所述补偿滤波器的频响为被补偿的滤波器的幅响的倒数。 Pre-cosine [0010] aspect of the present invention is achieved, according to the present invention is a digital decimation filter comprises a pre-filter with a cosine Cic cascaded filters, the compensation filters and HR filters, cascaded with the CIC filter, the filter compensation filters and HR filters are connected in sequence by said compensation filter "frequency sampling method" generation, and the compensation filter frequency response compensated amplitude response filter reciprocal .

[0011] 本发明采取的技术方案还包括:所述补偿滤波器是30阶、16位增益的补偿滤波器。 [0011] The technical solution of the present invention taken further comprising: a compensation filter order is 30, 16-bit gain compensation filter.

[0012] 本发明采取的技术方案还包括:所述数字抽取滤波器的带级联的余弦预滤波器的CIC滤波器包括CIC滤波器和带级联的余弦预滤波器。 [0012] The present invention takes the technical scheme further comprises: the cosine digital decimation filter with a pre-filter cascaded CIC filter comprises a cosine filter and a pre-filter with cascaded CIC.

[0013] 本发明采取的技术方案还包括:所述级联余弦预滤波器ζ变换形式为: [0013] The present invention takes the technical scheme further comprises: a cascade cosine transform of the pre-filter is a ζ:

Figure CN101442296BD00041

[0014]其中 [0014] in which

Figure CN101442296BD00042

[0015] 本发明采取的技术方案还包括:所述级联余弦预滤波器ζ变换形式为: [0015] The present invention takes the technical scheme further comprises: a cascade cosine transform of the pre-filter is a ζ:

[0016] [0016]

Figure CN101442296BD00043

[0017]其中 Hcic(Z) = 1/2(1+2-1), [0017] wherein Hcic (Z) = 1/2 (1 + 2-1),

Figure CN101442296BD00044

[0019] Hcos(Z) = 1/4(Z+Z-1)+1/8(Z2+Z-2)+1/4。 [0019] Hcos (Z) = 1/4 (Z + Z-1) +1/8 (Z2 + Z2) +1/4.

[0020] 本发明采取的技术方案还包括:所述级联余弦预滤波器ζ变换形式为: [0020] The present invention takes the technical scheme further comprises: a cascade cosine transform of the pre-filter is a ζ:

[0021] [0021]

Figure CN101442296BD00045

[0022]其 中Hcic(Z) = 1/2(1 + 2-1), [0022] in which Hcic (Z) = 1/2 (1 + 2-1),

Figure CN101442296BD00046

[0023] Hcos(Z) = 1/4(Z+Z-1)+1/8(Z2+Z-2)+1/4。 [0023] Hcos (Z) = 1/4 (Z + Z-1) +1/8 (Z2 + Z2) +1/4.

[0024] [0024]

[0025] 本发明的有益效果在于:本发明的数字抽取滤波器引入CIC加级联余弦预滤波器加补偿再加FIR滤波器的方式,级联余弦预滤波器可以加大阻带衰减而不引起通带的大的波动,补偿使通带变得较平坦,而FIR滤波器减小过渡带长度,这种方式的输出量化噪声功率较小,而且这种方式带来的功耗增加也不大。 [0025] Advantageous effects of the present invention is that: a digital decimation filter of the present invention is introduced into the compensation plus plus plus FIR filter cascaded CIC manner prefilter cosine, cosine cascade of prefilter can not increase stopband attenuation causing large fluctuations in the pass band, the compensation becomes flatter pass band, and the length of the FIR filter transition band decreases, the output of the quantization noise power is small in this way, and in this way brings increased power consumption nor Big.

[0026] 本发明的特征及优点将通过实施例结合附图进行详细说明。 [0026] The features and advantages of the invention will be described in detail by way of example in conjunction with the accompanying drawings. 附图说明 BRIEF DESCRIPTION

[0027] 图1是现有的数字抽取滤波器的结构示意图; [0027] FIG. 1 is a schematic structural diagram of a conventional digital decimation filter;

[0028] 图2是本发明的数字抽取滤波器的结构示意图; [0028] FIG. 2 is a structural diagram of a digital decimation filter of the present invention;

[0029] 图3是本发明的数字抽取滤波器的带级联的余弦预滤波器的CIC滤波器的结构示意图; [0029] FIG. 3 is a schematic diagram of the CIC filter prefilter cosine digital decimation filter of the present invention with a cascade;

[0030] 图4是本发明的数字抽取滤波器的余弦预滤波器的结构示意图; [0030] FIG. 4 is a schematic diagram of a digital cosine filter of the present invention, the pre-decimation filter;

[0031] 图5是CIC+HR 4 : 1方式和噪声的对数幅度谱; [0031] FIG. 5 is a CIC + HR 4: 1 mode and the number of noise amplitude spectrum;

[0032] 图6是CIC+HR 2 : 1方式和噪声的对数幅度谱; [0032] FIG. 6 is a CIC + HR 2: 1 logarithmic mode and noise amplitude spectrum;

[0033] 图7是CIC+CC0S+HR 2 : 1方式和噪声的对数幅度谱; [0033] FIG. 7 is a CIC + CC0S + HR 2: 1 logarithmic mode and noise amplitude spectrum;

[0034] 图8是CIC+CC0S2+HR 4 : 1方式和噪声的对数幅度谱; [0034] FIG. 8 is a CIC + CC0S2 + HR 4: 1 mode and the number of noise amplitude spectrum;

[0035] 图9是4阶CIC+CC0S1+HR 2 : 1的对数幅度响应的通带部分幅度谱; [0035] FIG. 9 is a fourth-order CIC + CC0S1 + HR 2: Part passband amplitude response of a log magnitude spectrum;

[0036] 图10是4阶CIC+CC0S2+HR 4 : 1的对数幅度响应的通带部分幅度谱; [0036] FIG. 10 is a fourth-order CIC + CC0S2 + HR 4: 1 log amplitude response passband amplitude spectrum portion;

[0037] 图11是4阶CIC+HR 4 : 1的对数幅度响应的通带部分幅度谱。 [0037] FIG. 11 is a fourth-order CIC + HR 4: Part passband amplitude response of a log magnitude spectrum.

具体实施方式 detailed description

[0038] 为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。 [0038] To make the objectives, technical solutions and advantages of the present invention will become more apparent hereinafter in conjunction with the accompanying drawings and embodiments of the present invention will be further described in detail.

[0039] 请参阅图2,为本发明的数字抽取滤波器的结构示意图。 [0039] Please refer to FIG. 2, a schematic structural diagram of a digital filter of the present invention is extracted. 本发明的数字抽取滤波器包括:带级联的余弦预滤波器的CIC滤波器、补偿滤波器和HR滤波器。 A digital decimation filter of the present invention comprises: a pre-filter with a cosine cascaded CIC filters, the compensation filters and HR filters. 带级联的余弦预滤波器的CIC滤波器、补偿滤波器和HR滤波器依次相连。 CIC filters, HR filters and the filter compensation pre-filter with a cosine sequentially connected in cascade. 本发明采用“频率采样法”生成补偿滤波器。 The present invention uses a "frequency sampling" generate a compensation filter. 补偿滤波器的频响为被补偿的滤波器的幅响的倒数,即G(f) =l/|H(f)|,最后通过“频率采样法”生成补偿滤波器。 Frequency response compensation filter to filter the compensated amplitude of the reciprocal ring, i.e. G (f) = l / | H (f) |, and finally the "sampling frequency" generate a compensation filter.

[0040] 请参阅图3和图4,本发明的数字抽取滤波器的带级联的余弦预滤波器的CIC滤波器包括CIC滤波器和带级联的余弦预滤波器。 [0040] Please refer to FIG. 3 and FIG. 4, the present invention is a digital decimation pre-filter with a cosine filter cascade of the CIC filter comprises a cosine filter and a pre-filter with cascaded CIC.

[0041] 级联余弦预滤波器(cascaded cosine pref ilter),其ζ变换形式为: [0041] cascade cosine prefilter (cascaded cosine pref ilter), which is the transform of ζ:

[0042] [0042]

Figure CN101442296BD00051

[0043] 其中 [0043] in which

Figure CN101442296BD00052

,相应的幅度响应为: , Corresponding amplitude response is:

[0044] I Hc。 [0044] I Hc. s, i (eJ") I = 1/2 | cos (Ni ω) +cos2 (Ni ω) | ⑵ s, i (eJ ") I = 1/2 | cos (Ni ω) + cos2 (Ni ω) | ⑵

[0045]叫阶的余弦预滤波器记为 [0045] called cosine order referred to as the pre-filter

Figure CN101442296BD00053

:则高阶的级联余弦预滤波器为: : The high-order pre-filter is a cosine cascade:

[0046] [0046]

Figure CN101442296BD00054

[0047] Ni表示了余弦预滤波器所放置的阶段,形式为: [0047] Ni represents the cosine phase of the pre-filter is placed in the form of:

[0048] Ni = R/2i+1 (4) [0048] Ni = R / 2i + 1 (4)

[0049] 其中R = R1R2. . . &,表示有M个阶段,每个阶段的抽取因子为氏。 [0049] wherein R = R1R2... &, Expressed the M phases, each decimation factor s. 本发明中对上述参数的选择有两种方案: In the present invention, there are two options for the choice of the above parameters:

[0050] (1)取M = 5,R1 = & = · · · = = 2,则R = 32,并取N1 = 8,N2 = 4,N3 = 2,N4 =1。 [0050] (1) taking M = 5, R1 = & = · · · = = 2, then R = 32, and taking N1 = 8, N2 = 4, N3 = 2, N4 = 1. 设Hcic (z) = 1/2 (1+广),则级联了余弦预滤波器的CIC滤波器的频响为:[0051] h(z) = h4cic (z)h'cic (z2)hicic (ζ4 (ζ8)h4c!c (ζ16 )hccos (ζ) ( 5 ) Provided Hcic (z) = 1/2 (1+ wide), the frequency response of the cascade of the CIC filter pre cosine filter is: [0051] h (z) = h4cic (z) h'cic (z2) hicic (ζ4 (ζ8) h4c! c (ζ16) hccos (ζ) (5)

[0052]其中孖CO^(Z) = H^os (z8)¾(Z4)H^os (z2)Hnc^os (ζ),这里取H1 = η2 [0052] wherein margin CO ^ (Z) = H ^ os (z8) ¾ (Z4) H ^ os (z2) Hnc ^ os (ζ), where H1 = η2 take

=η3 = η4 = 4ο = Η3 = η4 = 4ο

[0053] 这样的级联余弦预滤波器的CIC滤波器我们记为CIC+CC0S1。 [0053] Such a cascade of prefilter cosine CIC filter we write CIC + CC0S1.

[0054] (2)取M = 4,R1 = R2 = R3 = R4 = 2,则R = 16,并取N1 = 4,N2 = 2,N3 = 1。 [0054] (2) taking M = 4, R1 = R2 = R3 = R4 = 2, then R = 16, and taking N1 = 4, N2 = 2, N3 = 1.

[0055] SHac(Z) = 1/2 (1+ζ—1),则级联了余弦预滤波器的CIC滤波器的频响为: [0055] SHac (Z) = 1/2 (1 + ζ-1), the frequency response of the cascade of the CIC filter is a cosine prefilter:

[0056] H(z) = H4ac (z)H'clc (Z2)H4ac (Z4)H4ac (zs) Hccos (ζ) (6) [0056] H (z) = H4ac (z) H'clc (Z2) H4ac (Z4) H4ac (zs) Hccos (ζ) (6)

[0057]其中丑= Hn^os{zA)H^os{z2)H^os{z),这里取H1 = η2 = η3 = 4。 [0057] wherein ugly = Hn ^ os {zA) H ^ os {z2) H ^ os {z), where taking H1 = η2 = η3 = 4.

[0058] 这样的级联余弦预滤波器的CIC滤波器我们记为CIC+CC0S2。 [0058] Such a cascade of prefilter cosine CIC filter we write CIC + CC0S2.

[0059] 设H(fd))为整个抽取滤波器的频率响应,则抽取后的信号和噪声总的功率谱密度为: [0059] provided H (fd)) for the entire frequency response of the decimation filter, the noise signal and the decimated overall power spectral density:

[0060] Sz (fd) = IH (fd) 12Sx (fd) +1H (fd) I 2Sn (fd) (7) [0060] Sz (fd) = IH (fd) 12Sx (fd) + 1H (fd) I 2Sn (fd) (7)

[0061] 其中Sx(fd)是输入信号的功率谱密度,Sn(fd)是量化噪声的功率谱密度。 [0061] wherein Sx (fd) is the power spectral density of the input signal, Sn (fd) is the power spectral density of the quantization noise. 这里我们仅仅讨论量化噪声的功率谱密度。 Here we discuss only the quantization noise power spectral density. 对于P阶的Σ -Δ调制器,量化噪声的功率谱密度为: For P Σ -Δ order modulator, the quantization noise power spectral density is:

[0062] Sn(fd) = E(fd) · [2sin (Jifd)]p (8) [0062] Sn (fd) = E (fd) · [2sin (Jifd)] p (8)

[0063] 其中= 为在假设量化噪声为白噪声的采样噪声谱密度,fd归一化的频率,对应角频率为ω = 2 π fd,fd e [0,0. 5],Δ = (2Vr/2N-l)是N比特分辨率量化器的量化阶,21为量化器输入的动态范围。 [0063] where = quantization noise is assumed in the noise spectral density of white noise samples, normalized frequency FD corresponding angular frequency ω = 2 π fd, fd e [0,0. 5], Δ = (2Vr / 2N-l) is an N-bit resolution quantization step of the quantizer, the quantizer 21 is input dynamic range. 假设量化噪声的传递函数为(1-z—1)3,因此量化噪声的功率谱密度为: Suppose the quantization noise transfer function (1-z-1) 3, and therefore the quantization noise power spectral density is:

[0064] = (9) [0064] = (9)

[0065] 这相当于E(fd) = l,p = 6时的情形。 [0065] This is equivalent = l, 6 in the case E (fd) p =. 下面的进行性能的比较就是在此情形下的比较。 Compare is a comparison in this case following the performance.

[0066] 下面记输出端的噪声功率谱密度为: [0066] The noise power spectral density output of the following is referred to:

[0067] Sno (fd) = |H(fd) |2SN(fd) (10) [0067] Sno (fd) = | H (fd) | 2SN (fd) (10)

[0068] 输出端的噪声功率为(只计算在混叠带内的功率): Noise power [0068] is an output terminal (counting only the aliasing band power):

[0069] Pm = Σ O (Λ Wd (11) [0069] Pm = Σ O (Λ Wd (11)

[0070] 其中k=l,...,LR/2」,对于R为偶数。 [0070] where k = l, ..., LR / 2 "for R is an even number.

[0071] 假设总的抽取因子R = 64,归一化fs/2为π,则感兴趣频带在0〜π/R,内(KR),则混叠带为口^^/! [0071] Suppose the total decimation factor R = 64, normalized fs / 2 to π, the frequency band of interest in the mouth ^^ 0~π / R, the (KR), the aliasing band /! ? -^! - ^! /^^^/! / ^^^ /! ? +^! + ^! /! /! ^,其中!^=^…,LR/2」。 ^ Where! ^ = ^ ..., LR / 2. " 一般应用中L = R,因此混叠带在[0,π ]的整个区间。 General applications L = R, so aliasing band [0, π] of the whole interval. 因此抽取滤波器的0到π范围内都对输出端的噪声功率产生影响。 0 decimation filter thus have an impact on the noise power output of the π range.

[0072] 请参阅图5、图6、图7和图8,分别比较4阶CIC+HR 4 : 1方式,4阶CIC+HR 2 : 1方式,4阶CIC+CC0S1+HR 2 : 1方式,4阶CIC+CC0S2+FIR4 : 1方式的滤波器的对数幅度谱。 [0072] Referring to FIG. 5, 6, 7, and 8 were compared 4th order CIC + HR 4: 1 mode, fourth-order CIC + HR 2: 1 manner, fourth-order CIC + CC0S1 + HR 2: 1 manner , 4th order CIC + CC0S2 + FIR4: log magnitude spectrum of the filter of embodiment 1. 在图5、图6、图7和图8中,虚竖线为混叠带的起点,实竖线为混叠带的终点。 In FIG. 5, FIG. 6, FIG. 7 and FIG. 8, the starting point is a virtual vertical aliasing band, and the solid vertical line to the end of the aliasing band.

[0073] 请参阅图9,4阶CIC+CC0S1+HR 2 : 1方式的通带虽然有点补偿过头(补偿滤波器阶数增加会改善),但与4阶CIC+HR 4 : 1方式相比波动不大,而8阶或10阶CIC+HR4 : 1方式的通带波动很大。 [0073] Referring to FIG. 9,4-order CIC + CC0S1 + HR 2: 1 aspect passband although a little too far compensation (compensation filter order improves increase), but the fourth-order CIC + HR 4: 1 compared to the embodiment small fluctuations, the step 8 or step 10 CIC + HR4: passband aspect great. 请参阅图10,4阶CIC+CC0S2+HR 4 : 1方式的通带基本没有波动,因为使用的CIC滤波器要少。 See FIG 10,4 order CIC + CC0S2 + HR 4: 1 aspect passband substantially no fluctuation, since the CIC filter uses less. 这里所用到的补偿滤波器都是30阶的,16位增益的。 Compensation filter used here is of the order 30, 16 gain.

[0074] 下表为三种方式估计的噪声功率。 [0074] The following table shows the estimated noise power in three ways.

[0075] 表1 :三种方式的噪声功率比较 [0075] Table 1: Comparison of the noise power in three ways

[0076] [0076]

Figure CN101442296BD00071

[0077]可见 CIC+CC0S1+FIR 2 : 1 和CIC+CC0S2+FIR 4 : 1 方式的噪声功率较小。 [0077] visible CIC + CC0S1 + FIR 2: 1 and CIC + CC0S2 + FIR 4: 1 mode noise power is small.

[0078] 功耗估计为下式: [0078] The power estimation of the formula:

[0079] [0079]

Figure CN101442296BD00072

[0080] 其中NPi是在第i阶段中的部分积的数量,Wi是第i个阶段的输入字长,Mj为第i个阶段的抽取因子,1为抽取阶段总数。 [0080] where NPi is the number of partial products in the first stage i, Wi is the input word length of the i-th stage, Mj of the i-th stage of the decimation factor, the total number of stage 1 decimation. 这里说的部分积是指与2的幂次的乘积,当与2 的幂次相乘,在硬件实现时就可转化为整数左移。 Here that portion of the product is the product of a power of 2, when multiplied by the power of 2, can be implemented in hardware into the left integer. 例如当N = 5时,HR滤波器传递函数为(1+z-1)5= Ι+δζ-^ΙΟζί+ΙΟζ^+δζ^ζ-5,对应的滤波器的冲激响应为[1 5 10 10 5 1],对应的2进制表示为WOOl 0101 1010 1010 0101 0001],因此共有10次与2的幂次的乘积,即有10次的整数左移,对应NPi = 10。 For example, when N = 5, HR filter transfer function (1 + z-1) 5 = Ι + δζ- ^ ΙΟζί + ΙΟζ ^ + δζ ^ ζ-5, the corresponding filter impulse response [15 101051], expressed as the corresponding binary WOOl 0101 1010 1010 0101 0001], so a total of 10 times the product of the power of 2, i.e. 10 times left integers corresponding NPi = 10. 因为每一次左移就对应一次加法,因此部分积的个数实际代表了左移和加法的个数,它很好的表示了硬件实现时的复杂度。 Because each corresponding to an addition to the left, so the actual product part number represents the number of left shift and addition, it is well expressed when the complexity of hardware implementation. 除以Π ρ/M^是因为第i阶段总的抽取数代表了速率下降的倍数,而且默认速率下降一倍所进行的运算的功耗就下降一倍这个事实。 Dividing Π ρ / M ^ is because the total number of the first extraction stage i represents a multiple rate reduction, power consumption decrease and a default rate doubling operation performed on the fact that lowered twice.

[0081]下面比较 CIC+FIR 4 : LCIC+FIR 2 : 1,CIC+CC0S1+FIR 2 : 1 和CIC+CC0S2+FIR 4 : 1四种方式的功耗。 [0081] The following Comparative CIC + FIR 4: LCIC + FIR 2: 1, CIC + CC0S1 + FIR 2: 1 power in four ways: 1 and CIC + CC0S2 + FIR 4.

[0082] 4阶的CIC滤波器的部分积数量为6,字长为4,补偿4个4阶的CIC滤波器的补偿滤波器的部分积数量为179,字长为16,HR 4 : 1滤波器的部分积数量为四45,字长为M。 Product part number [0082] order CIC filter 4 to 6, the word length is 4, the number of product portions compensation filter is compensated 4 4 order CIC filter 179, word length is 16, HR 4: 1 part number is four product filter 45, word size M. 补偿5个4阶的CIC滤波器的补偿滤波器的部分积数量为172,字长为16,HR 2 : 1滤波器的部分积数量为1383,字长为22。4阶的余弦预滤波器的部分积数量为48,字长为3,补偿5个4阶的CIC滤波器加4个4阶余弦预滤波器的补偿滤波器的部分积数量为159,字长为16。 Product number compensation section 5 4 order CIC filter compensation filter 172, word length is 16, HR 2: Product Number 1 filter section 1383, the word length of the order of 22.4 cosine prefilter scalar product portion 48, word size of 3, 5 4 compensating order CIC filter scalar product portion 4 plus 4 prefilter order cosine compensation filter 159, word length is 16. 补偿4个4阶的CIC滤波器加3个4阶余弦预滤波器的补偿滤波器的部分积数量为110,字长为16。 4 Number of partial compensation plot order CIC filter 4 plus 3 4 prefilter order cosine compensation filter 110, word length is 16. 第i个阶段的输入字长为Wi = WH+WH,其中WfH为第i-1个阶段的滤波器字长,Wtl = Lfff0 = 0。 The i-th input word lengths stage is Wi = WH + WH, wherein the filter is the wordlength WfH i-1 th stages, Wtl = Lfff0 = 0. 第i个阶段的抽取因子Mi由下采样倍数很容易得出,假设对FIR滤波器的实现都以多相位形式实现,因此采用先抽取再滤波的结构,抽取因子的位置应适当前移。 The i-th stage of the decimation factor is given by Mi readily sampling times, assuming FIR filter are realized in the form of a multi-phase, thus re-using the first decimation filter structure, the decimation factor should be appropriate forward position. 根据上述数据,可以计算出四种方式的功耗,列为下表: According to the above data, the power consumption can be calculated in four ways, as the following table:

[0083] 表2:功耗 [0083] Table 2: Power

[0084] [0084]

Figure CN101442296BD00081

[0085] CIC+FIR 2 : 1方式的功耗最小,但噪声功率较大。 [0085] CIC + FIR 2: 1 aspect of the minimum power, but the noise power is large. CIC+CC0S1+HR 2 : 1方式的功耗小于CIC+HR 4 : 1方式,但其噪声功率要比CIC+HR 4 : 1方式的小得多。 CIC + CC0S1 + HR 2: 1 power consumption mode is smaller than the CIC + HR 4: 1 manner, but the noise power than CIC + HR 4: 1 mode is much smaller. CIC+CC0S2+FIR 4 : 1的功耗最大,但噪声功率CIC+CC0S1+HR2 : 1方式的相当,而且这种方式的通带最平坦。 CIC + CC0S2 + FIR 4: 1 maximum power, but the noise power CIC + CC0S1 + HR2: 1 equivalent manner, and the pass band of the flattest in this manner.

[0086] 以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。 [0086] The foregoing is only preferred embodiments of the present invention but are not intended to limit the present invention, any modifications within the spirit and principle of the present invention, equivalent substitutions and improvements should be included in the present within the scope of the invention.

Claims (6)

  1. 1. 一种数字抽取滤波器,包括带级联的余弦预滤波器的Cic滤波器,其特征在于:还包括补偿滤波器和HR滤波器,所述带级联的余弦预滤波器的Cic滤波器、补偿滤波器和HR 滤波器依次相连,所述补偿滤波器通过“频率采样法”生成,且所述补偿滤波器的频响为被补偿的滤波器的幅响的倒数。 A digital decimation filter, comprising Cic cosine filter cascaded with a prefilter, characterized in that: further comprising compensation filters and HR filters, the cosine filter with a prefilter Cic cascaded , a compensation filter, and HR filters are connected in sequence by said compensation filter "frequency sampling method" generation, and the compensation filter frequency response compensated amplitude response filter reciprocal.
  2. 2.如权利要求1所述的数字抽取滤波器,其特征在于,所述补偿滤波器是30阶、16位增益的补偿滤波器。 1 2. The number of the decimation filter as claimed in claim, wherein said filter is a 30-order compensation, gain compensation filter 16.
  3. 3.如权利要求1所述的数字抽取滤波器,其特征在于,所述数字抽取滤波器的带级联的余弦预滤波器的CIC滤波器包括CIC滤波器和带级联的余弦预滤波器。 3. The digital decimation filter of claim 1, wherein the digital decimation filter with pre-cosine filter cascaded CIC filter comprises a prefilter cosine filter and a band cascaded CIC .
  4. 4.如权利要求3所述的数字抽取滤波器,其特征在于,所述级联余弦预滤波器ζ变换形式为:F·⑵=, /=1其中Zfcos,,.(ζ) = 1/4(ζ"|. +Z~N') + 1/Kz2N' +Z-2wO+ 1/4 ο The digital decimation filter according to claim 3, characterized in that said cascade [zeta] cosine transform of the pre-filter is: F · ⑵ =, / = 1 where Zfcos ,, (ζ) = 1 /. 4 (ζ "|. + Z ~ N ') + 1 / Kz2N' + Z-2wO + 1/4 ο
  5. 5.权利要求3所述的数字抽取滤波器,其特征在于,所述级联余弦预滤波器ζ变换形式为:H(z) = H'CIC (Z)H4cic (ζ2 )H'C1C (ζ4 )H4cic (ζ8 )H4cic (ζ16 )Hccos (ζ)其中Hcic(Z) = 1/2 (1+ζ-1),Hccos (ζ) = H^os(ζ8)H 1^2os(ζ4)Hgos(ζ2)H^aos(ζ) , = ^2 = = ^4 = 4 'Hcos (ζ) = 1/4 (ζ+ζ_1) +1/8 (ζ2+ζ-2) +1/40 Said digital decimation filter of claim 3, wherein said ζ cascade cosine transform of the pre-filter is: H (z) = H'CIC (Z) H4cic (ζ2) H'C1C (ζ4 ) H4cic (ζ8) H4cic (ζ16) Hccos (ζ) where Hcic (Z) = 1/2 (1 + ζ-1), Hccos (ζ) = H ^ os (ζ8) H 1 ^ 2os (ζ4) Hgos ( ζ2) H ^ aos (ζ), = ^ 2 = = ^ 4 = 4 'Hcos (ζ) = 1/4 (ζ + ζ_1) +1/8 (ζ2 + ζ2) +1/40
  6. 6.权利要求3所述的数字抽取滤波器,其特征在于,所述级联余弦预滤波器ζ变换形式为:H(z) = H4cic (Z)H4cic (ζ2 )Hacic (ζ4 )H'CIC (ζ8 )Hccos (ζ)其中Hcic(Z) = 1/2 ( 1 + Z - 1 ),Hccos(z) = H^os(z4)^cos(z2)^cos(z) ' nx=n2=n3=4,Hcos (ζ) = 1/4 (z+z_1) +1/8 (z2+z-2) +l/4o Said digital decimation filter of claim 3, wherein said ζ cascade cosine transform of the pre-filter is: H (z) = H4cic (Z) H4cic (ζ2) Hacic (ζ4) H'CIC (ζ8) Hccos (ζ) where Hcic (Z) = 1/2 (1 + Z - 1), Hccos (z) = H ^ os (z4) ^ cos (z2) ^ cos (z) 'nx = n2 = n3 = 4, Hcos (ζ) = 1/4 (z + z_1) +1/8 (z2 + z2) + l / 4o
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