CN101752382A

CN101752382A - One-time programmable memory and manufacture and programming reading method

Info

Publication number: CN101752382A
Application number: CN200810239925A
Authority: CN
Inventors: 朱一明; 苏如伟
Original assignee: Beijing Xinji Jiayi Microelectronic Science & Tech Co Ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2008-12-15
Filing date: 2008-12-15
Publication date: 2010-06-23
Anticipated expiration: 2028-12-15
Also published as: CN101752382B

Abstract

The invention discloses a one-time programmable memory and a manufacture and programming reading method of a semitransistor structure. A semitransistor comprises a programmable capacitor formed by a polysilicon layer, a gate oxide layer, a lightly doped drain zone and an ion implantation zone, and a diode formed by the ion implantation zone and a heavily doped zone, wherein the programmable capacitor is connected with the diode in series, and the polysilicon layer is connected with a word line; and the heavily doped zone is connected with a bit line. By utilizing the characteristics that the programmable capacitor form an on resistance when being broken down and is still taken as an insulation capacitor when not being broken down, and the forward conducting and reverse-closing characteristic of the diode, the one-time programmable memory which has small memory cell area and high integration level, can further improve integration level with the development of process, is based on the existing logical process without adding a special process, and has high stability and reliability of data storage can be achieved.

Description

Disposable programmable memory, manufacturing and programming read method

Technical field

The present invention relates generally to the semiconductor memory field, relates in particular to disposable programmable memory, manufacturing and programming read method.

Background technology

At present, DRAM structure is mainly adopted in the design of the disposable programmable memory of logic-based technology, but utilizes the breakdown characteristics of transistorized grid oxide layer to carry out data programing.Each unit of this disposable programmable memory all comprises two transistors, and one of them transistor is the thick grid oxide layer transistor that is used for input and output, because its grid oxide layer is thicker, therefore has higher withstand voltage properties; Another transistor is the thin grid oxide layer transistor that is used for the chip internal circuit, because its grid oxide layer is thinner, therefore is easy under lower voltage breakdown.Because thick grid oxide layer transistor possesses the gating characteristic, thin grid oxide layer transistor possesses can puncture capacitance characteristic, and therefore, the sort circuit structure is also referred to as and comprises a gate transistor and the circuit structure that can puncture electric capacity (1T1C).The disposable programmable memory of this structure, because program voltage is higher, need gate tube to have higher withstand voltage properties, but because the transistorized area of thick grid oxide layer is relatively large, make that the area of each memory cell is also bigger, therefore, cause the increase of manufacturing cost and the reduction of integrated level.

Summary of the invention

In view of this, the object of the present invention is to provide a kind of disposable programmable memory, manufacturing and programming read method, reaching provides that to have a memory cell area little, the integrated level height, can further improve integrated level with the development of technology, based on existing logic process, the disposable programmable memory that need not to increase special process, has high storage stability and reliability.

According to the one side of the embodiment of the invention, a kind of disposable programmable memory of half crastal tube structure is provided, described semitransistor comprises:

The programmable capacitor that forms by polysilicon layer, grid oxide layer, lightly doped drain, ion implanted region;

The diode that forms by ion implanted region and heavily doped region;

Described programmable capacitor and described diode are connected in series; Wherein,

Described polysilicon layer is connected with word line, and described heavily doped region is connected with bit line.

According to a feature of the embodiment of the invention, described semitransistor comprises:

Isolated groove is used for described ion implanted region is isolated; Wherein, the degree of depth of described isolated groove is greater than the degree of depth of described ion implanted region.

According to another feature of the embodiment of the invention, the doping content of described ion implanted region is less than the doping content of described heavily doped region.

According to another feature of the embodiment of the invention, described ion implanted region comprises n type or p type ion implanted region.

According to another feature of the embodiment of the invention, described heavily doped region comprises n type or p type heavily doped region.

According to another feature of the embodiment of the invention, described lightly doped drain is opposite with the doping type of described heavily doped region.

According to the embodiment of the invention on the other hand, provide a kind of manufacture method of disposable programmable memory of half crastal tube structure, may further comprise the steps:

Generate shallow isolated groove;

On substrate, form trap;

In trap, form ion implanted region;

On ion implanted region, generate grid oxide layer;

On grid oxide layer, generate polysilicon layer;

In ion implanted region, form lightly doped drain;

Both sides at grid oxide layer and polysilicon layer form side wall;

In ion implanted region, form heavily doped region;

Polysilicon layer, thin grid oxide layer, lightly doped drain, ion implanted region form programmable capacitor;

The diode that ion implanted region and heavily doped region form;

Programmable capacitor and diode are connected in series.

Generate isolated groove;

On substrate, form trap;

On ion implanted region, generate grid oxide layer;

On grid oxide layer, generate polysilicon layer;

In trap, form lightly doped drain;

Both sides at grid oxide layer and polysilicon layer form side wall;

In trap, form heavily doped region;

In trap, form ion implanted region;

Lightly doped drain is positioned at outside the ion implanted region, and heavily doped region is positioned within the ion implanted region;

Wherein, polysilicon layer, thin grid oxide layer, ion implanted region form programmable capacitor;

Ion implanted region and heavily doped region form diode;

Programmable capacitor and diode are connected in series.

According to a feature of the embodiment of the invention,

Described isolated groove is used for described ion implanted region is isolated; Wherein, the degree of depth of described isolated groove is greater than the degree of depth of described ion implanted region.

According to another feature of the embodiment of the invention, described trap comprises n type or p type trap.

According to the embodiment of the invention on the other hand, provide a kind of programmed method of disposable programmable memory of half crastal tube structure, described semitransistor comprises:

The diode that forms by ion implanted region and heavily doped region;

Described polysilicon layer is connected with word line, and described heavily doped region is connected with bit line;

Described programmed method comprises:

On word line, apply first voltage, on bit line, apply second voltage, programmable capacitor is punctured the formation conducting resistance, and make diode current flow.

According to a feature of the embodiment of the invention,

The difference of described first voltage and described second voltage is the magnitude of voltage that described programmable capacitor can be punctured.

According to the embodiment of the invention on the other hand, provide a kind of read method of disposable programmable memory of half crastal tube structure, described semitransistor comprises:

The diode that forms by ion implanted region and heavily doped region;

Described read method comprises:

Whether apply tertiary voltage on word line, apply the 4th voltage on bit line, detecting sense amplifier has electric current, if, then represent the breakdown formation resistance of programmable capacitor, diode current flow is output as logical one; Otherwise the expression programmable capacitor is not breakdown, output logic " 0 ".

Disposable programmable memory of the present invention, manufacturing and programming read method, the beneficial effect that reaches is as follows:

1. owing to adopt half crastal tube structure, therefore, this one-time programmable memory cell only takies transistorized area half, thereby has reduced memory cell area, has improved integrated level;

2. because based on existing logic process manufacturing, so this one-time programmable memory cell can make integrated level further raising with the development of technology of this disposable programmable memory with technology characteristics size scaled down;

3. owing to need not to increase special process so this one-time programmable memory cell can be directly embedded in the SOC chip;

4. the programmable capacitor breakdown area concentrates on lightly doped drain during owing to programming, therefore guarantees that transistorized heavily doped region is not influenced by puncture voltage, thereby has improved the reliability of one-off programming memory.

Description of drawings

Fig. 1 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the first embodiment of the invention;

Fig. 2 is the partial top view of the One Time Programmable storage array of n type half crastal tube structure in the first embodiment of the invention;

Fig. 3 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the second embodiment of the invention;

Fig. 4 is the partial top view of the One Time Programmable storage array of p type half crastal tube structure in the second embodiment of the invention;

Fig. 5 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the third embodiment of the invention;

Fig. 6 is the partial top view of the One Time Programmable storage array of n type half crastal tube structure in the third embodiment of the invention;

Fig. 7 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the fourth embodiment of the invention;

Fig. 8 is the partial top view of the One Time Programmable storage array of p type half crastal tube structure in the fourth embodiment of the invention;

Fig. 9 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the fifth embodiment of the invention;

Figure 10 is the partial top view of the One Time Programmable storage array of n type half crastal tube structure in the fifth embodiment of the invention;

Figure 11 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the sixth embodiment of the invention;

Figure 12 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the seventh embodiment of the invention;

Figure 13 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the eighth embodiment of the invention;

Figure 14 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the ninth embodiment of the invention;

Figure 15 A is the equivalent circuit theory figure of the one-time programmable memory cell of n type half crastal tube structure among the present invention first and third, five, six, eight embodiment;

Figure 15 B is the equivalent circuit theory figure after the one-time programmable memory cell programming of n type half crastal tube structure among the present invention first and third, five, six, eight embodiment punctures;

Figure 16 is the partial schematic diagram of the One Time Programmable storage array of n type half crastal tube structure among the present invention first and third, five, six, eight embodiment;

Figure 17 A is the circuit theory diagrams of the one-time programmable memory cell of p type half crastal tube structure among the present invention second, four, seven, nine embodiment;

Figure 17 B is the equivalent circuit theory figure after the one-time programmable memory cell programming of p type half crastal tube structure among the present invention second, four, seven, nine embodiment punctures;

Figure 18 is the partial schematic diagram of the One Time Programmable storage array of p type half crastal tube structure among the present invention second, four, seven, nine embodiment.

Embodiment

Describe specific embodiments of the invention in detail below in conjunction with accompanying drawing.

Embodiment one

Fig. 1 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the first embodiment of the invention, comprises among Fig. 1: polysilicon layer 101, thin grid oxide layer 102, p type ion implanted region 103, n type heavily doped region 104, shallow isolated groove 105, n type trap 106 and p type substrate 107.Polysilicon layer is connected to thin grid oxide layer 102 for 101 times, thin grid oxide layer is connected to p type ion implanted region 103 for 102 times, and p type ion implanted region 103 is positioned at n type trap 106, and heavily doped region 104 is arranged in p type ion implanted region 103; Polysilicon layer 101 is connected with word line (WL, Word Line), and n type heavily doped region 104 is connected with bit line (BL, Bit Line).Thin grid oxide layer 102 is connected with p type ion implanted region 103.Keep preset distance between thin grid oxide layer 102 and the n type heavily doped region 104.

Wherein, polysilicon layer 101, thin grid oxide layer 102, p type ion implanted region 103 form programmable capacitor, and p type ion implanted region 103 forms diode with n type heavily doped region 104.Shallow isolated groove 105 is used for p type ion implanted region 103 is isolated, and wherein, the degree of depth of shallow isolated groove 105 is greater than the degree of depth of p type ion implanted region 103.But the doping content of p type ion implanted region 103 is greater than the doping content of n type trap 106 less than the doping content of n type heavily doped region 104.

Introduce the manufacture method of the one-time programmable memory cell of n type half crastal tube structure in the first embodiment of the invention below, concrete steps are as follows:

Step 101S generates shallow isolated groove according to mask pattern;

Step 102S forms the n trap on p type substrate;

Step 103S forms p type ion implanted region in the n trap;

Step 104S generates grid oxide layer on p type ion implanted region;

Step 105S generates polysilicon layer on grid oxide layer;

Step 106S carries out heavy dose of n type ion and injects formation n type heavily doped region in p type ion implanted region.

In the above-mentioned steps, polysilicon layer, grid oxide layer, p type ion implanted region form programmable capacitor, and p type ion implanted region and n type heavily doped region form diode.The degree of depth of shallow isolated groove is less than the degree of depth of n trap but greater than the degree of depth of p type ion implanted region, thereby guarantee that shallow isolated groove can isolate p type ion implanted region well, make that the spacing between each one-time programmable memory cell is very little, thereby reduce the area that the One Time Programmable storage array takies.

Fig. 2 is the partial top view of the One Time Programmable storage array of n type half crastal tube structure in the first embodiment of the invention, among Fig. 2, each one-time programmable memory cell comprises polysilicon layer 201, metal level 202, contact hole 203, n type heavily doped region 204 and p type ion implanted region 205.Wherein, polysilicon layer 201 is connected with word line WL1, and the metal level 202 that is connected with bit line BL1 is connected with n type heavily doped region 204 through contact hole 203.

Table 1 is the programming and the read method of the one-time programmable memory cell of n type half crastal tube structure in the first embodiment of the invention:

		??V _WL	??V _BL	Whether programme
		??V _WL	??V _BL	Whether programme	Programming	Select WL/ to select BL	??V _pp	??0V	Be
	Select WL/ not select BL	??V _pp	??V _ppOr high resistant	Not	Programming	Select WL/ to select BL	??V _pp	??0V	Be
	Select WL/ not select BL	??V _pp	??V _ppOr high resistant	Not		Do not select WL/ to select BL	??0V	??0V	Not
	Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not		Do not select WL/ to select BL	??0V	??0V	Not
	Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not					Whether detect the sense amplifier electric current
Read	Select WL/ to select BL	??V _read	??0V	Be					Whether detect the sense amplifier electric current

	??V _WL	??V _BL	Whether programme
	??V _WL	??V _BL	Whether programme	Select WL/ not select BL	??V _read	??V _dd	Not
Do not select WL/ to select BL	??0V	??0V	Not	Select WL/ not select BL	??V _read	??V _dd	Not
Do not select WL/ to select BL	??0V	??0V	Not	Do not select WL/ not select BL	??0V	??V _dd	Not

Table 1

In the table 1, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

On word line WL, apply puncture voltage V _PpOn bit line BL, apply 0V voltage, promptly on n type heavily doped region, apply 0V voltage, thereby the programmable capacitor that polysilicon layer, thin grid oxide layer, p type ion implanted region are formed punctures, and the diode forward conducting that p type ion implanted region and n type heavily doped region are formed.Under the logic process of 0.13um, puncture voltage V _PpSelectable magnitude of voltage such as 6.5V, operating voltage V _DdSelectable magnitude of voltage such as 1.3V read voltage V _ReadSelectable magnitude of voltage such as 0.8-1.3V.

Read process:

With word line WL on apply and read voltage V _ReadOn bit line BL, apply 0V voltage, promptly on n type heavily doped region, apply 0V voltage, detect sense amplifier whether electric current is arranged, if, then represent the breakdown formation resistance of programmable capacitor that polysilicon layer, thin grid oxide layer, p type ion implanted region form, the diode forward conducting that p type ion implanted region and n type heavily doped region form then is output as logical one; Otherwise the programmable capacitor that expression polysilicon layer, thin grid oxide layer, p type ion implanted region form is not breakdown, output logic " 0 ".

Embodiment two

Fig. 3 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the second embodiment of the invention, comprises among Fig. 3: polysilicon layer 301, thin grid oxide layer 302, n type ion implanted region 303, p type heavily doped region 304, shallow isolated groove 305, p type trap 306 and p type substrate 307.Polysilicon layer is connected to thin grid oxide layer 302 for 301 times, thin grid oxide layer is connected to n type ion implanted region 303 for 302 times, and n type ion implanted region 303 is positioned at p type trap 306, and p type heavily doped region 304 is arranged in n type ion implanted region 303.Polysilicon layer 301 is connected with word line WL, and p type heavily doped region 304 is connected with bit line BL.Thin grid oxide layer 302 is connected with n type ion implanted region 303.Keep preset distance between thin grid oxide layer 302 and the p type heavily doped region 304.

Wherein, polysilicon layer 301, thin grid oxide layer 302, n type ion implanted region 303 form programmable capacitor, and n type ion implanted region 303 forms diode with p type heavily doped region 304.Shallow isolated groove 305 is used for n type ion implanted region 303 is isolated, and wherein, the degree of depth of shallow isolated groove 305 is greater than the degree of depth of n type ion implanted region 303.But the doping content of n type ion implanted region 303 is greater than the doping content of p type trap 306 less than the doping content of p type heavily doped region 304.

Introduce the manufacture method of the one-time programmable memory cell of p type half crastal tube structure in the second embodiment of the invention below, concrete steps are as follows:

Step 201S generates shallow isolated groove according to mask pattern;

Step 202S forms the p trap on p type substrate;

Step 203S forms n type ion implanted region in the p trap;

Step 204S generates grid oxide layer on n type ion implanted region;

Step 205S generates polysilicon layer on grid oxide layer;

Step 206S carries out heavy dose of p type ion and injects formation p type heavily doped region in n type ion implanted region.

In the above-mentioned steps, polysilicon layer, grid oxide layer, n type ion implanted region form programmable capacitor, and n type ion implanted region and p type heavily doped region form diode.The degree of depth of shallow isolated groove is less than the degree of depth of p trap but greater than the degree of depth of n type ion implanted region, thereby guarantee that shallow isolated groove can isolate n type ion implanted region well, make that the spacing between each one-time programmable memory cell is very little, thereby reduce the area that the One Time Programmable storage array takies.

Fig. 4 is the partial top view of the One Time Programmable storage array of p type half crastal tube structure in the second embodiment of the invention, among Fig. 4, each one-time programmable memory cell comprises polysilicon layer 401, metal level 402, contact hole 403, p type heavily doped region 404 and n type ion implanted region 405.Wherein, polysilicon layer 401 is connected with word line WL1, and the metal level 402 that is connected with bit line BL1 is connected with p type heavily doped region 404 through contact hole 403.

Table 2 is the programming and the read method of the one-time programmable memory cell of p type half crastal tube structure in the second embodiment of the invention:

		??V _WL	??V _BL	Whether programme
		??V _WL	??V _BL	Whether programme	Programming	Select WL/ to select BL	??0V	??V _pp	Be
	Select WL/ not select BL	??0V	??0V	Not	Programming	Select WL/ to select BL	??0V	??V _pp	Be
	Select WL/ not select BL	??0V	??0V	Not		Do not select WL/ to select BL	??V _ppOr high resistant	??V _pp	Not
	Do not select WL/ not select BL	??V _ppOr high resistant	??0V	Not		Do not select WL/ to select BL	??V _ppOr high resistant	??V _pp	Not
	Do not select WL/ not select BL	??V _ppOr high resistant	??0V	Not					Whether detect the sense amplifier electric current
Read	Select WL/ to select BL	??0V	??V _read	Be					Whether detect the sense amplifier electric current
Read	Select WL/ to select BL	??0V	??V _read	Be		Select WL/ not select BL	??0V	??0V	Not
	Do not select WL/ to select BL	??V _dd	??V _read	Not		Select WL/ not select BL	??0V	??0V	Not
	Do not select WL/ to select BL	??V _dd	??V _read	Not		Do not select WL/ not select BL	??V _dd	??0V	Not

Table 2

In the table 2, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

With word line WL on apply 0V voltage, on bit line BL, apply puncture voltage V _Pp, promptly on p type heavily doped region, apply puncture voltage V _PpThereby the programmable capacitor that polysilicon layer, thin grid oxide layer, n type ion implanted region are formed punctures, and the diode forward conducting that p type heavily doped region and n type ion implanted region are formed.

Read process:

Apply voltage 0V voltage at word line WL, on bit line BL, apply and read voltage V _Read, promptly on p type heavily doped region, apply and read voltage V _ReadWhether have electric current, if then represent the breakdown formation resistance of programmable capacitor that polysilicon layer, thin grid oxide layer, n type ion implanted region form if detecting sense amplifier, the diode forward conducting that p type heavily doped region and n type ion implanted region form then is output as logical one; Otherwise the programmable capacitor that expression polysilicon layer, thin grid oxide layer, n type ion implanted region form is not breakdown, output logic " 0 ".

Embodiment three

Fig. 5 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the third embodiment of the invention, comprises among Fig. 5: polysilicon layer 501, thin grid oxide layer 502, p type lightly doped drain 503, n type heavily doped region 504, p type ion implanted region 505, shallow isolated groove 506, n type trap 507 and p type substrate 508.Polysilicon layer is connected to thin grid oxide layer 502 for 501 times, thin grid oxide layer 502 is adjacent to p type lightly doped drain 503, and p type lightly doped drain 503, n type heavily doped region 504 are arranged in p type ion implanted region 505, and p type ion implanted region 505 is arranged in n type trap 507.(WL's polysilicon layer 501 WordLine) is connected, and n type heavily doped region 504 is connected with bit line (BL, Bit Line) with word line.Thin grid oxide layer 502 is connected with p type ion implanted region 505.

Wherein, polysilicon layer 501, thin grid oxide layer 502, p type lightly doped drain 503, p type ion implanted region 505 form programmable capacitor, and p type ion implanted region 505 forms diode with n type heavily doped region 504.Shallow isolated groove 505 is used for p type ion implanted region 505 is isolated, and wherein, the degree of depth of shallow isolated groove 505 is greater than the degree of depth of p type ion implanted region 505.But the doping content of p type ion implanted region 505 is greater than the doping content of n type trap 507 less than the doping content of n type heavily doped region 504.

Introduce the manufacture method of the one-time programmable memory cell of n type half crastal tube structure in the third embodiment of the invention below, concrete steps are as follows:

Step 301S generates shallow isolated groove according to mask pattern;

Step 302S forms the n trap on p type substrate;

Step 303S forms p type ion implanted region in the n trap;

Step 304S generates grid oxide layer on p type ion implanted region;

Step 305S generates polysilicon layer on grid oxide layer;

Step 306S carries out low dose of p type ion at p type ion implanted region and injects formation p type lightly doped drain;

Step 307S forms side wall (sidewall) in the both sides of grid oxide layer and polysilicon layer;

Step 308S carries out heavy dose of n type ion and injects formation n type heavily doped region in p type ion implanted region, owing to stopping of side wall, the regional reserve part p type lightly doped drain that ion implanted region is contacted with side wall forms p type lightly doped drain.

In the above-mentioned steps, polysilicon layer, grid oxide layer, p type lightly doped drain, p type ion implanted region form programmable capacitor, and p type ion implanted region and n type heavily doped region form diode.The degree of depth of shallow isolated groove is less than the degree of depth of n trap but greater than the degree of depth of p type ion implanted region, thereby guarantee that shallow isolated groove can isolate p type ion implanted region well, make that the spacing between each one-time programmable memory cell is very little, thereby reduce the area that the One Time Programmable storage array takies.

Fig. 6 is the partial top view of the One Time Programmable storage array of n type half crastal tube structure in the third embodiment of the invention, among Fig. 6, each one-time programmable memory cell comprises polysilicon layer 601, metal level 602, contact hole 603, n type heavily doped region 604, p type lightly doped drain 605 and p type ion implanted region 606.Wherein, polysilicon layer 601 is connected with word line WL1, and the metal level 602 that is connected with bit line BL1 is connected with n type heavily doped region 604 through contact hole 603.The p type ion implanted region 606 that frame of broken lines is represented, its part is covered by polysilicon layer 601.

Table 3 is the programming and the read method of the one-time programmable memory cell of n type half crastal tube structure in the third embodiment of the invention:

		??V _WL	??V _BL	Whether programme
		??V _WL	??V _BL	Whether programme	Programming	Select WL/ to select BL	??V _pp	??0V	Be
	Select WL/ not select BL	??V _pp	??V _ppOr high resistant	Not	Programming	Select WL/ to select BL	??V _pp	??0V	Be
	Select WL/ not select BL	??V _pp	??V _ppOr high resistant	Not		Do not select WL/ to select BL	??0V	??0V	Not
	Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not		Do not select WL/ to select BL	??0V	??0V	Not
	Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not					Whether detect the sense amplifier electric current
Read	Select WL/ to select BL	??V _read	??0V	Be					Whether detect the sense amplifier electric current
Read	Select WL/ to select BL	??V _read	??0V	Be		Select WL/ not select BL	??V _read	??V _dd	Not
	Do not select WL/ to select BL	??0V	??0V	Not		Select WL/ not select BL	??V _read	??V _dd	Not
	Do not select WL/ to select BL	??0V	??0V	Not		Do not select WL/ not select BL	??0V	??V _dd	Not

Table 3

In the table 3, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

With word line WL on apply voltage V _Pp, apply 0V voltage at bit line BL, promptly on n type heavily doped region, apply 0V voltage.At this moment, the diode structure that p type ion implanted region and n type heavily doped region form makes p type ion implanted region be clamped at diode cut-in voltage V _ThIn addition, the part that is connected with thin grid oxide layer in p type ion implanted region forms n type inversion layer, and the electromotive force of this n type inversion layer can be because word line WL goes up voltage V _PpEffect and by corresponding raising, therefore, electrical potential difference between p type lightly doped drain and the thin grid oxide layer will be greater than the electrical potential difference between p type ion implanted region and the thin grid oxide layer, therefore, the programmable capacitor that polysilicon layer, thin grid oxide layer, p type lightly doped drain, p type ion implanted region form will be breakdown in the coupling part of p type lightly doped drain and thin grid oxide layer, the diode forward conducting that p type ion implanted region and n type heavily doped region form.

Read process:

On word line WL, apply voltage V _ReadOn bit line BL, apply 0V voltage, promptly on n type heavily doped region, apply 0V voltage, detect sense amplifier whether electric current is arranged, if, then represent the breakdown formation resistance of programmable capacitor that polysilicon layer, thin grid oxide layer, p type lightly doped drain, p type ion implanted region form, the diode forward conducting that p type ion implanted region and n type heavily doped region form then is output as logical one; Otherwise the programmable capacitor that expression polysilicon layer, thin grid oxide layer, p type lightly doped drain, p type ion implanted region form is not breakdown, output logic " 0 ".

Embodiment four

Fig. 7 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the fourth embodiment of the invention, comprises among Fig. 7: polysilicon layer 701, thin grid oxide layer 702, n type lightly doped drain 703, p type heavily doped region 704, n type ion implanted region 705, shallow isolated groove 706, p type trap 707 and p type substrate 708.Polysilicon layer is connected to thin grid oxide layer 702 for 701 times, thin grid oxide layer 702 is adjacent to n type lightly doped drain 703, and n type lightly doped drain 703, p type heavily doped region 704 are arranged in n type ion implanted region 705, and n type ion implanted region 705 is arranged in p type trap 707.Polysilicon layer 701 is connected with word line WL, and p type heavily doped region 704 is connected with bit line BL.Thin grid oxide layer 702 is connected with n type ion implanted region 705.

Wherein, polysilicon layer 701, thin grid oxide layer 702, n type lightly doped drain 703, n type ion implanted region 705 form programmable capacitor, and n type ion implanted region 705 forms diode with p type heavily doped region 704.Shallow isolated groove 705 is used for n type ion implanted region 705 is isolated, and wherein, the degree of depth of shallow isolated groove 705 is greater than the degree of depth of n type ion implanted region 705.But the doping content of n type ion implanted region 705 is greater than the doping content of p type trap 706 less than the doping content of p type heavily doped region 704.

Step 401S generates shallow isolated groove according to mask pattern;

Step 402S forms the p trap on p type substrate;

Step 403S forms n type ion implanted region in the p trap;

Step 404S generates grid oxide layer on n type ion implanted region;

Step 405S generates polysilicon layer on grid oxide layer;

Step 406S carries out low dose of n type ion and injects formation n type lightly doped drain in n type ion implanted region.

Step 407S forms side wall (sidewall) in the both sides of grid oxide layer and polysilicon layer;

Step 408S carries out heavy dose of p type ion and injects formation p type heavily doped region in n type ion implanted region, owing to stopping of side wall, the regional reserve part n type lightly doped drain that ion implanted region is contacted with side wall forms n type lightly doped drain.

In the above-mentioned steps, polysilicon layer, grid oxide layer, n type lightly doped drain, n type ion implanted region form programmable capacitor, and n type ion implanted region and p type heavily doped region form diode.The degree of depth of shallow isolated groove is less than the degree of depth of p trap but greater than the degree of depth of n type ion implanted region, thereby guarantee that shallow isolated groove can isolate n type ion implanted region well, make that the spacing between each one-time programmable memory cell is very little, thereby reduce the area that the One Time Programmable storage array takies.

Fig. 8 is the partial top view of the One Time Programmable storage array of p type half crastal tube structure in the fourth embodiment of the invention, among Fig. 8, each one-time programmable memory cell comprises polysilicon layer 801, metal level 802, contact hole 803, p type heavily doped region 804 and n type lightly doped drain 805 and n type ion implanted region 806.Wherein, polysilicon layer 801 is connected with word line WL1, and the metal level 802 that is connected with bit line BL1 is connected with p type heavily doped region 804 through contact hole 803.The n type ion implanted region 806 that frame of broken lines is represented, its part is covered by polysilicon layer 801.

Table 4 is the programming and the read method of the one-time programmable memory cell of p type half crastal tube structure in the fourth embodiment of the invention:

		??V _WL	??V _BL	Whether programme
		??V _WL	??V _BL	Whether programme	Programming	Select WL/ to select BL	??0V	??V _pp	Be

	??V _WL	??V _BL	Whether programme
	??V _WL	??V _BL	Whether programme		Select WL/ not select BL	??0V	??0V	Not
Do not select WL/ to select BL	??V _ppOr high resistant	??V _pp	Not		Select WL/ not select BL	??0V	??0V	Not
Do not select WL/ to select BL	??V _ppOr high resistant	??V _pp	Not		Do not select WL/ not select BL	??V _ppOr high resistant	??0V	Not
			Whether detect the sense amplifier electric current		Do not select WL/ not select BL	??V _ppOr high resistant	??0V	Not
			Whether detect the sense amplifier electric current	Read	Select WL/ to select BL	??0V	??V _read	Be
Select WL/ not select BL	??0V	??0V	Not	Read	Select WL/ to select BL	??0V	??V _read	Be
Select WL/ not select BL	??0V	??0V	Not		Do not select WL/ to select BL	??V _dd	??V _read	Not
Do not select WL/ not select BL	??V _dd	??0V	Not		Do not select WL/ to select BL	??V _dd	??V _read	Not

Table 4

In the table 4, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

On word line WL, apply 0V voltage, on bit line BL, apply voltage V _Pp, promptly on p type heavily doped region, apply puncture voltage V _PpAt this moment, the diode structure that n type ion implanted region and p type heavily doped region form makes n type ion implanted region be clamped at V _Pp-V _ThIn addition, the part that is connected with thin grid oxide layer in n type ion implanted region forms p-type inversion layer, and the electromotive force of this p-type inversion layer is understood owing to the effect of the last 0V voltage of word line WL by corresponding reduction, therefore, electrical potential difference between n type lightly doped drain and the thin grid oxide layer will be greater than the electrical potential difference between n type ion implanted region and the thin grid oxide layer, therefore, polysilicon layer, thin grid oxide layer, n type lightly doped drain, the programmable capacitor that n type ion implanted region forms will be breakdown in the coupling part of n type lightly doped drain and thin grid oxide layer, at this moment, the diode forward conducting of n type ion implanted region and p type heavily doped region formation.

Read process:

On word line WL, apply voltage 0V voltage, on bit line BL, apply voltage V _Read, promptly on p type heavily doped region, apply and read voltage V _ReadDetect sense amplifier whether electric current is arranged, if, then represent the breakdown formation resistance of programmable capacitor that polysilicon layer, thin grid oxide layer, n type lightly doped drain, n type ion implanted region form, the diode forward conducting that n type ion implanted region and p type heavily doped region form then is output as logical one; Otherwise the programmable capacitor that expression polysilicon layer, thin grid oxide layer, n type lightly doped drain, n type ion implanted region form is not breakdown, no current process, output logic " 0 ".

Embodiment five

Fig. 9 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the fifth embodiment of the invention, comprises among Fig. 9: polysilicon layer 901, thin grid oxide layer 902, p type lightly doped drain 903, n type heavily doped region 904, p type ion implanted region 905, shallow isolated groove 906, n type trap 907 and p type substrate 908.Polysilicon layer is connected to thin grid oxide layer 902 for 901 times, thin grid oxide layer is connected to the zone outside the p type ion implanted region 905 for 902 times, p type lightly doped drain 903, p type ion implanted region 905 are positioned at n type trap 907, n type heavily doped region 904 is arranged in p type ion implanted region 905, and p type lightly doped drain 903 is adjacent to p type ion implanted region 905.Polysilicon layer 901 is connected with word line WL, and n type heavily doped region 905 is connected with bit line BL.Thin grid oxide layer 902 is adjacent to p type lightly doped drain 903.

Wherein, polysilicon layer 901, thin grid oxide layer 902, p type lightly doped drain 903, p type ion implanted region 905 form programmable capacitor, and p type ion implanted region 905 forms diode with n type heavily doped region 905.Shallow isolated groove 906 is used for p type ion implanted region 905 is isolated, and wherein, the degree of depth of shallow isolated groove 906 is greater than the degree of depth of p type ion implanted region 905.But the doping content of p type ion implanted region 905 is greater than the doping content of n type trap 907 less than the doping content of n type heavily doped region 905.

Introduce the manufacture method of the one-time programmable memory cell of n type half crastal tube structure in the fifth embodiment of the invention below, concrete steps are as follows:

Step 501S generates shallow isolated groove according to mask pattern;

Step 502S forms the n trap on p type substrate;

Step 503S, deposit silicon dioxide forms grid oxide layer;

Step 504S generates polysilicon layer on grid oxide layer;

Step 505S carries out low dose of p type ion and injects formation p type lightly doped drain in the n trap;

Step 506S forms side wall (sidewall) in the both sides of grid oxide layer and polysilicon layer;

Step 507S carries out heavy dose of n type ion and injects formation n type heavily doped region in the n trap.

Step 508S forms p type ion implanted region in the n trap, wherein, p type lightly doped drain is positioned at outside the p type ion implanted region, and n type heavily doped region is positioned within the p type ion implanted region.

In the above-mentioned steps, polysilicon layer, thin grid oxide layer, p type lightly doped drain, p type ion implanted region form programmable capacitor, and p type ion implanted region and n type heavily doped region form diode.The degree of depth of shallow isolated groove is less than the degree of depth of n trap but greater than the degree of depth of p type ion implanted region, thereby guarantee that shallow isolated groove can isolate p type ion implanted region well, make that the spacing between each one-time programmable memory cell is very little, thereby reduce the area that the One Time Programmable storage array takies.

In addition, in the third embodiment of the invention, because grid oxide layer do not cover p type ion implanted region and p type lightly doped drain, therefore, and can first deposit silicon dioxide, form grid oxide layer, in the n trap, form p type ion implanted region and p type lightly doped drain again.

Figure 10 is the partial top view of the One Time Programmable storage array of n type half crastal tube structure in the fifth embodiment of the invention, among Figure 10, each one-time programmable memory cell comprises polysilicon layer 1001, metal level 1002, contact hole 1003, p type lightly doped drain 1004, n type heavily doped region 1005 and p type ion implanted region 1006.Wherein, polysilicon layer 1001 is connected with word line WL1, is connected with p type heavily doped region 1004 through contact hole 1003 as the metal level 1002 of bit line BL1.The p type ion implanted region 1006 that frame of broken lines is represented.

Table 5 is the programming and the read method of the one-time programmable memory cell of n type half crastal tube structure in the fifth embodiment of the invention:

	??V _WL	??V _BL	Whether programme
	??V _WL	??V _BL	Whether programme	Programming	Select WL/ to select BL	??V _pp	??0V	Be
Select WL/ not select BL	??V _pp	??V _ppOr high resistant	Not	Programming	Select WL/ to select BL	??V _pp	??0V	Be

		??V _WL	??V _BL	Whether programme
		??V _WL	??V _BL	Whether programme	Do not select WL/ to select BL	??0V	??0V	Not
	Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not	Do not select WL/ to select BL	??0V	??0V	Not
	Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not				Whether detect the sense amplifier electric current
Read	Select WL/ to select BL	??V _read	??0V	Be				Whether detect the sense amplifier electric current
Read	Select WL/ to select BL	??V _read	??0V	Be	Select WL/ not select BL	??V _read	??V _dd	Not
	Do not select WL/ to select BL	??0V	??0V	Not	Select WL/ not select BL	??V _read	??V _dd	Not
	Do not select WL/ to select BL	??0V	??0V	Not	Do not select WL/ not select BL	??0V	??V _dd	Not

Table 5

In the table 5, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

On word line WL, apply voltage V _Pp, on bit line BL, apply 0V voltage, promptly on n type heavily doped region, apply 0V voltage.At this moment, the diode structure that p type ion implanted region and n type heavily doped region form makes p type ion implanted region be clamped at diode cut-in voltage V _ThIn addition, the part that is connected with thin grid oxide layer in p type ion implanted region forms n type inversion layer, and the electromotive force of this n type inversion layer can be because word line WL goes up voltage V _PpEffect and by corresponding raising, therefore, electrical potential difference between p type lightly doped drain and the thin grid oxide layer will be greater than the electrical potential difference between p type ion implanted region and the thin grid oxide layer, therefore, the programmable capacitor that polysilicon layer, thin grid oxide layer, p type lightly doped drain, p type ion implanted region form will be breakdown in the coupling part of p type lightly doped drain and thin grid oxide layer, at this moment, the diode forward conducting of p type ion implanted region and n type heavily doped region formation.

Read process:

Embodiment six

Figure 11 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the sixth embodiment of the invention, comprises among Figure 11: polysilicon layer 1101, thin grid oxide layer 1102, p type ion implanted region 1103, n type heavily doped region 1104, shallow isolated groove 1105, insulating barrier 1106 and p type substrate 1107.Polysilicon layer is connected to thin grid oxide layer 1102 for 1101 times, thin grid oxide layer is connected to p type ion implanted region 1103 for 1102 times, and p type ion implanted region 1103 is positioned on the insulating barrier 1106, and heavily doped region 1104 is arranged in p type ion implanted region 1103; Polysilicon layer 1101 is connected with word line WL, and n type heavily doped region 1104 is connected with bit line BL.Thin grid oxide layer 1102 is connected with p type ion implanted region 1103.Keep preset distance between thin grid oxide layer 1102 and the n type heavily doped region 1104.

Wherein, polysilicon layer 1101, thin grid oxide layer 1102, p type ion implanted region 1103 form programmable capacitor, and p type ion implanted region 1103 forms diode with n type heavily doped region 1104.Shallow isolated groove 1105 is directly connected to insulating barrier 1106, thereby isolates p type ion implanted region 1103 reliably, and wherein, the doping content of p type ion implanted region 1103 is less than the doping content of n type heavily doped region 1104.Insulating barrier 1106 can pass through silicon-on-insulator (SOI, Silicon On Insulator) technology or silicon on sapphire (SOS, Silicon On Sapphire) technology manufacturing, employing has the high dielectric-constant dielectric material such as silicon dioxide, sapphire etc. and makes insulating barrier.Because insulating barrier 1106 has the good insulation performance characteristic, therefore need not on substrate 1107, make the transoid trap, thereby further reduce the area of memory cell, in addition, adopt insulating barrier to substitute the transoid trap of conventional bulk silicon technology, thereby can avoid the inferior position on the bulk silicon technological performance, as bolt-lock effect etc.Make the disposable programmable memory of insulating barrier for adopting silicon on sapphire technology, because sapphire have extremely strong stability, be not subject to influence as various abominable external environment conditions such as radiation, HTHPs, therefore, greatly improve the stability and the reliability of the storage of disposable programmable memory.

Introduce the manufacture method of the one-time programmable memory cell of n type half crastal tube structure in the sixth embodiment of the invention below, concrete steps are as follows:

Step 601S generates shallow isolated groove according to mask pattern; Wherein, shallow isolated groove is deeply to insulating barrier;

Step 602S forms p type ion implanted region on insulating barrier;

Step 603S generates grid oxide layer on p type ion implanted region;

Step 604S generates polysilicon layer on grid oxide layer;

Step 605S carries out heavy dose of n type ion and injects formation n type heavily doped region in p type ion implanted region.

In the above-mentioned steps, polysilicon layer, grid oxide layer, p type ion implanted region form programmable capacitor, and p type ion implanted region and n type heavily doped region form diode.Shallow isolated groove is directly connected to insulating barrier from top to down, thereby isolates p type ion implanted region reliably, makes that the spacing between each one-time programmable memory cell is very little, thereby reduces the area that the One Time Programmable storage array takies.

The partial top view of embodiment six is identical with Fig. 2.

Table 6 is the programming and the read method of the one-time programmable memory cell of n type half crastal tube structure in the sixth embodiment of the invention:

	??V _WL	??V _BL	Whether programme
	??V _WL	??V _BL	Whether programme	Programming	Select WL/ to select BL	??V _pp	??0V	Be
Select WL/ not select BL	??V _pp	??V _ppOr high resistant	Not	Programming	Select WL/ to select BL	??V _pp	??0V	Be
Select WL/ not select BL	??V _pp	??V _ppOr high resistant	Not		Do not select WL/ to select BL	??0V	??0V	Not
Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not		Do not select WL/ to select BL	??0V	??0V	Not
Do not select WL/ not select BL	??0V	??V _ppOr high resistant	Not					Whether detect the sense amplifier electric current

	??V _WL	??V _BL	Whether programme
	??V _WL	??V _BL	Whether programme	Read	Select WL/ to select BL	??V _read	??0V	Be
Select WL/ not select BL	??V _read	??V _dd	Not	Read	Select WL/ to select BL	??V _read	??0V	Be
Select WL/ not select BL	??V _read	??V _dd	Not		Do not select WL/ to select BL	??0V	??0V	Not
Do not select WL/ not select BL	??0V	??V _dd	Not		Do not select WL/ to select BL	??0V	??0V	Not

Table 6

In the table 6, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

On word line WL, apply puncture voltage V _PpOn bit line BL, apply 0V voltage, promptly on n type heavily doped region, apply 0V voltage, thereby the programmable capacitor that polysilicon layer, thin grid oxide layer, p type ion implanted region are formed punctures, and the diode forward conducting that p type ion implanted region and n type heavily doped region are formed.

Read process:

On word line WL, apply and read voltage V _ReadOn bit line BL, apply 0V voltage, promptly on n type heavily doped region, apply 0V voltage, detect sense amplifier whether electric current is arranged, if, then represent the breakdown formation resistance of programmable capacitor that polysilicon layer, thin grid oxide layer, p type ion implanted region form, the diode forward conducting that p type ion implanted region and n type heavily doped region form then is output as logical one; Otherwise the programmable capacitor that expression polysilicon layer, thin grid oxide layer, p type ion implanted region form is not breakdown, output logic " 0 ".

Embodiment seven

Figure 12 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the seventh embodiment of the invention, comprises among Figure 12: polysilicon layer 1201, thin grid oxide layer 1202, n type ion implanted region 1203, p type heavily doped region 1204, shallow isolated groove 1205, insulating barrier 1206 and p type substrate 1207.Polysilicon layer is connected to thin grid oxide layer 1202 for 1201 times, thin grid oxide layer is connected to n type ion implanted region 1203 for 1202 times, and n type ion implanted region 1203 is positioned on the insulating barrier 1206, and p type heavily doped region 1204 is arranged in n type ion implanted region 1203.Polysilicon layer 1201 is connected with word line WL, and p type heavily doped region 1204 is connected with bit line BL.Thin grid oxide layer 1202 is connected with n type ion implanted region 1203.Keep preset distance between thin grid oxide layer 1202 and the p type heavily doped region 1204.

Wherein, polysilicon layer 1201, thin grid oxide layer 1202, n type ion implanted region 1203 form programmable capacitor, and n type ion implanted region 1203 forms diode with p type heavily doped region 1204.Shallow isolated groove 1205 is directly connected to insulating barrier 1206, thereby isolates n type ion implanted region 1203 reliably.The doping content of n type ion implanted region 1203 is less than the doping content of p type heavily doped region 1204.Insulating barrier 1206 can be made by silicon-on-insulator process or silicon on sapphire technology, and employing has the high dielectric-constant dielectric material such as silicon dioxide, sapphire etc. and makes insulating barrier.Because insulating barrier 1206 has the good insulation performance characteristic, therefore need not on substrate 1207, make the transoid trap, thereby further reduce the area of memory cell, in addition, adopt insulating barrier to substitute the transoid trap of conventional bulk silicon technology, thereby can avoid the inferior position on the bulk silicon technological performance, as bolt-lock effect etc.Make the disposable programmable memory of insulating barrier for adopting silicon on sapphire technology, because sapphire have extremely strong stability, be not subject to influence as various abominable external environment conditions such as radiation, HTHPs, therefore, greatly improve the stability and the reliability of the storage of disposable programmable memory.

Step 701S generates shallow isolated groove according to mask pattern; Wherein, shallow isolated groove is deeply to insulating barrier;

Step 702S forms n type ion implanted region on insulating barrier;

Step 703S generates grid oxide layer on n type ion implanted region;

Step 704S generates polysilicon layer on grid oxide layer;

Step 705S carries out heavy dose of p type ion and injects formation p type heavily doped region in n type ion implanted region.

In the above-mentioned steps, polysilicon layer, grid oxide layer, n type ion implanted region form programmable capacitor, and n type ion implanted region and p type heavily doped region form diode.Shallow isolated groove is directly connected to insulating barrier from top to down, thereby isolates n type ion implanted region reliably, makes that the spacing between each one-time programmable memory cell is very little, thereby reduces the area that the One Time Programmable storage array takies.

The partial top view of embodiment seven is identical with Fig. 4.

Table 7 is the programming and the read method of the one-time programmable memory cell of p type half crastal tube structure in the second embodiment of the invention:

Table 7

In the table 7, puncture voltage V _Pp〉=2 operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

On word line WL, apply 0V voltage, on bit line BL, apply puncture voltage V _Pp, promptly on p type heavily doped region, apply puncture voltage V _PpThereby the programmable capacitor that polysilicon layer, thin grid oxide layer, n type ion implanted region are formed punctures, and the diode forward conducting that p type heavily doped region and n type ion implanted region are formed.

Read process:

On word line WL, apply voltage 0V voltage, on bit line BL, apply and read voltage V _Read, promptly on p type heavily doped region, apply and read voltage V _ReadWhether have electric current, if then represent the breakdown formation resistance of programmable capacitor that polysilicon layer, thin grid oxide layer, n type ion implanted region form if detecting sense amplifier, the diode forward conducting that p type heavily doped region and n type ion implanted region form then is output as logical one; Otherwise the programmable capacitor that expression polysilicon layer, thin grid oxide layer, n type ion implanted region form is not breakdown, output logic " 0 ".

Embodiment eight

Figure 13 is the end view of the one-time programmable memory cell structure of n type half crastal tube structure in the eighth embodiment of the invention, comprises among Figure 13: polysilicon layer 1301, thin grid oxide layer 1302, p type lightly doped drain 1303, n type heavily doped region 1304, p type ion implanted region 1305, shallow isolated groove 1306, insulating barrier 1307 and p type substrate 1308.Polysilicon layer is connected to thin grid oxide layer 1302 for 1301 times, thin grid oxide layer 1302 is adjacent to p type lightly doped drain 1303, p type lightly doped drain 1303, n type heavily doped region 1304 are arranged in p type ion implanted region 1305, and p type ion implanted region 1305 is positioned on the insulating barrier 1307.Polysilicon layer 1301 is connected with word line WL, and n type heavily doped region 1304 is connected with bit line BL.Thin grid oxide layer is connected to p type ion implanted region 1305 for 1302 times.

Wherein, polysilicon layer 1301, thin grid oxide layer 1302, p type lightly doped drain 1303, p type ion implanted region 1305 form programmable capacitor, and p type ion implanted region 1305 forms diode with n type heavily doped region 1304.Shallow isolated groove 1306 is directly connected to insulating barrier 1307, thereby isolates p type ion implanted region 1305 reliably, and wherein, the doping content of p type ion implanted region 1305 is less than the doping content of n type heavily doped region 1304.Insulating barrier 1307 can pass through silicon-on-insulator (SOI, Silicon On Insulator) technology or silicon on sapphire (SOS, Silicon On Sapphire) technology manufacturing, employing has the high dielectric-constant dielectric material such as silicon dioxide, sapphire etc. and makes insulating barrier.Because insulating barrier 1307 has the good insulation performance characteristic, therefore need not on substrate 1308, make the transoid trap, thereby further reduce the area of memory cell, in addition, adopt insulating barrier to substitute the transoid trap of conventional bulk silicon technology, thereby can avoid the inferior position on the bulk silicon technological performance, as bolt-lock effect etc.Make the disposable programmable memory of insulating barrier for adopting silicon on sapphire technology, because sapphire have extremely strong stability, be not subject to influence as various abominable external environment conditions such as radiation, HTHPs, therefore, greatly improve the stability and the reliability of the storage of disposable programmable memory.

Step 801S generates shallow isolated groove according to mask pattern; Wherein, shallow isolated groove is deeply to insulating barrier;

Step 802S forms p type ion implanted region on insulating barrier;

Step 803S generates grid oxide layer on p type ion implanted region;

Step 804S generates polysilicon layer on grid oxide layer;

Step 805S carries out low dose of p type ion at p type ion implanted region and injects formation p type lightly doped drain;

Step 806S forms side wall (sidewall) in the both sides of grid oxide layer and polysilicon layer;

Step 807S carries out heavy dose of n type ion and injects formation n type heavily doped region in p type ion implanted region, owing to stopping of side wall, the regional reserve part p type lightly doped drain that ion implanted region is contacted with side wall forms p type lightly doped drain.

In the above-mentioned steps, polysilicon layer, grid oxide layer, p type lightly doped drain, p type ion implanted region form programmable capacitor, and p type ion implanted region and n type heavily doped region form diode.Shallow isolated groove is directly connected to insulating barrier from top to down, thereby isolates p type ion implanted region reliably, makes that the spacing between each one-time programmable memory cell is very little, thereby reduces the area that the One Time Programmable storage array takies.

The partial top view of embodiment eight is identical with Fig. 6.

Table 8 is the programming and the read method of the one-time programmable memory cell of n type half crastal tube structure in the first embodiment of the invention:

Table 8

In the table 8, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

Read process:

Embodiment nine

Figure 14 is the end view of the one-time programmable memory cell structure of p type half crastal tube structure in the ninth embodiment of the invention, comprises among Figure 14: polysilicon layer 1401, thin grid oxide layer 1402, n type lightly doped drain 1403, p type heavily doped region 1404, n type ion implanted region 1405, shallow isolated groove 1406, insulating barrier 1407 and p type substrate 1408.Polysilicon layer is connected to thin grid oxide layer 1402 for 1401 times, thin grid oxide layer 1402 is adjacent to n type lightly doped drain 1403, n type lightly doped drain 1403, p type heavily doped region 1404 are arranged in n type ion implanted region 1405, and n type ion implanted region 1405 is positioned on the insulating barrier 1407.Polysilicon layer 1401 is connected with word line WL, and p type heavily doped region 1404 is connected with bit line BL.Thin grid oxide layer is connected to n type ion implanted region 1405 for 1402 times.

Wherein, polysilicon layer 1401, thin grid oxide layer 1402, n type lightly doped drain 1403, n type ion implanted region 1405 form programmable capacitor, and n type ion implanted region 1405 forms diode with p type heavily doped region 1404.Shallow isolated groove 1406 is directly connected to insulating barrier 1407, thereby isolates n type ion implanted region 1405 reliably.The doping content of n type ion implanted region 1405 is less than the doping content of p type heavily doped region 1404.Insulating barrier 1407 can be made by silicon-on-insulator process or silicon on sapphire technology, and employing has the high dielectric-constant dielectric material such as silicon dioxide, sapphire etc. and makes insulating barrier.Because insulating barrier 1407 has the good insulation performance characteristic, therefore need not on substrate 1408, make the transoid trap, thereby further reduce the area of memory cell, in addition, adopt insulating barrier to substitute the transoid trap of conventional bulk silicon technology, thereby can avoid the inferior position on the bulk silicon technological performance, as bolt-lock effect etc.Make the disposable programmable memory of insulating barrier for adopting silicon on sapphire technology, because sapphire have extremely strong stability, be not subject to influence as various abominable external environment conditions such as radiation, HTHPs, therefore, greatly improve the stability and the reliability of the storage of disposable programmable memory.

Step 901S generates shallow isolated groove according to mask pattern; Wherein, shallow isolated groove is deeply to insulating barrier;

Step 902S forms n type ion implanted region on insulating barrier;

Step 903S generates grid oxide layer on n type ion implanted region;

Step 904S generates polysilicon layer on grid oxide layer;

Step 905S carries out low dose of n type ion and injects formation n type lightly doped drain in n type ion implanted region.

Step 906S forms side wall (sidewall) in the both sides of grid oxide layer and polysilicon layer;

Step 907S carries out heavy dose of p type ion at n type ion implanted region and injects formation p type heavily doped region, and owing to stopping of side wall, the regional reserve part n type lightly doped drain that ion implanted region is contacted with side wall forms n type lightly doped drain.

In the above-mentioned steps, polysilicon layer, grid oxide layer, n type lightly doped drain, n type ion implanted region form programmable capacitor, and n type ion implanted region and p type heavily doped region form diode.Shallow isolated groove is directly connected to insulating barrier from top to down, thereby isolates n type ion implanted region reliably, makes that the spacing between each one-time programmable memory cell is very little, thereby reduces the area that the One Time Programmable storage array takies.

The partial top view of embodiment nine is identical with Fig. 8.

Table 9 is the programming and the read method of the one-time programmable memory cell of p type half crastal tube structure in the ninth embodiment of the invention:

Table 9

In the table 9, puncture voltage V _Pp〉=2 times of operating voltage V _Dd, read voltage V _Read≤ operating voltage V _Dd

Programming process:

On word line WL, apply 0V voltage, on bit line BL, apply voltage V _Pp, promptly on p type heavily doped region, apply puncture voltage V _PpAt this moment, the diode structure that n type ion implanted region and p type heavily doped region form makes n type ion implanted region be clamped at V _Pp-V _ThIn addition, the part that is connected with thin grid oxide layer in n type ion implanted region forms p-type inversion layer, and the electromotive force of this p-type inversion layer is understood owing to the effect of the last 0V voltage of word line WL by corresponding reduction, therefore, electrical potential difference between n type lightly doped drain and the thin grid oxide layer is greater than the electrical potential difference between n type ion implanted region and the thin grid oxide layer, therefore, polysilicon layer, thin grid oxide layer, n type lightly doped drain, the programmable capacitor that n type ion implanted region forms will be breakdown in the coupling part of n type lightly doped drain and thin grid oxide layer, at this moment, the diode forward conducting of n type ion implanted region and p type heavily doped region formation.

Read process:

On word line WL, apply voltage 0V voltage, on bit line BL, apply voltage V _Read, promptly on p type heavily doped region, apply and read voltage V _ReadDetect sense amplifier whether electric current is arranged, if, then represent the breakdown formation resistance of programmable capacitor that polysilicon layer, thin grid oxide layer, n type lightly doped drain, n type ion implanted region form, the diode forward conducting that n type ion implanted region and p type heavily doped region are formed then is output as logical one; Otherwise the programmable capacitor that expression polysilicon layer, thin grid oxide layer, n type lightly doped drain, n type ion implanted region form is not breakdown, output logic " 0 ".

Figure 15 A is the equivalent circuit theory figure of the one-time programmable memory cell of n type half crastal tube structure among the present invention first and third, five, six, eight embodiment, comprise the diode 1501 and the electric capacity 1502 that are connected in series among Figure 15, wherein, diode 1501 is connected with bit line BL, and electric capacity 1502 is connected with word line WL.

Figure 15 B is the equivalent circuit theory figure after the one-time programmable memory cell programming of n type half crastal tube structure among the present invention first and third, five, six, eight embodiment punctures, comprise the diode 1501 and the resistance 1503 that are connected in series among the figure, wherein, after breakdown under the effect of the electric capacity among Figure 15 A 1502 at program voltage, form resistance 1503.The direction of electric current I along word line WL to bit line BL flows.

Figure 16 is the partial schematic diagram of the One Time Programmable storage array of n type half crastal tube structure among the present invention first and third, five, six, eight embodiment, the one-time programmable memory cell, word line WL1, word line WL2, word line WL3, bit line BL1, bit line BL2, the bit line BL3 that comprise a plurality of n type half crastal tube structures among Figure 16, each one-time programmable memory cell is connected with a bit lines with a word line.The one-time programmable memory cell that connects word line WL2, bit line BL2 respectively that is positioned at figure central authorities has been programmed puncture, therefore, represents this one-time programmable memory cell with the equivalent electric circuit of resistance series diode among the figure.

Figure 17 A is the circuit theory diagrams of the one-time programmable memory cell of p type half crastal tube structure among the present invention second, four, seven, nine embodiment, comprise the diode 1701 and the electric capacity 1702 that are connected in series among Figure 17 A, wherein, diode 1701 is connected with bit line BL, and electric capacity 1702 is connected with word line WL.

Figure 17 B is the equivalent circuit theory figure after the one-time programmable memory cell programming of p type half crastal tube structure among the present invention second, four, seven, nine embodiment punctures, comprise the diode 1701 and the resistance 1703 that are connected in series among Figure 17 B, wherein, after breakdown under the effect of the electric capacity among Figure 17 A 702 at program voltage, form resistance 1703.The direction of electric current I along bit line BL to word line WL flows.

Figure 18 is the partial schematic diagram of the One Time Programmable storage array of p type half crastal tube structure among the present invention second, four, seven, nine embodiment, the one-time programmable memory cell, word line WL1, word line WL2, word line WL3, bit line BL1, bit line BL2, the bit line BL3 that comprise a plurality of p type half crastal tube structures among Figure 18, each one-time programmable memory cell is connected with a bit lines with a word line.The one-time programmable memory cell that connects word line WL2, bit line BL2 respectively that is positioned at figure central authorities has been programmed puncture, therefore, represents this one-time programmable memory cell with the equivalent electric circuit of resistance series diode among the figure.

Among the invention described above embodiment, first and second, six, seven embodiment form programmable capacitor by polysilicon layer, thin grid oxide layer, ion implanted region, form and the programmable capacitor diode in series by ion implanted region and heavily doped region; The 3rd, four, five, eight, nine embodiment pass through polysilicon layer, thin grid oxide layer, lightly doped drain, ion implanted region forms programmable capacitor, form and the programmable capacitor diode in series by ion implanted region and heavily doped region, form conducting resistance when utilizing programmable capacitor breakdown, still be the characteristic of insulation electric capacity and the forward conduction and the characteristic of oppositely closing of diode when not puncturing, realize that memory cell area only takies transistor area half, the integration density height, can need not to increase special process with the dwindling and dwindle of technology characteristics size with same ratio, the disposable programmable non-volatile memory that reliability is high.

In addition, among the invention described above embodiment, six, seven, eight, nine embodiment utilize insulating barrier in silicon-on-insulator or the silicon on sapphire technology to replace transoid trap in the conventional bulk silicon technology, have improved the stability and the reliability of disposable programmable non-volatile memory storage greatly.

The above only is preferred embodiment of the present invention; not in order to restriction the present invention; within the spirit and principles in the present invention all, any modification, the change that the embodiment of the invention is done, make up, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. the disposable programmable memory of a half crastal tube structure is characterized in that, described semitransistor comprises:

The diode that forms by described ion implanted region and heavily doped region;

2. disposable programmable memory according to claim 1 is characterized in that, described semitransistor comprises:

3. disposable programmable memory according to claim 1 is characterized in that,

The doping content of described ion implanted region is less than the doping content of described heavily doped region.

4. disposable programmable memory according to claim 1 is characterized in that,

Described ion implanted region comprises n type or p type ion implanted region.

5. disposable programmable memory according to claim 1 is characterized in that,

Described heavily doped region comprises n type or p type heavily doped region.

6. disposable programmable memory according to claim 1 is characterized in that,

The doping type of described lightly doped drain is opposite with the doping type of described heavily doped region.

7. the manufacture method of the disposable programmable memory of a half crastal tube structure is characterized in that, may further comprise the steps:

Generate isolated groove;

On substrate, form trap;

In described trap, form ion implanted region;

On described ion implanted region, generate grid oxide layer;

On described grid oxide layer, generate polysilicon layer;

In described ion implanted region, form lightly doped drain;

Both sides at described grid oxide layer and described polysilicon layer form side wall;

In described ion implanted region, form heavily doped region;

Described polysilicon layer, described grid oxide layer, described lightly doped drain, described ion implanted region form programmable capacitor;

The diode that described ion implanted region and described heavily doped region form;

Described programmable capacitor and described diode are connected in series.

8. the manufacture method of the disposable programmable memory of a half crastal tube structure is characterized in that, may further comprise the steps:

Generate isolated groove;

On substrate, form trap;

Generate grid oxide layer;

On described grid oxide layer, generate polysilicon layer;

In described trap, form lightly doped drain;

In described trap, form heavily doped region;

In described trap, form ion implanted region;

Described lightly doped drain is positioned at outside the described ion implanted region, and described heavily doped region is positioned within the described ion implanted region;

Wherein, described polysilicon layer, described thin grid oxide layer, described ion implanted region form programmable capacitor;

Described ion implanted region and described heavily doped region form diode;

Described programmable capacitor and described diode are connected in series.

9. according to claim 7 or 8 described manufacture methods, it is characterized in that,

10. according to claim 7 or 8 described manufacture methods, it is characterized in that,

11. according to claim 7 or 8 described manufacture methods, it is characterized in that,

Described ion implanted region comprises n type or p type ion implanted region.

12. according to claim 7 or 8 described manufacture methods, it is characterized in that,

Described heavily doped region comprises n type or p type heavily doped region.

13. according to claim 7 or 8 described manufacture methods, it is characterized in that,

Described lightly doped drain is opposite with the doping type of described heavily doped region.

14. according to claim 7 or 8 described manufacture methods, it is characterized in that,

Described trap comprises n type or p type trap.

15. the programmed method of the disposable programmable memory of a half crastal tube structure is characterized in that,

Described semitransistor comprises:

Described programmed method comprises:

On described word line, apply first voltage, on described bit line, apply second voltage, programmable capacitor is punctured the formation conducting resistance, and make diode current flow.

16. programmed method according to claim 15 is characterized in that,

17. the read method of the disposable programmable memory of a half crastal tube structure is characterized in that,

Described semitransistor comprises:

Described read method comprises:

Whether apply tertiary voltage on described word line, apply the 4th voltage on described bit line, detecting sense amplifier has electric current, if, then represent the breakdown formation resistance of programmable capacitor, diode current flow is output as logical one; Otherwise the expression programmable capacitor is not breakdown, output logic " 0 ".