CN101752322A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN101752322A CN101752322A CN200810186349.3A CN200810186349A CN101752322A CN 101752322 A CN101752322 A CN 101752322A CN 200810186349 A CN200810186349 A CN 200810186349A CN 101752322 A CN101752322 A CN 101752322A
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- China
- Prior art keywords
- chip
- adhesion coating
- base plate
- circuit base
- bonding wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims description 77
- 238000000576 coating method Methods 0.000 claims description 77
- 238000000034 method Methods 0.000 claims description 21
- 239000000084 colloidal system Substances 0.000 claims description 16
- 238000012856 packing Methods 0.000 claims description 16
- 238000007711 solidification Methods 0.000 claims description 2
- 230000008023 solidification Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 12
- 239000012790 adhesive layer Substances 0.000 abstract 4
- 239000002390 adhesive tape Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Wire Bonding (AREA)
Abstract
The invention discloses a chip packaging structure, which comprises a circuit substrate, a chip, a B stage adhesive layer, a wire frame, a plurality of first bonding wires, a plurality of second bonding wires and a plurality of third bonding wires. The chip, the B stage adhesive layer and the wire frame are arranged on the circuit substrate, wherein, the wire frame comprises a plurality of pins, part of the pins are embedded in the B stage adhesive layer, and one end of each pin is exposed out of the B stage adhesive layer. The first bonding wires are electrically connected with the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the pins. The third bonding wires are electrically connected between the pins and the circuit substrate. In addition, the invention also provides a manufacturing method of the chip packaging structure.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and particularly relevant for a kind of chip-packaging structure and manufacture method thereof.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the making (IC process) of the design of integrated circuit (IC design), integrated circuit and the encapsulation (IC package) of integrated circuit.
In the making of integrated circuit, chip (chip) is to finish via wafer (wafer) making, formation integrated circuit and cut crystal steps such as (wafer sawing).Wafer has an active face (activesurface), the surface with active element (active element) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active face of wafer more disposed a plurality of weld pads (bonding pad), can outwards be electrically connected at a carrier (carrier) via these weld pads so that finally cut formed chip by wafer.Carrier for example is a lead frame (leadframe), a base plate for packaging (package substrate) or is made up of jointly a lead frame and a base plate for packaging.The mode that chip can see through routing joint (wire bonding) or flip chip bonding (flip chip bonding) is connected on the carrier, makes the weld pad of chip can be electrically connected at the contact of carrier, to constitute a chip-packaging structure.
Generally speaking, in the manufacture process of chip-packaging structure, be to use adhesive tape (tape) that lead frame is fixed in base plate for packaging.Owing to must dispose adhesive tape respectively in each zone on base plate for packaging surface according to the shape of lead frame, increase manufacturing cost so can expend the more time.In addition, the high price of adhesive tape also increases the manufacturing cost of chip-packaging structure.
Summary of the invention
The invention provides a kind of chip-packaging structure, its manufacturing cost is comparatively cheap.
The invention provides a kind of manufacture method of chip-packaging structure, its manufacture process comparatively saves time.
The present invention proposes a kind of chip-packaging structure, and it comprises a circuit base plate, a chip, a B rank adhesion coating, a lead frame, many first bonding wires, many second bonding wires and many articles the 3rd bonding wires.Chip configuration is on circuit base plate.B rank adhesion coating is disposed on the circuit base plate.Lead frame is disposed on the circuit base plate, and wherein lead frame comprises many pins, and (embedded) imbedded in the adhesion coating of B rank in the subregion of pin, and a terminal system of each pin is exposed to outside the adhesion coating of B rank.
In one embodiment of this invention, above-mentioned B rank adhesion coating has a ring-shaped continuous pattern, and the B rank adhesion coating with ring-shaped continuous pattern is around chip, and the subregion of pin is coated.
In one embodiment of this invention, above-mentioned B rank adhesion coating has a plurality of discrete blockies, and the B rank adhesion coating of each blocky of tool coats the subregion of one of them pin respectively.
In one embodiment of this invention, above-mentioned lead frame is the lead frame of a centreless bar.
In one embodiment of this invention, above-mentioned chip-packaging structure more comprises a packing colloid, is disposed on the circuit base plate, wherein packing colloid coating chip, B rank adhesion coating, lead frame, first bonding wire, second bonding wire and the 3rd bonding wire.
The present invention proposes a kind of manufacture method of chip-packaging structure.At first, form a B rank adhesion coating on a circuit base plate, and through B rank adhesion coating one lead frame is fixed on the circuit base plate, wherein lead frame comprises many pins, and the subregion of pin is embedded in the adhesion coating of B rank, and an end of each pin is to be exposed to outside the adhesion coating of B rank.Then, a chip is fixed on the circuit base plate.Afterwards, form many first bonding wires, so that chip and circuit base plate electrically connect.Form many second bonding wires, so that the end of chip and pin electrically connects.Form many articles the 3rd bonding wires, so that the end of pin and circuit base plate electrically connect.
In one embodiment of this invention, the above-mentioned B rank adhesion coating that sees through is fixed in method on the circuit base plate with lead frame and is included in and forms a second order adhesion coating (two stage adhesive) on the circuit base plate, make second order adhesion coating B rankization (B-stagized) forming a B rank adhesion coating, lead frame is pressed in the adhesion coating of B rank, and with B rank adhesion coating full solidification.
In one embodiment of this invention, the manufacture method of above-mentioned chip-packaging structure more is included in and forms a packing colloid on the circuit base plate, so that packing colloid coating chip, B rank adhesion coating, lead frame, first bonding wire, second bonding wire and the 3rd bonding wire.
The present invention utilizes B rank adhesion coating that lead frame is fixed on the circuit base plate, because the process of configuration B rank adhesion coating comparatively saves time and the price of B rank adhesion coating is cheaper, so the present invention can save manufacturing time and reduce manufacturing cost.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Figure 1A is the generalized section of the chip-packaging structure of one embodiment of the invention.
Figure 1B is the schematic top plan view of the chip-packaging structure of Figure 1A.
Fig. 2 is the schematic top plan view of the chip-packaging structure of another embodiment of the present invention.
Fig. 3 A to Fig. 3 E is the generalized section of manufacture method of the chip-packaging structure of Figure 1A.
The main element symbol description:
100,100 ': chip-packaging structure
110: circuit base plate
120: chip
130,130 ': B rank adhesion coating
140: lead frame
142: pin
150: the first bonding wires
160: the second bonding wires
170: the three bonding wires
180: the chip join layer
190: packing colloid
D: distance
E: end
P: weld pad
S1: active surface
S2: the back side
X: second order adhesion coating
Embodiment
Figure 1A is the generalized section of the chip-packaging structure of one embodiment of the invention.Please refer to Figure 1A, the chip-packaging structure 100 of present embodiment comprises a circuit base plate 110, a chip 120, a B rank adhesion coating 130.Chip 120 is disposed on the circuit base plate 110.B rank adhesion coating 130 is disposed on the circuit base plate 110.Lead frame 140 is disposed on the circuit base plate 110, and wherein lead frame 140 comprises many pins 142, and the subregion of pin 142 is embedded in the B rank adhesion coating 130, and a terminal E of each pin 142 is exposed to outside the B rank adhesion coating 130.
Can see through control pin 142 apart from d and be absorbed in the height of B rank adhesion coating and adjust between pin 142 and the circuit base plate 110 to cooperate follow-up manufacture procedure of adhesive, makes it have preferable process parameter.In addition, be adhered between substrate and the pin with adhesive tape compared to existing, pin 142 has more contact area with B rank adhesion coating 130, and makes the B rank adhesion coating 130 can be by pin 142 being coated the adhesion that increases by 110 of pin 142 and circuit base plates.
Existing chip-packaging structure often utilizes chip carrier to sink to designing to reduce the bonding wire height, can be more consistent and make lead frame have a side of bonding wire and do not have the height of packing colloid of the opposite side of bonding wire, because of the height of the packing colloid of lead frame both sides differs the probability of warpage takes place to reduce chip-packaging structure.It should be noted that having chip carrier sinks the lead frame of design after being produced, the difference in height of its chip carrier and pin can't change for fixing.In the present embodiment, have apart from d between pin 142 and the circuit base plate 110, sink to designing same effect and can reach with the said chip seat.In addition, compared to the design of sinking of existing chip seat, can see through control pin 142 apart from d and be absorbed in the height of B rank adhesion coating and adjust between pin 142 and the circuit base plate 110 makes it have more variability in design with disposing.
Please refer to Figure 1A, in the present embodiment, chip-packaging structure 100 more comprises many first bonding wires 150, many second bonding wires 160 and many articles the 3rd bonding wires 170.First bonding wire 150 is electrically connected between chip 120 and the circuit base plate 110.Second bonding wire 160 is electrically connected between the terminal E of chip 120 and pin 142.The 3rd bonding wire 170 is electrically connected between the terminal E and circuit base plate 110 of pin 142.
Specifically, chip 120 has an active surperficial S1, an a plurality of weld pad P and back side S2 who is positioned on the active surperficial S1.Circuit base plate 110 also has a plurality of position weld pad P thereon.Chip-packaging structure 100 more comprises a chip join layer 180, and this chip join layer 180 is disposed between the back side S2 and circuit base plate 110 of chip 120.First bonding wire 150 is electrically connected between the part of solder pads P of the part of solder pads P of chip 120 and circuit base plate 110, and second bonding wire 160 is electrically connected between the terminal E of the part of solder pads P of chip 120 and pin 142.
Right the present invention does not limit the mode of connection of chip-packaging structure 100.In other words, compared to the above-mentioned mode of connection, chip-packaging structure 100 of the present invention more can utilize other the mode of connection, reaches the purpose that electrically connects each element.
In the present embodiment, lead frame 140 is the lead frame of a centreless bar.Chip-packaging structure 100 more comprises a packing colloid 190, and packing colloid 190 is disposed on the circuit base plate 110, wherein packing colloid 190 coating chips 120, B rank adhesion coating 130, lead frame 140, first bonding wire 150, second bonding wire 160 and the 3rd bonding wire 170.
Figure 1B is the schematic top plan view of the chip-packaging structure of Figure 1A.Please refer to Figure 1B, the B rank adhesion coating 130 of Figure 1A has a ring-shaped continuous pattern, and the B rank adhesion coating 130 with ring-shaped continuous pattern is around chip 120, and the subregion of pin 142 is coated.
In the present embodiment, the weld pad P on the chip 120 can directly see through second bonding wire 160 and be electrically connected at a pin 142.It should be noted that, being arranged in weld pad P on the substrate 110 can see through the internal wiring (not illustrating in figure) of substrate 110 and electrically connect, and make the weld pad P on the chip 120 more can see through the weld pad P on first bonding wire 150, the substrate 110, internal wiring, another weld pad P on the substrate 110 and the 3rd bonding wire 170 of substrate 110 in regular turn, and be electrically connected at a pin 142.In other words, fixing all in the configuration of weld pad P on the chip 120 and pin 142 and under the situation that can't change, weld pad on the chip 120 and with its distance pin 142 far away, can be by the configuration of the internal wiring of aforesaid substrate 110, and be easy to mutual electric connection.
Fig. 2 is the schematic top plan view of the chip-packaging structure of another embodiment of the present invention.Please refer to Fig. 2, B rank adhesion coating 130 compared to the chip-packaging structure 100 of Figure 1B, the B rank adhesion coating 130 ' of the chip-packaging structure 100 ' of present embodiment has a plurality of discrete blockies, and the B rank adhesion coating 130 ' of each blocky of tool coats the subregion of wherein one or more pins 142 respectively.
Below the manufacture method of the chip-packaging structure 100 of Figure 1A is explained.Fig. 3 A to Fig. 3 E is the generalized section of manufacture method of the chip-packaging structure of Figure 1A.At first, please refer to Fig. 3 A, a circuit base plate 110 with a plurality of weld pad P is provided, on circuit base plate 110, form a second order adhesion coating X.Then, please refer to Fig. 3 B, second order adhesion coating X is carried out the B rankization to form a B rank adhesion coating 130.
Specifically, owing to second order adhesion coating X is formed by the thermosetting sticky material manufacturing with second order (A-B rank and B-C rank) character, so B rank adhesion coating 130 forms after second order adhesion coating X is by the B rankization.
In the present embodiment, B rank adhesion coating 130 for example can be ABLESTIK 8008,8008HT, 6200,6201,6202C or HITACHI Chemical CO., the SA-200-6 that Ltd. provides, SA-200-10 or other similar B rank glue materials.
Afterwards, please refer to Fig. 3 C, a lead frame 140 is provided, lead frame 140 is pressed in the B rank adhesion coating 130, and B rank adhesion coating 130 is further solidified.Wherein lead frame 140 comprises many pins 142, and the subregion of pin 142 is embedded in the B rank adhesion coating 130, and a terminal system of each pin 142 is exposed to outside the B rank adhesion coating 130.
Then, please refer to Fig. 3 D, provide one to have an active surperficial S1, a back side S2 and a plurality of chip 120 that is positioned at the weld pad P on the active surperficial S1.On circuit base plate 110, form a chip join layer 180, and be adhered on the circuit base plate 110 through the back side S2 of chip join layer 180 with chip 120.In the present embodiment, chip join layer 180 also can be applied in the back side of chip 120 S2, to carry out engaging between chip 120 and the circuit base plate 110.
Afterwards, please refer to Fig. 3 E, form first bonding wire 150, second bonding wire 160 and the 3rd bonding wire 170, wherein first bonding wire 150 is to use so that chip 120 electrically connects through one of them the weld pad P on the active surperficial S1 and one of them the weld pad P on the circuit base plate 110, second bonding wire 160 is with so that chip 120 sees through the terminal E of another weld pad P wherein and pin 142 on the active surperficial S1 electrically connects, and the 3rd bonding wire 170 is with so that another weld pad P electric connection wherein on the terminal E of pin 142 and the circuit base plate 110.In the present embodiment, the formation of first bonding wire 150, second bonding wire 160 and the 3rd bonding wire 170 order is not limit.Then, please refer to Figure 1A, packing colloid 190 coating chips 120, B rank adhesion coating 130, lead frame 140, first bonding wire 150, second bonding wire 160 and the 3rd bonding wire 170 on circuit base plate 110, form a packing colloid 190, so that can obtain chip-packaging structure 100.
Number that it should be noted that first bonding wire 150, second bonding wire 160 and the 3rd bonding wire 170 of the foregoing description can be decided according to the quantity of the weld pad P on the chip 120, and the present invention does not limit its quantity.
In sum, the present invention utilizes B rank adhesion coating that lead frame is fixed on the circuit base plate, compared to the existing adhesive tape that utilizes lead frame is fixed on the circuit base plate, the process of configuration B rank adhesion coating comparatively saves time, and the price of B rank adhesion coating is cheap and its thickness is little than adhesive tape than adhesive tape, so can save manufacturing time, reduce manufacturing cost and reduce the thickness of chip-packaging structure.Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when the modification that can do some and perfect, thus protection scope of the present invention when with appending claims the person of being defined be as the criterion.
Claims (8)
1. chip-packaging structure comprises:
One circuit base plate;
One chip is disposed on this circuit base plate;
One B rank adhesion coating is disposed on this circuit base plate;
One lead frame is disposed on this circuit base plate, and wherein this lead frame comprises many pins, and the subregion of those pins is embedded in this B rank adhesion coating, and respectively an end of this pin is to be exposed to outside this B rank adhesion coating;
Many first bonding wires are electrically connected between this chip and this circuit base plate;
Many second bonding wires are electrically connected between the end of this chip and those pins; And
Many articles the 3rd bonding wires are electrically connected between the end and this circuit base plate of those pins.
2. chip-packaging structure as claimed in claim 1 is characterized in that, this B rank adhesion coating has a ring-shaped continuous pattern, and this B rank adhesion coating with this ring-shaped continuous pattern is around this chip, and the subregion of those pins is coated.
3. chip-packaging structure as claimed in claim 1 is characterized in that, this B rank adhesion coating has a plurality of discrete blockies, and tool respectively this B rank adhesion coating of this blocky coats the subregion of one of them pin respectively.
4. chip-packaging structure as claimed in claim 1 is characterized in that, this lead frame is the lead frame of a centreless bar.
5. chip-packaging structure as claimed in claim 1, it is characterized in that, more comprise a packing colloid, be disposed on this circuit base plate that wherein this packing colloid coats this chip, this B rank adhesion coating, this lead frame, those first bonding wires, those second bonding wires and those the 3rd bonding wires.
6. the manufacture method of a chip-packaging structure comprises:
On a circuit base plate, form a B rank adhesion coating, and see through this B rank adhesion coating one lead frame is fixed on this circuit base plate, wherein this lead frame comprises many pins, and the subregion of those pins is embedded in this B rank adhesion coating, and respectively an end of this pin is to be exposed to outside this B rank adhesion coating;
One chip is fixed on this circuit base plate;
Form many first bonding wires, so that this chip and this circuit base plate electrically connect;
Form many second bonding wires, so that the end of this chip and those pins electrically connects; And
Form many articles the 3rd bonding wires, so that the end of those pins and this circuit base plate electrically connect.
7. the manufacture method of chip-packaging structure as claimed in claim 6 is characterized in that, sees through this B rank adhesion coating the method that this lead frame is fixed on this circuit base plate is comprised:
On this circuit base plate, form a second order adhesion coating;
Make this second order adhesion coating B rankization, to form a B rank adhesion coating;
This lead frame is pressed in this B rank adhesion coating; And
With this B rank adhesion coating full solidification.
8. the manufacture method of chip-packaging structure as claimed in claim 6, it is characterized in that, more be included in and form a packing colloid on this circuit base plate, so that this packing colloid coats this chip, this B rank adhesion coating, this lead frame, those first bonding wires, those second bonding wires and those the 3rd bonding wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810186349.3A CN101752322A (en) | 2008-12-08 | 2008-12-08 | Chip packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810186349.3A CN101752322A (en) | 2008-12-08 | 2008-12-08 | Chip packaging structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101752322A true CN101752322A (en) | 2010-06-23 |
Family
ID=42479047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810186349.3A Pending CN101752322A (en) | 2008-12-08 | 2008-12-08 | Chip packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101752322A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103828041A (en) * | 2011-09-29 | 2014-05-28 | 夏普株式会社 | Semiconductor device |
-
2008
- 2008-12-08 CN CN200810186349.3A patent/CN101752322A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103828041A (en) * | 2011-09-29 | 2014-05-28 | 夏普株式会社 | Semiconductor device |
| CN103828041B (en) * | 2011-09-29 | 2016-07-06 | 夏普株式会社 | Semiconductor device |
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Open date: 20100623 |