CN101751341B - Non-volatile memory data management method and non-volatile memory device - Google Patents
Non-volatile memory data management method and non-volatile memory device Download PDFInfo
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- CN101751341B CN101751341B CN2008102072456A CN200810207245A CN101751341B CN 101751341 B CN101751341 B CN 101751341B CN 2008102072456 A CN2008102072456 A CN 2008102072456A CN 200810207245 A CN200810207245 A CN 200810207245A CN 101751341 B CN101751341 B CN 101751341B
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Abstract
The invention discloses a non-volatile memory data management method and a non-volatile memory device. The method comprises the following steps: receiving a first logical block address and updated information; and when the first logical block address is not in a comparison table in a buffer memory and a pairing number surpasses a preset number, integrating data of a plurality of entity blocks corresponding to a lowest utilization ratio parameter based on the lowest utilization ratio parameter in the comparison table.
Description
Technical field
The invention relates to nonvolatile memory, especially about the data management method of nonvolatile memory.
Background technology
Flash memory is a kind of nonvolatile memory, is development in recent years memory storage rapidly, can be applicable to such as on the portable memory devices such as SmartMedia card, CompactFlash card, PCMCIA ATA card.
Fig. 1 is the configuration diagram of flash memory device.Flash memory device 100 comprises a flash memory 110 and a controller 120, and wherein this controller 120 is in order to the transmission of control flash memory 110 and 130 data of a main frame.Wherein, flash memory 110 is a nonvolatile memory, can not cause data to be eliminated because of outage.Yet for the usefulness that makes data access between flash memory 110 and the main frame 130 promotes more, controller 120 often includes a memory buffer 122 again.Common memory buffer 122 is Synchronous Dynamic Random Access Memory (SynchronousDynamic Random Access Memory; Volatile memory such as SDRAM); Because the price of its per unit storage volume other storeies is relatively come expensively; Be with on manufacturing and designing,, needn't possess too high capacity usually as long as can reach the effect that promotes transmission usefulness.
The mode of carrying out access to flash memory 110 is summarized as follows: comprise the female block 1a～6a of a plurality of data etc. in the flash memory 110, in order to store the data that transmits from main frame 130.If main frame 130 tendencies to develop send new data A ' former when being stored in data A old among the female block 1a of this data to replace (data A ' correspond to identical blocks position with data A; This is a prior art; So do not give unnecessary details); Can be in the spare area of flash memory 110 select a new data sub-block 1b (be to have corresponding relation each other with data sub-block 1b, and close and claim that both are blocks 1), and new data A ' is stored in wherein with the female block 1a of title data.In like manner; When the female block 2a～6a of other data is upgraded; Also produce corresponding data sub-block 2b～6b; And again the data of blocks 1～6 is put in order also (merge) suitable opportunity and also unnecessary block is removed to disengage new space, this does not detail for existing skill event.
Fig. 2 A, 2B and 2C are the table of comparisons synoptic diagram in the memory buffer 122.The blocks 1～5 of the memory buffer 122 corresponding flash memories 110 in the controller 120 and have the table of comparisons 1 '～5 '; And each table of comparisons 1 '～5 ' comprises the relevant information 1a～5a of the female block of data and the relevant information 1b～5b of data sub-block respectively; For example physical blocks address, logical block addresses ... or the like, shown in Fig. 2 A.Yet; Because the finite capacity of memory buffer 122 has stored up data completely to be written, the data of continuing out when therebetween, and main frame 130 desires are when carrying out access to the blocks 6 of flash memory 110; Then need discharge the relevant information that blocks 6 is deposited in the space in the memory buffer 122, i.e. the table of comparisons 6 '.If according to prior art; Memory buffer 122 is taked first in first out (First In First Out; FIFO) data access mode (and supposing that the table of comparisons 1 '～5 ' successively is stored in the memory buffer 122 in regular turn), then the table of comparisons 1 ' of memory buffer 122 can be eliminated, and the blocks 1 in the flash memory 110 must be done the action of data conformity; Set up the table of comparisons 6 ' again, shown in 2B figure.If this moment, main frame 130 when desire is carried out access to the blocks in the flash memory 110 1 was again then removed the table of comparisons 2 ', the information data area 2 of arrangement flash memory 110, set up the table of comparisons 1 ' in memory buffer 122 once more, shown in 2C figure according to above-mentioned principle of identity.
It all is quite consuming time and the life-span of consume block that flash memory 110 is carried out reading of data compilation and write operation, and can be known by above-mentioned explanation, the unnecessary waste in the time of obviously can causing access of the method for prior art.For the access usefulness that makes flash memory promotes more, it is very necessary designing a kind of new data management method.
Summary of the invention
The present invention has disclosed a kind of non-volatile memory data management method, comprising: receive one first logical block addresses and a data for updating; And the comparison list and the pairing number that are not present in the memory buffer when this first logical block addresses surpass a predetermined number; Then according to the minimum utilization rate parameter in this table of comparisons, the data in the whole and pairing a plurality of physical blocks of this minimum utilization rate parameter.
The present invention has also disclosed a kind of non-volatile memory device, comprises a nonvolatile memory and a controller.Wherein this nonvolatile memory comprises a plurality of entity stores blocks; This controller is electrically connected on this volatile memory; In order to receive one first logical block addresses and a data for updating; This controller more comprises an impact damper, and in order to store this data for updating and comparison list, this table of comparisons and the pairing number that are not present in this impact damper when this first logical block addresses surpass a predetermined number; Then according to the minimum utilization rate parameter in this table of comparisons, the data in whole and pairing these physical blocks of this minimum utilization rate parameter.
The present invention has also disclosed a kind of non-volatile memory data management method, comprises receiving one first logical block addresses and a data for updating; And the comparison list and the pairing number that are not present in the memory buffer when this first logical block addresses surpass a predetermined number; Then, remove the relevant information of pairing one second logical block addresses of this minimum utilization rate parameter according to the minimum utilization rate parameter in this table of comparisons.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
Fig. 1 is the configuration diagram of flash memory device;
Fig. 2 A, 2B and 2C are the synoptic diagram of the table of comparisons in the memory buffer;
Fig. 3 is for accordinging to flash memory data management method process flow diagram of the present invention;
Fig. 4 A is the synoptic diagram of the table of comparisons in the memory buffer;
Fig. 4 B is the synoptic diagram of the table of comparisons in the memory buffer.
The main element symbol description:
100～quick flashing memory device, 110～flash memory, 120～controller, 122～memory buffer; 130～main frame, 1～5～blocks, 1 '～5 '～table of comparisons, the female block of 1a～5a～entity; 1b～5b～entity sub-block, the female block of 1a '～5a '～entity, 1b '～5b '～entity sub-block; A～data, A '～data, S302～S320～step.
Embodiment
Preamble has been done the summary of each characteristic to the present invention, please refer to this paper and accompanying drawing, will do more detailed description in this.Conjunction with figs. of the present invention is done detailed description, yet non-in order to restriction the present invention.Opposite, in the scope and the spirit that do not break away from the appending claims to be defined, the present invention is when change and the retouching that can do all patterns.
Fig. 3 is the flash memory data management method process flow diagram according to one embodiment of the invention.Fig. 4 A and 4B are the table of comparisons synoptic diagram of memory buffer 122 among the present invention.Flash memory data management method of the present invention is performed by controller as shown in Figure 1 120, below will be with reference to the 1st, 3,4A and 4B figure explanation technology of the present invention.Flash memory device 100 of the present invention comprises a flash memory 110 and a controller 120, and wherein this controller 120 is in order to the transmission of control flash memory 110 and 130 data of a main frame, and carries out data management method of the present invention.Wherein, Flash memory 110 has a plurality of blocks 1～6 and wherein comprises the female block 1a～6a of entity and entity sub-block 1b～6b; Then have the corresponding a plurality of blocks 1～5 of the table of comparisons 1 '～5 ' in the memory buffer 122; And the table of comparisons 1 '～5 ' comprises relevant information the 1a '～5a ' of female block and relevant information the 1b '～5b ' of sub-block respectively, for example physical blocks address, logical block addresses ... or the like.In addition, the table of comparisons 1 '～5 ' more comprises utilization rate parameter (for example can be the access times of each logical block addresses).In the present embodiment, physical blocks 1a and 1b have common logical block addresses and the access times of this logical block addresses are 50; Physical blocks 2a and 2b have common logical block addresses and the access times of this logical block addresses are 42; Physical blocks 3a and 3b have common logical block addresses and the access times of this logical block addresses are 10; Physical blocks 4a and 4b have common logical block addresses and the access times of this logical block addresses are 33 and physical blocks 5a and 5b has common logical block addresses and the access times of this logical block addresses are 36 times, shown in Fig. 4 A.In addition, be convenient explanation, memory buffer 122 only can store 5 pairing numbers (being that the table of comparisons 1 '～5 ' has 5 groups) in the present embodiment, needn't be as limit yet match number in other embodiments.
Non-volatile memory data management method of the present invention comprises step S302～S318.In step S302, a logical block addresses and a data for updating that flash memory device 100 receives from main frame 130 are in order to upgrade the data of blocks 6 in the flash memory 110.In step S304, when access command and the desire of receiving main frame 130 when controller 120 carried out access to the blocks 6 of flash memory 110, whether there are this blocks 6 pairing logical block addresses in the table of comparisons in this memory buffer 122 of inspection earlier.Yet, shown in Fig. 4 A, do not have the related data of blocks 6 in the table of comparisons.Therefore, carry out step S308, whether the pairing number of inspection memory buffer 122 has reached the upper limit.Likewise, shown in Fig. 4 A, the pairing number of memory buffer 122 has reached 5 groups the upper limit at this moment, therefore must memory buffer 122 be removed the relevant information of segment space with stored logic block 6.In step S314, controller 120 is put in order also (merge) according to the minimum utilization rate parameter in the table of comparisons with the blocks in the flash memory 110 3 (comprising female block 3a ' of entity and entity sub-block 3b ').The relevant information that in step S316, will have the blocks 3 of minimum utilization rate parameter (access times only 10 times) is again removed, and promptly is that the table of comparisons 3a ' with minimum utilization rate parameter is removed to disengage the space.In step S318; Controller 120 can write down the relevant information of the table of comparisons 6 ' (corresponding to above-mentioned blocks 6) in this table of comparisons, wherein relevant information comprises the physical blocks address of female block 6a ', physical blocks address and the utilization rate parameter of sub-block 6b '.At last, in step S320, above-mentioned data for updating is write among the physical blocks 6b ' of flash memory 110.At this moment, corresponding utilization rate parameter is 2 in the table of comparisons.
In other embodiments; Logical block addresses that quick flashing memory device 100 is received and data for updating are when corresponding to the blocks 1 of flash memory 110; Because in the memory buffer 122 during the table of comparisons 1 ' of existing and blocks 1; Then shown in step S306 of the present invention, directly the physical blocks 1b ' with data for updating write buffering memory 122 gets final product.At this moment, should increase by 1 and be 51 (figure does not show) about the utilization rate parameter of blocks 1 in the table of comparisons 1 '.
In addition; In another embodiment; In the middle of logical block addresses that this quick flashing memory device 100 is received and data for updating are not present in this memory buffer 122; And the pairing number in the memory buffer 122 does not reach a predetermined number (number that for example matches has only 4 groups) yet and when still remaining space being arranged, then shown in step S310 of the present invention, directly in the table of comparisons, sets up the relevant information of this logical block addresses; And in step S312, data for updating write in the corresponding physical blocks of this logical block addresses get final product.
Embodiment of the present invention flash memory management document method will help controller 120 to judge the use situation of each blocks 1～5; For the high blocks of historical access times; It is also high by the possibility of access backward in deducibility; Then should hold it in as much as possible within the memory buffer 122, to decrease in the life-span that data is put in order time waste also and reduced consumption flash memory 110 in the flash memory 110; Otherwise, for the low blocks of historical access times, then can be as preferentially being put in order object also.By the present invention, the efficient of flash memory management data will be able to promote.
Claims (8)
1. non-volatile memory data management method comprises:
Receive one first logical block addresses and a data for updating; And
A pairing number that is not present in comparison list and this memory buffer in the memory buffer when this first logical block addresses surpasses a predetermined number; Then according to the minimum utilization rate parameter in this table of comparisons; Data in the whole and pairing a plurality of physical blocks of this minimum utilization rate parameter; Remove the relevant information of pairing one second logical block addresses of this minimum utilization rate parameter; In this table of comparisons, set up the relevant information of this first logical block addresses, and this data for updating is written in the corresponding physical blocks of this first logical block addresses
Wherein this pairing number is meant the number of the matched group information of female block of the entity with common logical block addresses and entity sub-block.
2. non-volatile memory data management method as claimed in claim 1 is characterized in that, more comprises:
When this first logical block addresses has been present in this memory buffer, then this data for updating is written in the corresponding physical blocks of this first logical block addresses.
3. non-volatile memory data management method as claimed in claim 1 is characterized in that, more comprises:
The comparison list and this pairing number that are not present in this memory buffer when this first logical block addresses do not surpass this predetermined number, then in this table of comparisons, set up the relevant information of this first logical block addresses.
4. non-volatile memory data management method as claimed in claim 3 is characterized in that, this relevant information comprises the physical blocks address and the corresponding utilization rate parameter of this logical block addresses of at least one block.
5. non-volatile memory data management system comprises:
In order to receive the device of one first logical block addresses and a data for updating;
Pairing number in order to not to be present in comparison list and this memory buffer in the memory buffer when this first logical block addresses surpasses a predetermined number; Then according to the minimum utilization rate parameter in this table of comparisons, the device of the data in the whole and pairing a plurality of physical blocks of this minimum utilization rate parameter;
Device in order to the relevant information of removing pairing one second logical block addresses of this minimum utilization rate parameter;
Be used to set up in this table of comparisons the device of the relevant information of this first logical block addresses; And
In order to this data for updating is written into the device in the corresponding physical blocks of this first logical block addresses;
Wherein this pairing number is meant the number of the matched group information of female block of the entity with common logical block addresses and entity sub-block.
6. non-volatile memory data management system as claimed in claim 5; It is characterized in that; Also comprise:, this data for updating is written into the device in the corresponding physical blocks of this first logical block addresses in order to be present in this impact damper when this first logical block addresses.
7. non-volatile memory data management system as claimed in claim 5; It is characterized in that; Also comprise: comparison list and this pairing number in order to not to be present in when this first logical block addresses in this impact damper do not surpass this predetermined number, in this table of comparisons, set up the device of the relevant information of this first logical block addresses.
8. non-volatile memory data management system as claimed in claim 7 is characterized in that, this relevant information comprises the physical blocks address and the corresponding utilization rate parameter of this logical block addresses of at least one block.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6490665B1 (en) * | 1999-03-05 | 2002-12-03 | Via Technologies, Inc. | Memory-access management method and system for synchronous random-access memory or the like |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6490665B1 (en) * | 1999-03-05 | 2002-12-03 | Via Technologies, Inc. | Memory-access management method and system for synchronous random-access memory or the like |
Non-Patent Citations (3)
| Title |
|---|
| JP特开2005-209058A 2005.08.04 |
| JP特开2008-165585A 2008.07.17 |
| JP特开平6-59982A 1994.03.04 |
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