CN101751341A - Non-volatile memory data management method and non-volatile memory device - Google Patents
Non-volatile memory data management method and non-volatile memory device Download PDFInfo
- Publication number
- CN101751341A CN101751341A CN200810207245A CN200810207245A CN101751341A CN 101751341 A CN101751341 A CN 101751341A CN 200810207245 A CN200810207245 A CN 200810207245A CN 200810207245 A CN200810207245 A CN 200810207245A CN 101751341 A CN101751341 A CN 101751341A
- Authority
- CN
- China
- Prior art keywords
- logical block
- block addresses
- volatile memory
- data
- comparisons
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
Abstract
The invention discloses a non-volatile memory data management method and a non-volatile memory device. The method comprises the following steps: receiving a first logical block address and updated information; and when the first logical block address is not in a comparison table in a buffer memory and a pairing number surpasses a preset number, integrating data of a plurality of entity blocks corresponding to a lowest utilization ratio parameter based on the lowest utilization ratio parameter in the comparison table.
Description
Technical field
The invention relates to nonvolatile memory, especially about the data management method of nonvolatile memory.
Background technology
Flash memory is a kind of nonvolatile memory, is development in recent years memory storage rapidly, can be applicable to such as on the portable memory devices such as SmartMedia card, CompactFlash card, PCMCIA ATA card.
Fig. 1 is the configuration diagram of flash memory device.Flash memory device 100 comprises a flash memory 110 and a controller 120, and wherein this controller 120 is in order to the transmission of control flash memory 110 and 130 data of a main frame.Wherein, flash memory 110 is a nonvolatile memory, can not cause data to be eliminated because of outage.Yet for the usefulness that makes data access between flash memory 110 and the main frame 130 promotes more, controller 120 often includes a memory buffer 122 again.Common memory buffer 122 is Synchronous Dynamic Random Access Memory (SynchronousDynamic Random Access Memory, volatile memory such as SDRAM), because the price of its per unit storage volume other storeies is relatively come expensively, be with on manufacturing and designing, as long as can reach the effect that promotes transmission usefulness, needn't possess too high capacity usually.
The mode of carrying out access to flash memory 110 is summarized as follows: comprise the female block 1a～6a of a plurality of data etc. in the flash memory 110, in order to store the data that transmits from main frame 130.If main frame 130 tendencies to develop send new data A ' former when being stored in data A old among the female block 1a of this data to replace (data A ' correspond to identical logical blocks position with data A, this is a prior art, so do not give unnecessary details), can select a new data sub-block 1b in the spare area of flash memory 110 (is to have corresponding relation each other with female block 1a of title data and data sub-block 1b, and be collectively referred to as both for logical blocks 1), and new data A ' is stored in wherein.In like manner, when the female block 2a～6a of other data is upgraded, also produce corresponding data sub-block 2b～6b, and again the data of logical blocks 1～6 is put in order also (merge) suitable opportunity and also unnecessary block is removed to disengage new space, this does not describe in detail for existing skill event.
Fig. 2 A, 2B and 2C are the table of comparisons synoptic diagram in the memory buffer 122.The logical blocks 1～5 of the memory buffer 122 corresponding flash memories 110 in the controller 120 and have the table of comparisons 1 '～5 ', and each table of comparisons 1 '～5 ' comprises the relevant information 1a～5a of the female block of data and the relevant information 1b～5b of data sub-block respectively, for example physical blocks address, logical block addresses ... or the like, shown in Fig. 2 A.Yet, because the finite capacity of memory buffer 122 has stored up data completely to be written, the data of continuing out when therebetween, and main frame 130 desires are when carrying out access to the logical blocks 6 of flash memory 110, then need discharge the relevant information that logical blocks 6 is deposited in the space in the memory buffer 122, i.e. the table of comparisons 6 '.If according to prior art, memory buffer 122 is taked first in first out (First In First Out, FIFO) data access mode (and supposing that the table of comparisons 1 '～5 ' successively is stored in the memory buffer 122 in regular turn), then the table of comparisons 1 ' of memory buffer 122 can be eliminated, and the logical blocks 1 in the flash memory 110 must be done the action of data conformity, set up the table of comparisons 6 ' again, shown in 2B figure.If this moment, main frame 130 when desire is carried out access to the logical blocks in the flash memory 110 1 was again then removed the table of comparisons 2 ', the information data area 2 of arrangement flash memory 110, set up the table of comparisons 1 ' in memory buffer 122, shown in 2C figure once more according to above-mentioned principle of identity.
It all is quite consuming time and the life-span of consume block that flash memory 110 is carried out reading of data compilation and write operation, and as shown in the above description, the unnecessary waste in the time of obviously can causing access of the method for prior art.For the access usefulness that makes flash memory promotes more, it is very necessary designing a kind of new data management method.
Summary of the invention
The present invention has disclosed a kind of non-volatile memory data management method, comprising: receive one first logical block addresses and a data for updating; And the comparison list and the pairing number that are not present in the memory buffer when this first logical block addresses surpass a predetermined number, then according to the minimum utilization rate parameter in this table of comparisons, the data in the whole and pairing a plurality of physical blocks of this minimum utilization rate parameter.
The present invention has also disclosed a kind of non-volatile memory device, comprises a nonvolatile memory and a controller.Wherein this nonvolatile memory comprises a plurality of entity stores blocks; This controller is electrically connected on this volatile memory, in order to receive one first logical block addresses and a data for updating, this controller more comprises an impact damper, in order to store this data for updating and comparison list, this table of comparisons and the pairing number that are not present in this impact damper when this first logical block addresses surpass a predetermined number, then according to the minimum utilization rate parameter in this table of comparisons, the data in whole and pairing these physical blocks of this minimum utilization rate parameter.
The present invention has also disclosed a kind of non-volatile memory data management method, comprises receiving one first logical block addresses and a data for updating; And the comparison list and the pairing number that are not present in the memory buffer when this first logical block addresses surpass a predetermined number, then, remove the relevant information of pairing one second logical block addresses of this minimum utilization rate parameter according to the minimum utilization rate parameter in this table of comparisons.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 is the configuration diagram of flash memory device;
Fig. 2 A, 2B and 2C are the synoptic diagram of the table of comparisons in the memory buffer;
Fig. 3 is according to flash memory data management method process flow diagram of the present invention;
Fig. 4 A is the synoptic diagram of the table of comparisons in the memory buffer;
Fig. 4 B is the synoptic diagram of the table of comparisons in the memory buffer.
The main element symbol description:
100～quick flashing memory device, 110～flash memory, 120～controller, 122～memory buffer, 130～main frame, 1～5～logical blocks, 1 '～5 '～table of comparisons, the female block of 1a～5a～entity, 1b～5b～entity sub-block, the female block of 1a '～5a '～entity, 1b '～5b '～entity sub-block, A～data, A '～data, S302～S320～step.
Embodiment
Preamble has been done the summary of each feature to the present invention, please refer to this paper and accompanying drawing, will do more detailed description in this.Conjunction with figs. of the present invention is done detailed description, yet non-in order to restriction the present invention.Opposite, in the scope and the spirit that do not break away from the appending claims to be defined, the present invention is when change and the retouching that can do all patterns.
Fig. 3 is the flash memory data management method process flow diagram according to one embodiment of the invention.Fig. 4 A and 4B are the table of comparisons synoptic diagram of memory buffer 122 among the present invention.Flash memory data management method of the present invention is performed by controller 120 as shown in Figure 1, hereinafter with reference to the 1st, 3,4A and 4B figure explanation technology of the present invention.Flash memory device 100 of the present invention comprises a flash memory 110 and a controller 120, and wherein this controller 120 is in order to the transmission of control flash memory 110 and 130 data of a main frame, and carries out data management method of the present invention.Wherein, flash memory 110 has a plurality of logical blocks 1～6 and wherein comprises the female block 1a～6a of entity and entity sub-block 1b～6b, then have the corresponding a plurality of logical blocks 1～5 of the table of comparisons 1 '～5 ' in the memory buffer 122, and the table of comparisons 1 '～5 ' comprises relevant information the 1a '～5a ' of female block and relevant information the 1b '～5b ' of sub-block respectively, for example physical blocks address, logical block addresses ... or the like.In addition, the table of comparisons 1 '～5 ' more comprises utilization rate parameter (for example can be the access times of each logical block addresses).In the present embodiment, physical blocks 1a and 1b have common logical block addresses and the access times of this logical block addresses are 50; Physical blocks 2a and 2b have common logical block addresses and the access times of this logical block addresses are 42; Physical blocks 3a and 3b have common logical block addresses and the access times of this logical block addresses are 10; Physical blocks 4a and 4b have common logical block addresses and the access times of this logical block addresses are 33 and physical blocks 5a and 5b has common logical block addresses and the access times of this logical block addresses are 36 times, shown in Fig. 4 A.In addition, for convenience of description, memory buffer 122 only can store 5 pairing numbers (being that the table of comparisons 1 '～5 ' has 5 groups) in the present embodiment, needn't be as limit yet match number in other embodiments.
Non-volatile memory data management method of the present invention comprises step S302～S318.In step S302, a logical block addresses and a data for updating that flash memory device 100 receives from main frame 130 are in order to upgrade the data of logical blocks 6 in the flash memory 110.In step S304, receive the access command of main frame 130 and desire when the logical blocks 6 of flash memory 110 is carried out access when controller 120, check in the table of comparisons in this memory buffer 122 whether have this logical blocks 6 pairing logical block addresses earlier.Yet, shown in Fig. 4 A, there is no the related data of logical blocks 6 in the table of comparisons.Therefore, carry out step S308, check whether the pairing number of memory buffer 122 has reached the upper limit.Similarly, shown in Fig. 4 A, the pairing number of memory buffer 122 has reached 5 groups the upper limit at this moment, therefore memory buffer 122 must be removed the relevant information of segment space with stored logic block 6.In step S314, controller 120 is put in order also (merge) according to the minimum utilization rate parameter in the table of comparisons with the logical blocks in the flash memory 110 3 (comprising female block 3a ' of entity and entity sub-block 3b ').The relevant information that will have the logical blocks 3 of minimum utilization rate parameter (access times only 10 times) again in step S316 is removed, and promptly is that the table of comparisons 3a ' that will have minimum utilization rate parameter is removed to disengage the space.In step S318, controller 120 can write down the relevant information of the table of comparisons 6 ' (corresponding to above-mentioned logical blocks 6) in this table of comparisons, wherein relevant information comprises the physical blocks address of female block 6a ', physical blocks address and the utilization rate parameter of sub-block 6b '.At last, in step S320, above-mentioned data for updating is write among the physical blocks 6b ' of flash memory 110.At this moment, corresponding utilization rate parameter is 2 in the table of comparisons.
In other embodiments, logical block addresses that quick flashing memory device 100 is received and data for updating are when corresponding to the logical blocks 1 of flash memory 110, because in the memory buffer 122 during the table of comparisons 1 ' of existing and logical blocks 1, then shown in step S306 of the present invention, directly the physical blocks 1b ' with data for updating write buffering memory 122 gets final product.At this moment, should increase by 1 and be 51 (figure does not show) about the utilization rate parameter of logical blocks 1 in the table of comparisons 1 '.
In addition, in another embodiment, in the middle of logical block addresses that this quick flashing memory device 100 is received and data for updating are not present in this memory buffer 122, and the pairing number in the memory buffer 122 does not reach a predetermined number (number that for example matches has only 4 groups) and when still remaining space being arranged yet, then shown in step S310 of the present invention, directly in the table of comparisons, set up the relevant information of this logical block addresses, and in step S312, data for updating is write in the physical blocks of this logical block addresses correspondence and get final product.
Implementing flash memory management document method of the present invention will help controller 120 to judge the use situation of each logical blocks 1～5, for the high logical blocks of historical access times, it is also high by the possibility of access backward in deducibility, then should hold it in as much as possible within the memory buffer 122, to decrease in the life-span that data is put in order time waste also and reduced consumption flash memory 110 in the flash memory 110; Otherwise, for the low logical blocks of historical access times, then can be as preferentially being put in order object also.By the present invention, the efficient of flash memory management data will be promoted.
Claims (15)
1. non-volatile memory data management method comprises:
Receive one first logical block addresses and a data for updating; And
The comparison list and the pairing number that are not present in the memory buffer when this first logical block addresses surpass a predetermined number, then according to the minimum utilization rate parameter in this table of comparisons, the data in the whole and pairing a plurality of physical blocks of this minimum utilization rate parameter.
2. non-volatile memory data management method as claimed in claim 1 is characterized in that, more comprises:
When this first logical block addresses has been present in this memory buffer, then this data for updating is written in the physical blocks of this first logical block addresses correspondence.
3. non-volatile memory data management method as claimed in claim 1 is characterized in that, more comprises:
When this first logical block addresses is not present in this memory buffer and this pairing number surpasses this predetermined number, then in this table of comparisons, set up the relevant information of this first logical block addresses.
4. non-volatile memory data management method as claimed in claim 3 is characterized in that, this relevant information comprises the physical blocks address of at least one block and the utilization rate parameter of this logical block addresses correspondence.
5. non-volatile memory data management method as claimed in claim 1 is characterized in that, more comprises:
Remove the relevant information of pairing one second logical block addresses of this minimum utilization rate parameter;
In this table of comparisons, set up the relevant information of this first logical block addresses; And
This data for updating is written in the physical blocks of this first logical block addresses correspondence.
6. non-volatile memory device comprises:
One nonvolatile memory comprises a plurality of entity stores blocks; And
One controller is electrically connected on this volatile memory, in order to receive one first logical block addresses and a data for updating, this controller more comprises an impact damper, in order to store this data for updating and comparison list, this table of comparisons and the pairing number that are not present in this impact damper when this first logical block addresses surpass a predetermined number, then according to the minimum utilization rate parameter in this table of comparisons, the data in whole and pairing these physical blocks of this minimum utilization rate parameter.
7. non-volatile memory device as claimed in claim 6 is characterized in that, when this first logical block addresses is present in this impact damper, this controller is written into this data for updating in this physical blocks of this first logical block addresses correspondence.
8. non-volatile memory device as claimed in claim 6, it is characterized in that, when this first logical block addresses is not present in this impact damper and this pairing number surpasses this predetermined number, this controller is set up the relevant information of this first logical block addresses in this table of comparisons.
9. non-volatile memory device as claimed in claim 8 is characterized in that, this relevant information comprises the physical blocks address of at least one block and the utilization rate parameter of this logical block addresses correspondence.
10. non-volatile memory device as claimed in claim 6, it is characterized in that, this controller is further removed the relevant information of pairing one second logical block addresses of this minimum utilization rate parameter, sets up the relevant information of this first logical block addresses and this data for updating is written in this physical blocks of this first logical block addresses correspondence in this table of comparisons.
11. a non-volatile memory data management method comprises:
Receive one first logical block addresses and a data for updating; And
The comparison list and the pairing number that are not present in the memory buffer when this first logical block addresses surpass a predetermined number, then, remove the relevant information of pairing one second logical block addresses of this minimum utilization rate parameter according to the minimum utilization rate parameter in this table of comparisons.
12. non-volatile memory data management method as claimed in claim 11 is characterized in that, more comprises:
When this first logical block addresses is present in this memory buffer, then this data for updating is written in the physical blocks of this first logical block addresses correspondence.
13. non-volatile memory data management method as claimed in claim 11 is characterized in that, more comprises:
When this first logical block addresses is not present in this memory buffer and this pairing number surpasses this predetermined number, then in this table of comparisons, set up the relevant information of this first logical block addresses.
14. non-volatile memory data management method as claimed in claim 13 is characterized in that, this relevant information comprises the physical blocks address of at least one block and the utilization rate parameter of this logical block addresses correspondence.
15. non-volatile memory data management method as claimed in claim 11 is characterized in that, more comprises:
Data in whole and pairing these physical blocks of this minimum utilization rate parameter;
In this table of comparisons, set up the relevant information of this first logical block addresses; And
This data for updating is written in the physical blocks of this first logical block addresses correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102072456A CN101751341B (en) | 2008-12-18 | 2008-12-18 | Non-volatile memory data management method and non-volatile memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102072456A CN101751341B (en) | 2008-12-18 | 2008-12-18 | Non-volatile memory data management method and non-volatile memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101751341A true CN101751341A (en) | 2010-06-23 |
| CN101751341B CN101751341B (en) | 2012-05-23 |
Family
ID=42478346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008102072456A Active CN101751341B (en) | 2008-12-18 | 2008-12-18 | Non-volatile memory data management method and non-volatile memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101751341B (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW416032B (en) * | 1999-03-05 | 2000-12-21 | Via Tech Inc | Memory pages management device and method for tracking memory access |
-
2008
- 2008-12-18 CN CN2008102072456A patent/CN101751341B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101751341B (en) | 2012-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8386698B2 (en) | Data accessing method for flash memory and storage system and controller using the same | |
| KR100816761B1 (en) | Memory card system including nand flash memory and sram/nor flash memory and data storage method thereof | |
| CN100573476C (en) | Flash memory medium data management method | |
| US8583860B2 (en) | Block management method for flash memory and controller and storage system using the same | |
| US7516296B2 (en) | Flash memory storage device and read/write method | |
| US20070214309A1 (en) | Nonvolatile storage device and data writing method thereof | |
| US20100042774A1 (en) | Block management method for flash memory, and storage system and controller using the same | |
| US20100057979A1 (en) | Data transmission method for flash memory and flash memory storage system and controller using the same | |
| KR20110006607A (en) | Memory system and information processing device | |
| CN101625897B (en) | Data write-in method, storage system and controller used for quick flash memory | |
| CN101556555B (en) | Block managing method for flash memory as well as controller and storage system thereof | |
| US9389998B2 (en) | Memory formatting method, memory controller, and memory storage apparatus | |
| US8037236B2 (en) | Flash memory writing method and storage system and controller using the same | |
| US8074128B2 (en) | Block management and replacement method, flash memory storage system and controller using the same | |
| CN101446922B (en) | Memory card and method for handling data updating of a flash memory | |
| CN107943710B (en) | Memory management method and memory controller using the same | |
| CN101661431B (en) | Block management method for flash memory, flash storage system and controller | |
| US20090210612A1 (en) | Memory controller, nonvolatile memory device, and nonvolatile memory system | |
| CN103309619A (en) | NAND Flash memory data storage method | |
| CN103389941B (en) | Storer formatting method, Memory Controller and memory storage apparatus | |
| CN105988950A (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN103218300B (en) | Data processing method, Memory Controller and memorizer memory devices | |
| US8209464B2 (en) | Management method, management apparatus, and controller for memory data access | |
| US20150046632A1 (en) | Memory address management method, memory controller and memory storage device | |
| CN101566969B (en) | Method and controller capable of enhancing management efficiency of nonvolatile storage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |