CN101751239A - High-speed floating point normalized arithmetic device - Google Patents
High-speed floating point normalized arithmetic device Download PDFInfo
- Publication number
- CN101751239A CN101751239A CN200910254638A CN200910254638A CN101751239A CN 101751239 A CN101751239 A CN 101751239A CN 200910254638 A CN200910254638 A CN 200910254638A CN 200910254638 A CN200910254638 A CN 200910254638A CN 101751239 A CN101751239 A CN 101751239A
- Authority
- CN
- China
- Prior art keywords
- leading zero
- shift unit
- result
- shift
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a high-speed floating point normalized arithmetic device which is used for solving the technical problem that the current normalized arithmetic device has a low arithmetic speed. The invention has the technical scheme that a leading zero detecting component is additionally provided with a primary OR array; shifters comprise a first shifter and a second shifter; the primary OR array generates first-stage shift signals; the first shifter shifts the unnormalized numbers according to the first-stage shift signals; and after the execution of the first shifter is finished, the result of the first shifter and second-stage shift signals are input into the second shifter to execute the shift operation. As the primary OR array is additionally arranged in the leading zero detecting component, partial shift signals are generated quickly, and the execution of the shifters is started as quickly as possible. Meanwhile, a divisional leading zero detecting component and a low-order leading zero signal generator generate other shift signals to enable the shifters to execute the shift operation continuously, thereby maximizing the parallel execution of leading zero detection and shift operation and improving the speed of floating point normalized operation.
Description
Technical field
The present invention relates to a kind of floating point calculator, particularly high-speed floating point normalized arithmetic device.
Background technology
Floating-point operation is a critical function of processor, and the floating-point operation ability of a processor usually is to weigh the important indicator of a processor performance.Floating-point operation is generally followed the IEEE754 standard, and floating-point format is a kind of normalized expression mode in this standard, and promptly the most significant digit of floating-point coefficient is 1.It is the operation that floating-point operation must have that floating number is carried out normalization operation, usually be used for floating-point operation before, be called prenormalization, after perhaps floating-point operation finishes, be called postnormalization or normalization.The normalized arithmetic device of floating number usually is on the critical path of each floating-point operation arithmetic, and the floating-point operation performance is had important effect.
With reference to Fig. 6.Document 1 " An algorithmic and novel design of a leading zero detector circuit:comparison with logic synthesis; Vojin G.Oklobdzija; IEEE Transaction on Very Large ScaleIntegration (VLSI) Systems; Vol.2; No.1; 1993, pp.124-128 " discloses a kind of normalized arithmetic device that detects based on leading zero, comprises leading zero detection part and shift unit.The leading zero detection part calculates the leading zero number of unnormalized number, and shift unit carries out moving to left of respective number according to the number of leading zero to unnormalized number, with the implementation specification operation.This normalized arithmetic device that detects based on leading zero need detect at leading zero could start shifting function after finishing, so the total time delay of document 1 described normalized arithmetic device adds shift time computing time for leading zero.
With reference to Fig. 7.Document 2 " Leading Zero Anticipation and Detection-A Comparison of Methods ", Martin S.Schmookler and Kevin J.Nowka, Proc.of the 15th IEEE Symposium on ComputerArihmetic, 2001, pp.7-12 " a kind of normalized arithmetic device based on leading zero prediction disclosed; comprise the leading zero sequence generator, leading zero detection part and shift unit.The leading zero sequence generator is to the redundant representation form of unnormalized number, as the form of preserving with the carry value and the retention of unnormalized number, generation and unnormalized number have the sequence of same preamble zero number, the leading zero detection part carries out the calculating of leading zero number to this sequence then, uses shift unit to finish normalization operation at last.This normalized arithmetic device based on the leading zero prediction can move simultaneously with the floating-point operation arithmetic parts, when the floating-point operation arithmetic parts obtain unnormalized number to the carry value of unnormalized number and retention addition, obtain the number of leading zero, the time of leading zero detection and the execution time of arithmetic unit are overlapped, thereby reduced the time delay on the critical path.But in this structure, leading zero detects and the execution of shift unit still is the serial execution sequence.
Summary of the invention
Prior art detects leading zero in normalization operation and the shifting function serial is carried out in order to overcome, cause the low deficiency of normalization operations speed, the invention provides a kind of high-speed floating point normalized arithmetic device, by leading zero being detected and shift unit executed in parallel substantially, can improve normalization operations speed.
The technical solution adopted for the present invention to solve the technical problems: a kind of high-speed floating point normalized arithmetic device, comprise leading zero detection part and shift unit, be characterized in that described leading zero detection part comprises elementary or array, subregion leading zero detection part, low level leading zero signal generator and high-order leading zero signal generator; Subregion leading zero detection part carries out leading zero to the zones of different of unnormalized number and detects; Elementary or array carries out the logical OR operation to the zones of different of unnormalized number, produces the phase one shift signal; Described shift unit comprises first shift unit and second shift unit, and first shift unit is shifted to unnormalized number according to the phase one shift signal; Low level leading zero signal generator generates the subordinate phase shift signal according to the result of subregion leading zero detection part and the result of elementary or array; After first shift unit executes, the result and the subordinate phase shift signal of first shift unit are imported second shift unit, carry out shifting function; The result of second shift unit is exactly a normalized result; Simultaneously, high-order leading zero signal generator generates leading zero result's a high position according to the result of elementary or array, and the result with low level leading zero signal generator is spliced into the leading zero testing result then.
The invention has the beneficial effects as follows:, generated the transposition of partial signal fast, thereby started the execution of shift unit as soon as possible owing in the leading zero detection part, increased elementary or array.When shift unit is carried out, use subregion leading zero detection part and low level leading zero signal generator to generate other shift signal, behind the end-of-shift of phase one, make shift unit can continue to carry out shifting function.Thereby maximized the executed in parallel of leading zero detection and shifting function, improved the speed of floating point normalized operation.
Below in conjunction with drawings and Examples the present invention is elaborated.
Description of drawings
Fig. 1 is a high-speed floating point normalized arithmetic device structured flowchart of the present invention.
Fig. 2 is the high-speed floating point normalized arithmetic device inner structure detail drawing of the embodiment of the invention.
Fig. 3 is an elementary or array structure detail drawing among Fig. 2.
Fig. 4 is a low level leading zero signal generator detail of construction among Fig. 2.
Fig. 5 is a high-order leading zero signal generator detail of construction among Fig. 2.
Fig. 6 is the normalized arithmetic device structured flowchart based on the leading zero detection of document 1.
Fig. 7 is the normalized arithmetic device structured flowchart based on the leading zero prediction of document 2.
Embodiment
With reference to Fig. 1～5, the double-precision floating point of IEEE754 standard has 53 mantissa, in computing, in order to prevent overflow, needs to increase an integer-bit.Simultaneously, according to the IEEE754 standard, also need a warning position, a rounding bit and a sticky position.Need so altogether 57 intermediate operations results are carried out normalization operations.Therefore, present embodiment carries out normalization operations to 57 input, also exports the leading zero testing result simultaneously.Below these 57 inputs are called unnormalized number.
The embodiment of the invention comprises a leading zero detection part and a shift unit.Wherein, the leading zero detection part comprises an elementary or array, the first subregion leading zero detection part, the second subregion leading zero detection part, the 3rd subregion leading zero detection part, the 4th subregion leading zero detection part, a low level leading zero signal generator that generates four results of high-order leading zero signal generator that generates two results; Shift unit comprises first shift unit of three grades of displacements, second shift unit with a level Four displacement, first shift unit is made up of three grades of shifting parts of 16 of moving to left, second shift unit is by the 8 bit shift parts that move to left, 4 bit shift parts move to left, the 2 bit shift parts that move to left, the 1 bit shift parts that move to left are formed.
The execution that the present invention detects logic and shift unit with the leading zero parallelization of trying one's best.
The workflow of high-speed floating point normalized arithmetic device is: the execution of boot partition leading zero detection part and elementary or array simultaneously.Elementary or array is at first to the 0-15 position of unnormalized number, the 16-31 position, and the logical OR computing is carried out in the 32-47 position, 16 the operation that moves to left of wherein the 0-15 position or that the result produces first shift unit first order control signal that moves to left, the first order that starts first shift unit.When first shift unit was done first order displacement, elementary or array carried out logical OR with the 0-15 position or result and 16-31 position or result then, produced the second level control signal that moves to left.With the 32-47 position or result and the second level move to left control signal mutually or, produce the third level control signal that moves to left.After the first shift unit first order, 16 lts are finished, the second level that starts first shift unit one by one 16 and the third level 16 bit manipulations that move to left that move to left.First shift unit can be finished 0, and 16,32,48 shift left operation.The first, two, three grades of control signals that move to left have constituted the phase one shift signal.
In elementary or the array and the first shift unit work, four subregion leading zero detection parts also in commission.Wherein, the first subregion leading zero detection part carries out the leading zero detection to the 0-15 of unnormalized number, produces 4 leading zero testing result; The second subregion leading zero detection part carries out the leading zero detection to the 16-31 of unnormalized number, produces 4 leading zero testing result; The 3rd subregion leading zero detection part carries out the leading zero detection to the 32-47 of unnormalized number, produces 4 leading zero testing result; The 4th subregion leading zero detection part carries out the leading zero detection to the 48-56 of unnormalized number, produces 4 leading zero testing result.The operation that these four subregion leading zero detection parts carry out the different bit field of unnormalized number can walk abreast and carry out.
Before each subregion leading zero detection part work was finished, elementary or array had been worked and has been finished.Then, the output of each subregion leading zero detection part and the output of elementary or array are sent to low level leading zero signal generator, produce the leading zero testing result of low level, these signals also are the displacement control signals of second shift unit.Low level leading zero signal generator is to be made of the multilevel precedence selector switch, in the embodiment of the invention is to be made of three grades of selector switchs.Wherein, when the third level moves to left control signal when being 1, first selector selects the 3rd subregion leading zero testing result to be output, otherwise selects the 4th subregion leading zero testing result to be output; When the second level moves to left control signal when being 1, second selector selects the second subregion leading zero testing result to be output, otherwise selects the output of first selector; When the first order moves to left control signal when being 1, third selector selects the first subregion leading zero testing result to be output, otherwise selects the output of second selector.
In the work of low level leading zero signal generator, high-order leading zero signal generator is sent in the output of elementary or array, generate high-order leading zero result.High-order leading zero signal generator is to be made of three grades of preferential selector switchs.It selects input signal is four binary constants, and 11,10,01,00 forms, and highest priority is 11, and minimum is 00.Wherein, when the first order moves to left control signal when being 0, the 4th selector switch selects 10 to be output, otherwise selects 00 to be output; When the second level moves to left control signal when being 0, the 5th selector switch selects 10 to be output, otherwise selects the output of the 4th selector switch; When the third level moves to left control signal when being 0, the 6th selector switch selects 11 to be output, otherwise selects the output of the 5th selector switch.
At last, after first shift unit executes,, the leading zero result of low level as the subordinate phase shift signal, is started the execution of second shift unit with the shifted data of its shift result as second shift unit.Second shift unit can carry out the shift left operation of 0-15 position to shifted data.After the second shift unit work is intact, the output normalized result.High-order leading zero testing result and low level leading zero testing result are spliced into final leading zero testing result.
The present invention is not limited to previous embodiment, as normalization to the various floating-point formats among the IEEE754, and the floating-point format of other non-IEEE754 etc., the present invention is suitable for too.
Claims (1)
1. high-speed floating point normalized arithmetic device, comprise leading zero detection part and shift unit, it is characterized in that: described leading zero detection part comprises elementary or array, subregion leading zero detection part, low level leading zero signal generator and high-order leading zero signal generator; Subregion leading zero detection part carries out leading zero to the zones of different of unnormalized number and detects; Elementary or array carries out the logical OR operation to the zones of different of unnormalized number, produces the phase one shift signal; Described shift unit comprises first shift unit and second shift unit, and first shift unit is shifted to unnormalized number according to the phase one shift signal; Low level leading zero signal generator generates the subordinate phase shift signal according to the result of subregion leading zero detection part and the result of elementary or array; After first shift unit executes, the result and the subordinate phase shift signal of first shift unit are imported second shift unit, carry out shifting function; The result of second shift unit is exactly a normalized result; Simultaneously, high-order leading zero signal generator generates leading zero result's a high position according to the result of elementary or array, and the result with low level leading zero signal generator is spliced into the leading zero testing result then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102546387A CN101751239B (en) | 2009-12-31 | 2009-12-31 | High-speed floating point normalized arithmetic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102546387A CN101751239B (en) | 2009-12-31 | 2009-12-31 | High-speed floating point normalized arithmetic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101751239A true CN101751239A (en) | 2010-06-23 |
| CN101751239B CN101751239B (en) | 2011-06-08 |
Family
ID=42478261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009102546387A Expired - Fee Related CN101751239B (en) | 2009-12-31 | 2009-12-31 | High-speed floating point normalized arithmetic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101751239B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105786444A (en) * | 2014-12-26 | 2016-07-20 | 联想(北京)有限公司 | Detection method and apparatus for leading zeros in mantissas of floating-point number |
| CN112230882A (en) * | 2020-10-28 | 2021-01-15 | 海光信息技术股份有限公司 | Floating-point number processing device, floating-point number adding device and floating-point number processing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100555212C (en) * | 2007-07-18 | 2009-10-28 | 中国科学院计算技术研究所 | The carry calibration equipment of a kind of floating dual MAC and multiplication CSA compressed tree thereof |
| CN101221490B (en) * | 2007-12-20 | 2010-11-10 | 清华大学 | Floating point multiplier and adder unit with data forwarding structure |
| CN201628951U (en) * | 2009-12-31 | 2010-11-10 | 西北工业大学 | High-speed floating point normalization arithmetic unit |
-
2009
- 2009-12-31 CN CN2009102546387A patent/CN101751239B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105786444A (en) * | 2014-12-26 | 2016-07-20 | 联想(北京)有限公司 | Detection method and apparatus for leading zeros in mantissas of floating-point number |
| CN105786444B (en) * | 2014-12-26 | 2018-10-12 | 联想(北京)有限公司 | A kind of floating number mantissa leading zero detection method and device |
| CN112230882A (en) * | 2020-10-28 | 2021-01-15 | 海光信息技术股份有限公司 | Floating-point number processing device, floating-point number adding device and floating-point number processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101751239B (en) | 2011-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6001276B2 (en) | Apparatus and method for performing floating point addition | |
| KR101735677B1 (en) | Apparatus for multiply add fused unit of floating point number, and method thereof | |
| KR0139733B1 (en) | Method and device for rounding a floating point addition / subtraction operator | |
| CN108459840B (en) | SIMD structure floating point fusion point multiplication operation unit | |
| US7707236B2 (en) | Methods and apparatus for an efficient floating point ALU | |
| US5148386A (en) | Adder-subtracter for signed absolute values | |
| US6199089B1 (en) | Floating point arithmetic logic unit rounding using at least one least significant bit | |
| WO2007032985A2 (en) | Floating point normalization and denormalization | |
| CN201628951U (en) | High-speed floating point normalization arithmetic unit | |
| US7668892B2 (en) | Data processing apparatus and method for normalizing a data value | |
| US9317478B2 (en) | Dual-path fused floating-point add-subtract | |
| CN101751239B (en) | High-speed floating point normalized arithmetic device | |
| CN104991757A (en) | Floating point processing method and floating point processor | |
| CN104778026A (en) | High-speed data format conversion part with SIMD (single instruction multiple data) and conversion method thereof | |
| JP2012528391A (en) | Integer and multiply-add operations with saturation | |
| JP4858794B2 (en) | Floating point divider and information processing apparatus using the same | |
| US8554819B2 (en) | System to implement floating point adder using mantissa, rounding, and normalization | |
| US6889241B2 (en) | Floating point adder | |
| US7680874B2 (en) | Adder | |
| JPS608933A (en) | Arithmetic processing unit | |
| US5920493A (en) | Apparatus and method to determine a most significant bit | |
| US6571267B1 (en) | Floating point addition/subtraction execution unit | |
| CN105786444A (en) | Detection method and apparatus for leading zeros in mantissas of floating-point number | |
| CN100543723C (en) | The method that is used for efficient floating point calculator (ALU) | |
| US6684232B1 (en) | Method and predictor for streamlining execution of convert-to-integer operations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110608 Termination date: 20131231 |