CN101741455B - Equalizer and method applying same - Google Patents
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- CN101741455B CN101741455B CN 200810176822 CN200810176822A CN101741455B CN 101741455 B CN101741455 B CN 101741455B CN 200810176822 CN200810176822 CN 200810176822 CN 200810176822 A CN200810176822 A CN 200810176822A CN 101741455 B CN101741455 B CN 101741455B
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Abstract
The invention discloses an equalizer and a method applying the same. The equalizer comprises a first feed forward equalizing module, a second feed forward equalizing module and a phase error corrector. The first feed forward equalizing module and the second feed forward equalizing module respectively receive an input real part component signal and an input imaginary part component signal of a plurality of input signals and respectively equalize the input real part component signal and the input imaginary part component signal to generate a first real part component signal and a first imaginary part component signal. The phase error corrector is coupled to the first feed forward equalizing module and the second feed forward equalizing module and used for adjusting the plural phase corresponding to the first real part component signal and the first imaginary part component signal according to phase error information so as to generate a second real part component signal and a second imaginary part component signal.
Description
Technical field
The present invention relates to a kind of eqalizing cricuit and correlation technique thereof, relate in particular to and a kind of eqalizing cricuit and phase-error corrector are done better combination with the apparatus and method of the usefulness that promotes eqalizing cricuit.
Background technology
In communication system; disturb (Inter Symbol Interference between symbol; ISI) be a kind of quite common phenomenon; its main reason is multi-path transmission (multipath propagation); therefore, signal receiving end can add when eqalizing cricuit (equalizer) solves the signal transmission usually because the impact that the multi-path transmission causes.
And utilize eqalizing cricuit to process complex signal (vestigial sideband signal for example, VSB) time, if only with single eqalizing cricuit during to the processing such as real part composition grade in complex signal, because the signal of eqalizing cricuit still exists phase error, can limit the usefulness of eqalizing cricuit.And, although the signal after processing through eqalizing cricuit still can be adjusted its phase difference by phase-error corrector, because phase-error corrector only has one dimension input (the real part composition is only arranged), also can cause the usefulness of eqalizing cricuit not good.Therefore, how to promote the usefulness of eqalizing cricuit, namely become one of the important topic in the design field.
Summary of the invention
One of purpose of the present invention is to provide a kind of eqalizing cricuit and correlation technique thereof, to solve the problem in prior art.
Embodiments of the invention disclose a kind of eqalizing cricuit, and it includes the first module such as feedforward gradeization, the second feedforward etc. and changes module and phase-error corrector.The change modules such as the first feedforward become sub-signal in order to the input real part that receives complex input signal, and will input real part and become processing such as sub-signal grade to become sub-signal to produce the first real part.The change modules such as the second feedforward become sub-signal in order to the input imaginary part that receives complex input signal, and will input imaginary part and become processing such as sub-signal grade to become sub-signal to produce the first imaginary part.Phase-error corrector is coupled to the first feedforward module such as gradeization and the second feedforward etc. and changes module, is used for adjusting the first real part according to phase error information and becomes sub-signal to become sub-signal corresponding one plural phase place to become sub-signal and the second imaginary part to become sub-signal to produce the second real part with the first imaginary part.Wherein, the joint efficiency used according to change modules such as the first feedforwards of the change module such as the second feedforward becomes processing such as sub-signal grade to inputting imaginary part.
Embodiments of the invention separately disclose a kind of method that is applied to the first device, and the method includes: the input real part that receives complex input signal becomes sub-signal, and will input real part and become processing such as sub-signal grade to become sub-signal to produce the first real part; The input imaginary part that receives complex input signal becomes sub-signal, and will input imaginary part and become processing such as sub-signal grade to become sub-signal to produce the first imaginary part; And adjust the first real part and become sub-signal to become sub-signal corresponding one plural phase place to become sub-signal and the second imaginary part to become sub-signal to produce the second real part with the first imaginary part according to a phase error information.
Description of drawings
Fig. 1 is the schematic diagram of the first embodiment of eqalizing cricuit of the present invention.
Fig. 2 is the schematic diagram of the second embodiment of eqalizing cricuit of the present invention.
Fig. 3 is the flow chart of an example operation of the present invention's method of being applied to eqalizing cricuit.
Fig. 4 is the flow chart of another example operation of the present invention's method of being applied to eqalizing cricuit.
[main element symbol description]
100,200 eqalizing cricuits
110 first modules such as feedforward gradeization
120 second modules such as feedforward gradeization
130 phase-error corrector
140 first arithmetic elements
150 data slicers
160 feedback equalization modules
X[n] complex input signal
x
r[n] input real part becomes sub-signal
x
i[n] input imaginary part becomes sub-signal
y
r1[n] first real part becomes sub-signal
y
i1[n] first imaginary part becomes sub-signal
y
r2[n] second real part becomes sub-signal
y
i2[n] second imaginary part becomes sub-signal
y
r3[n] the 3rd real part becomes sub-signal
eqo
r[n] output real part becomes sub-signal
The Sd testing result
d
r[n], d
i[n] phase error information
210 first delayers
220 filters
230 first arithmetic elements
240 second delayers
250 phase error estimation and phase error devices
y
i' [n] estimate that imaginary part becomes sub-signal
y
di2[n] postponed the second imaginary part and become sub-signal
eqo
di[n] postponed to export imaginary part and become sub-signal
eqo
dr[n] postponed to export real part and become sub-signal
eqo
d[n] postponed plural output signal
302～314,410～450 steps
Embodiment
Please refer to Fig. 1, Fig. 1 is the schematic diagram of the first embodiment of eqalizing cricuit 100 of the present invention.Eqalizing cricuit 100 comprises (but being not limited to) first module such as feedforward gradeization 110, the second feedforward etc. and changes module 120, phase-error corrector 130, the first arithmetic element 140, data slicer 150 and feedback equalization module 160.As shown in Figure 1, the first 110 reception complex input signal x[n such as feedforward module such as gradeizations] input real part composition (real-part component) signal x
r[n], and will input real part and become sub-signal x
rProcessing such as [n] grade becomes sub-signal y to produce the first real part
r1[n].The second x[n such as reception complex input signal such as 120 of feedforward modules such as gradeizations] input imaginary part composition (imaginary-part component) signal x
i[n], and will input imaginary part and become sub-signal x
iProcessing such as [n] grade becomes sub-signal y to produce the first imaginary part
i1[n].And phase-error corrector (phase error corrector) 130 is coupled to the change modules 120 such as the first module such as feedforward gradeization 110 and the second feedforward, is used for according to phase error information d
r[n], d
i[n] adjusts the first real part and becomes sub-signal y
r1[n] becomes sub-signal y with the first imaginary part
i1[n] corresponding plural phase place becomes sub-signal y to produce the second real part
r2[n] and the second imaginary part become sub-signal y
i2[n].In addition, the first arithmetic element 140 is coupled to phase-error corrector 130, is used for the second real part is become sub-signal y
r2[n] becomes sub-signal y with the 3rd real part
r3[n] carries out computing and becomes sub-signal eqo to produce the output real part
r[n].Data slicer (slicer) 150 is coupled to the first arithmetic element 140, is used for carrying out rigid decision-making and becomes sub-signal eqo in the output real part
rOn [n], to produce testing result Sd.Feedback equalization module 160 is coupled to data slicer 150 and the first arithmetic element 140, is used for the changes such as execution to process on testing result Sd, becomes sub-signal y to produce the 3rd real part
r3[n].
Note that above-mentioned complex input signal x[n] (include the input real part and become sub-signal x
r[n] and input imaginary part become sub-signal x
i[n]) can be a vestigial sideband (vestigial sideband, VSB) signal, but the present invention is not limited thereto, also can be the signal of other kinds.And eqalizing cricuit 100 can be one and determines feedback equalization device (decision feedback equalizer, DFE), but this is not restrictive condition of the present invention, also can be the eqalizing cricuit of other kinds.
Please note again, the change modules 120 such as the change module 110 such as the first feedforward and the second feedforward can each be implemented it by a joint delay line eqalizing cricuit (tapped delay line equalizer), and joint efficiency (tap coefficient) f that uses of the change modules 110 such as change module 120 foundation the first feedforwards such as the second feedforward
r[n] becomes sub-signal x to the input imaginary part
iProcessing such as [n] grade.In other words, the module 110 identical joint efficiency f of employing are changed in the second module such as feedforward gradeization 120 and the first feedforward etc.
r[n] comes respectively the input real part to be become sub-signal x
r[n] becomes sub-signal x with the input imaginary part
iProcessing such as [n] grade, but this is only the preferred embodiments of the present invention, and other can reach identical purpose and the implementation mode of spirit according to the invention also belongs to covering scope of the present invention.
In the present embodiment, the first arithmetic element 140 realizes by an adder, and adder becomes sub-signal y with the second real part
r2[n] deducts the 3rd real part and becomes sub-signal y
r3[n] becomes sub-signal eqo to produce the output real part
r[n], but the present invention is not limited thereto, also can adopt the arithmetic unit of other kinds to implement.
As shown in Figure 1, by change modules 120 such as the change module 110 such as the first feedforward and the second feedforwards, the input real part is become sub-signal x respectively
r[n] becomes sub-signal x with the input imaginary part
iProcessing such as [n] grade, the signal that inputs to phase-error corrector 130 includes the two dimension input, and (that is the first real part becomes sub-signal y
r1[n] becomes sub-signal y with the first imaginary part
i1[n]), thus, not only the effect of phase-error corrector 130 adjustment phase differences can improve, and can also further promote the usefulness of eqalizing cricuit 100.In addition, the second real part of exporting of phase-error corrector 130 becomes sub-signal y
r2[n] via the processing that determines feedback fraction (that is the first arithmetic element 140, data slicer 150 and feedback equalization module 160), the output real part that can obtain eqalizing cricuit 100 becomes sub-signal eqo again
r[n].
Certainly, above-mentioned eqalizing cricuit 100 only is one of feasible embodiment of the present invention, and in other embodiment, can design more function promotes eqalizing cricuit in eqalizing cricuit usefulness.Please refer to Fig. 2, Fig. 2 is the schematic diagram of the second embodiment of eqalizing cricuit 200 of the present invention.The eqalizing cricuit 200 of Fig. 2 is similar with eqalizing cricuit 100 shown in Figure 1, and both are described below difference.Eqalizing cricuit 200 also comprises the first delayer 210, filter 220, the second arithmetic element 230, the second delayer 240 and to bit error estimator 250.The first delayer 210 is coupled to phase-error corrector 130, becomes sub-signal y in order to postpone the second imaginary part
i2[n] postponed the second imaginary part with generation and become sub-signal y
di2[n].Filter 220 is coupled to feedback equalization module 160, becomes sub-signal y in order to receive the 3rd real part
r3[n], and become sub-signal y according to the 3rd real part
r3[n] produces and estimates that imaginary part becomes sub-signal y
i' [n].Afterwards, the second arithmetic element 230 will postpone the second imaginary part again and become sub-signal y
di2[n] becomes sub-signal y with the estimation imaginary part
i' [n] carry out computing (for example subtracting each other) and postponed to export imaginary part and become sub-signal eqo to produce
di[n].The second 240 of delayers are coupled to the first arithmetic element 140, become sub-signal eqo in order to postpone the output real part
r[n] postponed to export real part with generation and become sub-signal eqo
dr[n] wherein postponed to export real part and become sub-signal eqo
dr[n] with postpone to export imaginary part and become sub-signal eqo
di[n] consists of one and postponed plural output signal e qo
d[n].In addition, phase error estimation and phase error device 250 is coupled to phase-error corrector 130, and becomes sub-signal eqo according to testing result Sd, output real part
r[n], postpone to export real part and become sub-signal eqo
dr[n] and postponed to export imaginary part and become sub-signal eqo
diIn [n] at least one come estimating phase error information d
r[n], d
i[n].
In the present embodiment, filter 220 can be Hilbert conversion (Hilbert Transform) circuit or its approximator, but this is not restrictive condition of the present invention.The 3rd real part becomes sub-signal y
r3[n] through after filter 220, the estimated value that can produce the imaginary part composition (that is estimates that imaginary part becomes sub-signal y
i' [n]).About the characteristic of Hilbert conversion (Hilbert Transform) known to those skilled in the art knowing, for for purpose of brevity, detail section does not repeat them here.In addition, the second arithmetic element 230 can realize by an adder, and adder will postpone the second real part and become sub-signal y
dr2[n] deducts and estimates that imaginary part becomes sub-signal y
i' [n], the output of the delay imaginary part that can obtain eqalizing cricuit 200 becomes sub-signal eqo
di[n], but the present invention is not limited thereto, also can adopt the arithmetic unit of other kinds to implement.
Note that phase error information d
r[n], d
i[n] consists of one group of complex signal, and can be represented by following formula:
d
r[n]＝cosΔθ (1)
d
i[n]＝sinΔθ (2)
In complex signal was processed, what the performed action of phase-error corrector 130 represented was with (y
r1[n]+j*y
i1[n]) turn the result after an angle delta θ, can following formula represent:
y
r2[n]＝y
r1[n]*d
r[n]-y
i1[n]*d
i[n] (3)
y
i2[n]＝y
r1[n]*d
i[n]+y
i1[n]*d
r[n] (4)
Can be learnt by Fig. 2, because phase error estimation and phase error device 250 can become sub-signal eqo according to testing result Sd, output real part
r[n], postpone to export real part and become sub-signal eqo
dr[n] and postponed to export imaginary part and become sub-signal eqo
diIn [n] at least one come estimating phase error information d
r[n], d
i[n] thus, can significantly improve the first real part and become sub-signal y
r1[n] becomes sub-signal y with the first imaginary part
i1The phase difference of [n] is with the usefulness of further lifting eqalizing cricuit.
Please refer to Fig. 3, Fig. 3 is the flow chart of one of the present invention's method of being applied to eqalizing cricuit example operation, it comprises (but being not limited to) following step and (please notes, if can obtain identical in fact result, these steps might not be carried out in accordance with execution order shown in Figure 3):
Step 302: beginning.
Step 304: the input real part that receives complex input signal becomes sub-signal, and will input real part and become processing such as sub-signal grade to become sub-signal to produce the first real part.
Step 306: the input imaginary part that receives complex input signal becomes sub-signal, and will input imaginary part and become processing such as sub-signal grade to become sub-signal to produce the first imaginary part.
Step 308: adjust the first real part according to phase error information and become sub-signal to become sub-signal corresponding one plural phase place with the first imaginary part, become sub-signal and the second imaginary part to become sub-signal to produce the second real part.
Step 310: become sub-signal to become sub-signal to carry out computing with the 3rd real part the second real part, become sub-signal to produce the output real part.
Step 312: carry out rigid decision-making and become on sub-signal in the output real part, to produce testing result.
Step 314: the changes such as execution are processed on this testing result, become sub-signal to produce the 3rd real part.
About each element that each step shown in Figure 3 please be arranged in pairs or groups shown in Figure 1, can understand each element and how to operate, therefore do not repeat them here.
Please refer to Fig. 4, Fig. 4 is the flow chart of another example operation of the present invention's method of being applied to eqalizing cricuit, and it comprises (but being not limited to) following steps:
Step 302: beginning.
Step 304: the input real part that receives complex input signal becomes sub-signal, and will input real part and become processing such as sub-signal grade to become sub-signal to produce the first real part.
Step 306: the input imaginary part that receives complex input signal becomes sub-signal, and will input imaginary part and become processing such as sub-signal grade to become sub-signal to produce the first imaginary part.
Step 308: adjust the first real part according to phase error information and become sub-signal to become sub-signal corresponding one plural phase place with the first imaginary part, become sub-signal and the second imaginary part to become sub-signal to produce the second real part.Execution in step 310,410.
Step 310: become sub-signal to become sub-signal to carry out computing with the 3rd real part the second real part and become sub-signal to produce the output real part.Execution in step 312,440.
Step 312: carry out rigid decision-making and become on sub-signal in the output real part, to produce testing result.
Step 314: the changes such as execution are processed on this testing result, become sub-signal to produce the 3rd real part.Execution in step 420.
Step 410: delay the second imaginary part becomes sub-signal to postpone the second imaginary part with generation and becomes sub-signal.
Step 420: receive the 3rd real part and become sub-signal, and become the sub-signal generation to estimate that imaginary part becomes sub-signal according to the 3rd real part.
Step 430: will postpone the second imaginary part and become sub-signal and estimate that imaginary part becomes sub-signal to carry out computing, and postpone to export imaginary part with generation and become sub-signal.
Step 440: postpone this output real part and become sub-signal to postpone to export real part and become sub-signal to produce one.
Step 450: become sub-signal, postpone to export real part and become sub-signal and postponed to export imaginary part to become the one at least in sub-signal to estimate that corresponding real part becomes sub-signal to become the phase error information of sub-signal with imaginary part according to testing result, output real part.
The step of Fig. 4 and the step of Fig. 3 are similar, it is the alternate embodiment of Fig. 3, both differences are that the flow process of Fig. 4 has separately increased operation and the function (that is step 410～450) of the first delayer 210, filter 220, the second arithmetic element 230, the second delayer 240 and phase error estimation and phase error device 250, can further improve the first real part and become sub-signal y
r1[n] becomes sub-signal y with the first imaginary part
i1The phase difference of [n].About each element that each step shown in Figure 4 please be arranged in pairs or groups shown in Figure 2, can understand each element and how to operate, therefore do not repeat them here.
The step of above-mentioned flow process only for the present invention for feasible embodiment, and unrestricted restrictive condition of the present invention, and in the situation that without prejudice to spirit of the present invention, the method can also comprise other intermediate steps or several steps can be merged into one step, to do suitable variation.
Above-described embodiment only is used for technical characterictic of the present invention is described, is not to limit to scope of the present invention.As from the foregoing, the invention provides a kind of eqalizing cricuit and correlation technique thereof.By change modules 120 such as the change module 110 such as the first feedforward and the second feedforwards, the input real part is become sub-signal x respectively
r[n] becomes sub-signal x with the input imaginary part
iProcessing such as [n] grade, the signal that inputs to phase-error corrector 130 includes the two dimension input, and thus, not only the effect change of phase-error corrector 130 adjustment phase differences is better, further the usefulness of lifting eqalizing cricuit.And the second real part that phase-error corrector 130 is exported becomes sub-signal y
r2After [n] processing via the decision feedback fraction, the output real part that can obtain eqalizing cricuit 100 becomes sub-signal eqo
r[n].Filter 220 can become sub-signal y according to the 3rd real part
r3[n] produces and estimates that imaginary part becomes sub-signal y
i' [n], become sub-signal y by adder with postponing the second imaginary part more afterwards
di2[n] becomes sub-signal y with the estimation imaginary part
i' [n] subtract each other, can obtain having postponed to export imaginary part and become sub-signal eqo
di[n].At last, (for example testing result Sd, output real part become sub-signal eqo with above-mentioned resulting signal
r[n], postpone to export real part and become sub-signal eqo
dr[n] and postponed to export imaginary part and become sub-signal eqo
diAt least one in [n]) input to phase error estimation and phase error device 250 for its estimating phase error information d
r[n], d
i[n] thus, can significantly improve the first real part and become sub-signal y
r1[n] becomes sub-signal y with the first imaginary part
i1The phase difference of [n] is further to promote the usefulness of eqalizing cricuit.
The above is only the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (18)
1. eqalizing cricuit includes:
One first feedforward module such as gradeizations is inputted real part and is become sub-signal in order to receive one of a complex input signal, and should input real part and become processing such as sub-signal grade to become sub-signal to produce one first real part;
One second feedforward module such as gradeizations is inputted imaginary part and is become sub-signal in order to receive one of this complex input signal, and should input imaginary part and become processing such as sub-signal grade to become sub-signal to produce one first imaginary part; And
One phase-error corrector, be coupled to this first feedforward module such as gradeization and this second feedforward etc. and change module, being used for adjusting this first real part according to a phase error information becomes sub-signal to become sub-signal corresponding one plural phase place to become sub-signal and one second imaginary part to become sub-signal to produce one second real part with this first imaginary part
Wherein the joint efficiency used according to change modules such as this first feedforwards of the change module such as this second feedforward becomes processing such as sub-signal grade to this input imaginary part.
2. eqalizing cricuit as claimed in claim 1, wherein this complex input signal is a vestigial sideband signal.
3. eqalizing cricuit as claimed in claim 1, it also comprises:
One first arithmetic element is coupled to this phase-error corrector, is used for becoming sub-signal to become sub-signal to carry out computing with one the 3rd real part this second real part and becomes sub-signal to produce an output real part;
One data slicer is coupled to this first arithmetic element, is used for carrying out a rigid decision-making and becomes on sub-signal to produce a testing result in this output real part; And
One feedback equalization module is coupled to this data slicer and this first arithmetic element, is used for carrying out first and processes on this testing result and become sub-signal to produce the 3rd real part.
4. eqalizing cricuit as claimed in claim 3, wherein this first arithmetic element is an adder, is used for becoming sub-signal to deduct the 3rd real part this second real part and becomes sub-signal to become sub-signal to produce this output real part.
5. eqalizing cricuit as claimed in claim 3, it also comprises:
One first delayer is coupled to this phase-error corrector, becomes sub-signal to postpone the second imaginary part and become sub-signal to produce one in order to postpone this second imaginary part;
One filter is coupled to this feedback equalization module, becomes sub-signal in order to receive the 3rd real part, and becomes sub-signal generation one to estimate that imaginary part becomes sub-signal according to the 3rd real part; And
One second arithmetic element is coupled to this filter and this first delayer, is used for that this has been postponed the second imaginary part and becomes sub-signal to become sub-signal to carry out computing with this estimation imaginary part to have postponed to export imaginary part and become sub-signal to produce one.
6. eqalizing cricuit as claimed in claim 5, wherein this second arithmetic element is an adder, is used for that this has been postponed the second imaginary part and becomes sub-signal to deduct this estimation imaginary part to become sub-signal to postpone to export imaginary part and become sub-signal to produce this.
7. eqalizing cricuit as claimed in claim 5, it also comprises:
One second delayer is coupled to this first arithmetic element, becomes sub-signal to postpone to export real part and become sub-signal to produce one in order to postpone this output real part;
Wherein this has postponed to export real part and becomes sub-signal and this to postpone to export imaginary part to become sub-signal to consist of one to have postponed plural output signal.
8. eqalizing cricuit as claimed in claim 7, it also comprises a phase error estimation and phase error device, be coupled to this phase-error corrector, in order to become sub-signal according to this testing result, this output real part, this has postponed to export real part and has become sub-signal and this to postpone to export imaginary part to become in sub-signal at least one to estimate to become sub-signal to become this phase error information of sub-signal with this input imaginary part to inputting real part.
9. eqalizing cricuit as claimed in claim 1, wherein the change module such as the change module such as this first feedforward and this second feedforward is respectively a joint delay line eqalizing cricuit.
10. eqalizing cricuit as claimed in claim 1, it is one to determine the feedback equalization device.
11. a method that is applied to the first device includes:
An input real part that receives a complex input signal becomes sub-signal, and should input real part and become processing such as sub-signal grade to become sub-signal to produce one first real part;
An input imaginary part that receives this complex input signal becomes sub-signal, and should input imaginary part and become processing such as sub-signal grade to become sub-signal to produce one first imaginary part; And
Adjust this first real part according to a phase error information and become sub-signal to become sub-signal corresponding one plural phase place to become sub-signal and one second imaginary part to become sub-signal to produce one second real part with this first imaginary part,
Wherein will input step that real part becomes processing such as sub-signal grade comprises the joint efficiency of using according to change modules such as one first feedforwards this input real part is become processing such as sub-signal grade; And
Become the step of processing such as sub-signal grade to comprise the joint efficiency of using according to change modules such as this first feedforwards this input imaginary part this input imaginary part is become processing such as sub-signal grade.
12. method as claimed in claim 11, wherein this complex input signal is a vestigial sideband signal.
13. method as claimed in claim 11, it also comprises:
Become sub-signal to become sub-signal to carry out computing with one the 3rd real part this second real part and become sub-signal to produce an output real part;
Carrying out a rigid decision-making becomes sub-signal to produce a testing result in this output real part; And
The execution first is processed on this testing result and is become sub-signal to produce the 3rd real part.
14. method as claimed in claim 13 wherein becomes this second real part sub-signal to become sub-signal to carry out computing with the 3rd real part and becomes the step of sub-signal to comprise to produce this output real part:
Becoming sub-signal to deduct the 3rd real part this second real part becomes sub-signal to become sub-signal to produce this output real part.
15. method as claimed in claim 13, it also comprises:
Postponing this second imaginary part becomes sub-signal to postpone the second imaginary part and become sub-signal to produce one;
Receive the 3rd real part and become sub-signal, and become sub-signal generation one to estimate that imaginary part becomes sub-signal according to the 3rd real part; And
This has been postponed the second imaginary part becomes sub-signal to become sub-signal to carry out computing with this estimation imaginary part to have postponed to export imaginary part and become sub-signal to produce one.
16. method as claimed in claim 15 has wherein postponed this second imaginary part and has become sub-signal to become sub-signal to carry out computing with this estimation imaginary part to have postponed to export imaginary part and become the step of sub-signal to comprise to produce this:
This has been postponed the second imaginary part becomes sub-signal to deduct this estimation imaginary part to become sub-signal to postpone to export imaginary part and become sub-signal to produce this.
17. method as claimed in claim 15, it also comprises:
Postponing this output real part becomes sub-signal to postpone to export real part and become sub-signal to produce one;
Wherein this has postponed to export real part and becomes sub-signal and this to postpone to export imaginary part to become sub-signal to consist of one to have postponed plural output signal.
18. method as claimed in claim 17, it also comprises:
According to this testing result, this output real part become sub-signal, this has postponed to export real part and has become sub-signal and this to postpone to export imaginary part to become the one at least in sub-signal to estimate to become sub-signal to become this phase error information of sub-signal with this input imaginary part to inputting real part.
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| CN1688146A (en) * | 2005-04-28 | 2005-10-26 | 上海微科集成电路有限公司 | Adaptive equalizing and carrier recovering method suitable for high-order QAM and circuit thereof |
| CN1799202A (en) * | 2003-06-06 | 2006-07-05 | 美商内数位科技公司 | Method and system for continuously compensating for phase variations introduced into a communication signal by automatic gain control adjustments |
| CN1852278A (en) * | 2006-04-24 | 2006-10-25 | 上海交通大学 | Phase tracking loop with NR decoding |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1799202A (en) * | 2003-06-06 | 2006-07-05 | 美商内数位科技公司 | Method and system for continuously compensating for phase variations introduced into a communication signal by automatic gain control adjustments |
| CN1688146A (en) * | 2005-04-28 | 2005-10-26 | 上海微科集成电路有限公司 | Adaptive equalizing and carrier recovering method suitable for high-order QAM and circuit thereof |
| CN1852278A (en) * | 2006-04-24 | 2006-10-25 | 上海交通大学 | Phase tracking loop with NR decoding |
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