CN101740527B - Chip packaging structure and manufacture method thereof - Google Patents
Chip packaging structure and manufacture method thereof Download PDFInfo
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- CN101740527B CN101740527B CN2008101768094A CN200810176809A CN101740527B CN 101740527 B CN101740527 B CN 101740527B CN 2008101768094 A CN2008101768094 A CN 2008101768094A CN 200810176809 A CN200810176809 A CN 200810176809A CN 101740527 B CN101740527 B CN 101740527B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 239000000084 colloidal system Substances 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims description 128
- 238000012856 packing Methods 0.000 claims description 57
- 230000017525 heat dissipation Effects 0.000 claims description 56
- 239000000853 adhesive Substances 0.000 claims description 18
- 230000001070 adhesive effect Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000004568 cement Substances 0.000 claims description 3
- 210000002683 foot Anatomy 0.000 claims 27
- 238000012545 processing Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000000741 silica gel Substances 0.000 description 7
- 229910002027 silica gel Inorganic materials 0.000 description 7
- 238000003780 insertion Methods 0.000 description 5
- 230000037431 insertion Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000002360 explosive Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
The invention relates to a chip packaging structure which comprises a base plate, at least one chip, a heat radiating element, at least one first conducting post, a packaging colloid and at least one second conducting post, wherein the base plate is provided with a first surface and a second surface which are opposite to each other; the chip is configured on the first surface of the base plate; the heat radiating element is configured on the second surface of the base plate; each first conducting post has two opposite end surfaces, one end surface is configured on the first surface of the base plate and electrically connected with the base plate, and the other end surface extends to the direction far away from the base plate; a fixed groove is arranged between the two end surfaces and penetrates through the other end surface; the packaging colloid coats the base plate, the chips, part of heat radiating element and the first conducting posts and has two opposite surfaces, and one surface is exposed out of the surface of the heat radiating element, which is far away from the base plate; each second conducting post is arranged on the other surface of the packaging colloid and comprises a conductive pin part and a lug boss, and the lug boss of each second conducting post is fixed in a fixed groove of each first conducting post.
Description
Technical field
The invention relates to a kind of chip-packaging structure and preparation method thereof, and particularly relevant for a kind of chip-packaging structure with high-voltage protection and preparation method thereof.
Background technology
When design needs the chip-packaging structure (for example being responsible for the power supply module of control power supply or the IGBT module of control motor driven) of high voltage input; For (for example: standard UL Standard) and guarantee the normal operation of encapsulating structure meeting safety requirements; Usually need consider encapsulating structure voltage input end (for example: lead foot) and the metal material (for example: creepage distance heat dissipation element) (creepage distance) and space length (clearance distance); Cause electrical short circuit to avoid conducting between lead foot and the heat dissipation element; And prevent directly to jump to low-pressure end (being heat dissipation element) by the instant high-voltage of lead foot input, and harm user safety.
Fig. 1 illustrates the profile of the encapsulating structure of existing high-power die.Fig. 2 A～Fig. 2 B illustrates the processing procedure profile of the chip-packaging structure of Fig. 1.Please with reference to Fig. 1, existing chip encapsulating structure 100 has a substrate 110, a plurality of chip 120, a heat dissipation element E, a plurality of lead foot 130, a housing 140, a silica gel layer 150 and an enclosing cover 160.Substrate 110 has two surfaces 112,114 respect to one another, and chip 120 is configured on the surface 112, and heat dissipation element E is disposed on the surface 114.Housing 140 is disposed on the surface 112, and housing 140 opening 144 that has relative two surfaces 141,142, be positioned at an opening 143 on surface 141 and be positioned at surface 142.Opening 143 expose heat dissipation element E towards a surface away from substrate 110 directions, and opening 144 exposes the chip 120 on the substrate 110.
The manufacture method of existing chip encapsulating structure 100 is described below.At first, please with reference to Fig. 2 A, lead foot 130 is made in the housing 140, method can be earlier to be put into mould with lead foot 130 together ejection formation or first ejection molded housing 140 embeds housings 140 with lead foot 130 again with housing 140 again.Then,, heat dissipation element E is disposed on the surface 114 of substrate 110 please with reference to Fig. 2 B, after be disposed on the surface 112 of substrate 110 chip 120 and between routing joint chip 120 and substrate 110 and the chip 120.Then, housing 140 is disposed on the surface 112 of substrate 110 and with substrate 110 gummeds, the opening 144 of housing 140 exposes the part surface 112 and the chip 120 of substrate 110, opening 143 exposes the surface of heat dissipation element E.Afterwards, routing joint chip 120, substrate 110 and lead foot 130.Then,, silica gel is inserted in the opening 144, to form silica gel layer 150 please once more with reference to Fig. 1.At last, be disposed at enclosing cover 160 on the silica gel layer 150 and seal opening 144.
Because lead foot 130 is to be extended by surface 142; And surface 142 is relative with the surface 141 that is provided with heat dissipation element E; Therefore, the creepage distance and the space length of existing chip encapsulating structure 100 are bigger, make that encapsulating structure 100 can be high voltage withstanding and meet safety requirements.But the making step of existing chip encapsulating structure 100 is quite complicated, and housing 140 all is disposed on the surface 112 of substrate 110 with chip 120, so but the area of substrate 110 carries chips 120 is less.For making substrate 110 have enough loaded areas, certainly will need to increase the size of substrate 110, and this will cause the cost of substrate 110 to increase and the volume of encapsulating structure 100 increases.
Summary of the invention
The present invention proposes a kind of chip-packaging structure, can effectively increase creepage distance and space length between lead foot and the heat dissipation element, makes the encapsulating structure can be high voltage withstanding and meet safety requirements, but and the area of its substrate carries chips bigger.
The present invention proposes a kind of manufacture method of chip-packaging structure in addition, can save existing step of making housing and configuration enclosing cover, reaches the simplification fabrication schedule.
The present invention proposes a kind of manufacture method of chip-packaging structure again, can prevent in the groove of packing colloid overflow to mould in manufacture procedure of adhesive and pollutes mould, and then prolong the useful life of mould.
The present invention proposes a kind of chip-packaging structure, and it comprises a substrate, at least one chip, at least one first conductive pole, a heat dissipation element, a packing colloid and at least one second conductive pole.Substrate has opposite first and second surface.Chip configuration is on the first surface of substrate.First conductive pole has relative both ends of the surface, and wherein an end face is disposed on the first surface of substrate and with substrate and electrically connects, and extend towards the direction away from substrate the other end, a holddown groove is set between the both ends of the surface and it runs through the other end.Heat dissipation element is disposed on the second surface of substrate.Packing colloid coats substrate, chip, part heat dissipation element and first conductive pole, and packing colloid has two opposite surfaces, and wherein a surface exposes the surface away from substrate of heat dissipation element.Second conductive pole is arranged on another surface on two surfaces of packing colloid, and second conductive pole comprises a lead foot portion and a lug boss, and the lug boss of second conductive pole is fixed in the holddown groove of first conductive pole.
In one embodiment of this invention, the inwall of the holddown groove of first conductive pole has one first screw thread, and the sidewall of the lug boss of second conductive pole has one second screw thread with first threaded engagement, and lug boss screws in the holddown groove.
In one embodiment of this invention, second conductive pole more comprises a stop section, and the stop section is between lead foot portion and lug boss, and the stop section directly contacts with another surface of the packing colloid that is positioned at second conductive pole periphery.
In one embodiment of this invention, the lug boss of second conductive pole is fixed in that mode in the holddown groove of first conductive pole can be that close-fitting connects, trip interlocking or gummed connect.
In one embodiment of this invention, first conductive pole is a polygonal cylinder, an oval cylinder or a cylinder.
In one embodiment of this invention, the lateral wall of first conductive pole has at least one groove or at least one convexity, and packing colloid is inserted in the groove or coating is protruding.
In one embodiment of this invention, groove is a v-depression, a circular groove, a half slot or a helical groove.
The present invention proposes a kind of chip-packaging structure and comprises a substrate, at least one chip, a plurality of lead foot, a heat dissipation element and a packing colloid.Substrate has a relative first surface and a second surface.Chip configuration is on the first surface of substrate.Each lead foot has one first end and one second end, and the external diameter of each lead foot increases progressively to first end by second end, and first end is disposed on the first surface of substrate, and second end extends towards the direction away from substrate.Heat dissipation element is disposed at the second surface of substrate.Packing colloid coats the part of substrate, chip, part heat dissipation element and lead foot.Packing colloid has two opposite surfaces, and wherein a surface exposes the surface away from substrate of heat dissipation element, and the part of each lead foot is extended by another surface on two surfaces of packing colloid.
In one embodiment of this invention, each lead foot is the cone that cuts off.
In one embodiment of this invention, the part that is positioned at packing colloid of each lead foot has a groove or a convexity, and packing colloid is inserted in the groove or coating is protruding.
The manufacture method that the present invention proposes a kind of chip-packaging structure is described below.At first, a substrate, at least one chip, a plurality of lead foot and a heat dissipation element are provided, wherein chip configuration is on substrate.Each lead foot has one first end and one second end, and the external diameter of each lead foot increases progressively to first end by second end, and first end is disposed on the substrate, and second end extends towards the direction away from substrate.Heat dissipation element is disposed at the surface away from lead foot of substrate.Then, a mould is provided, mould has a die cavity, and the inner surface of die cavity has a plurality of first grooves, and each first groove has an opening and a bottom, and the internal diameter of each first groove is increased progressively to opening by the bottom.Then, substrate is disposed in the die cavity of mould, so that second end of each lead foot is interfered driving fit with the first corresponding groove.Afterwards, carry out a manufacture procedure of adhesive (molding process), to form a packing colloid, it coats the part outside first groove that is exposed to of substrate, chip, part heat dissipation element and lead foot.Then, remove mould.
In one embodiment of this invention, the external diameter of first end of each lead foot is D1, and the external diameter of second end is D2, and the length of each lead foot is L, and the internal diameter of the opening of each first groove is I1, and the internal diameter of bottom is I2, and the degree of depth of each first groove is A, and
In one embodiment of this invention, each lead foot is the cone that cuts off, and the first corresponding groove is the taper groove that cuts off.
The manufacture method that the present invention proposes a kind of chip-packaging structure is described below.At first, a substrate, at least one chip, a heat dissipation element and a plurality of lead foot are provided, wherein chip configuration is on substrate.Each lead foot is a column, and first end of lead foot is disposed on the substrate and electrically connect with substrate, and second end of lead foot extends to the direction away from substrate, and heat dissipation element is disposed at the surface away from lead foot of substrate.Then, a mould and a plurality of catch ring are provided, mould has a die cavity, and the inner surface of die cavity has a plurality of grooves, and catch ring is arranged in the groove respectively.Then, substrate is disposed in the die cavity of mould, lead foot is inserted in the groove and catch ring is placed on the lead foot respectively and is bearing on the edge of opening of groove.Afterwards, carry out a manufacture procedure of adhesive (moldingprocess), to form a packing colloid, it coats the part outside groove and the catch ring that is exposed to of substrate, chip, part heat dissipation element and lead foot.Then, remove mould.Afterwards, remove catch ring.
In one embodiment of this invention, each catch ring has an opening, and each lead foot runs through the opening of corresponding catch ring, and opening is a polygonal opening or a circular open.
In one embodiment of this invention, catch ring is a circular circulus or a polygonal circulus.
In one embodiment of this invention, the cross sectional shape of catch ring is O shape, ellipse, L shaped, T shape or square.
In one embodiment of this invention, the material of catch ring comprises plastic cement.
Lead foot of the present invention is to be extended by the surface towards away from the direction of substrate of packing colloid, and therefore, creepage distance and space length between second conductive pole and the heat dissipation element are bigger.And the present invention does not need housing of the prior art, so but the area of substrate carries chips is big and size substrate is less.Thus, the cost of substrate is lower.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
Fig. 1 illustrates the profile of the encapsulating structure of existing high-power die.
Fig. 2 A～Fig. 2 B illustrates the processing procedure profile of the chip-packaging structure of Fig. 1.
Fig. 3 A illustrates the profile of the chip-packaging structure of one embodiment of the invention.
Fig. 3 B illustrates the explosive view of the chip-packaging structure of Fig. 3.
Fig. 4 A～Fig. 4 C illustrates the processing procedure profile of the chip-packaging structure of first embodiment of the invention.
Fig. 5 A～Fig. 5 C illustrates the processing procedure profile of the chip-packaging structure of second embodiment of the invention.
Fig. 6 illustrates the top view of the catch ring among Fig. 5 A.
The main element symbol description:
100,300: chip-packaging structure
110,310: substrate
112,114,141,142,312,314,341,342: the surface
120,320: chip
130,410,510: lead foot
132,412,512: the first ends
134,414,514: the second ends
140: housing
143,144,424a, 532: opening
150: silica gel layer
160: enclosing cover
170,360: bonding wire
330: the first conductive poles
332a, 332b: end face
334: holddown groove
334a: first screw thread
336: lateral wall
336a, 524: groove
340: packing colloid
350: the second conductive poles
352: lead foot portion
354: lug boss
354a: second screw thread
356: the stop section
370: conductive layer
410,510: lead foot
416: sidewall
416a: second groove
420,520: mould
421A, 521A: mold
421B, 521B: bed die
422A, 422B, 522A, 522B: inner surface
423,523: die cavity
424: the first grooves
424b: bottom
524a: edge of opening
530: catch ring
B1: width
B2: internal diameter
E: fin
S: sidewall
W: inwall
Embodiment
Fig. 3 A illustrates the profile of the chip-packaging structure of one embodiment of the invention, and Fig. 3 B illustrates the explosive view of the chip-packaging structure of Fig. 3 A.Please be simultaneously with reference to Fig. 3 A and Fig. 3 B, the chip-packaging structure 300 of present embodiment comprises a substrate 310, a plurality of chip 320, a heat dissipation element E, a plurality of first conductive pole 330, a packing colloid 340 and a plurality of second conductive pole 350.
First conductive pole 330 is disposed on the surface 312 of substrate 310, and electrically connects with substrate 310, and the material of first conductive pole 330 for example is copper, aluminium, iron or other electric conducting materials that is fit to.In detail; Can between first conductive pole 330 and substrate 310, dispose a conductive layer 370; And utilize welding, fixed component snapping or adhesion system to electrically connect first conductive pole 330 and substrate 310, and first conductive pole 330 is fixed on the surface 312 of substrate 310.In other words, in the present embodiment, first conductive pole 330 all is disposed on the surface 312 with chip 320.First conductive pole 330 has a lateral wall 336 and the holddown groove 334 of relative both ends of the surface 332a, 332b, connection both ends of the surface 332a, 332b; Wherein an end face 332a is disposed on the surface 312; Other end 332b extends towards the direction away from substrate 310, and holddown groove 334 is arranged between both ends of the surface 332a, the 332b and runs through end face 332b.
Second conductive pole 350 is arranged on the surface 342 and is disposed on first conductive pole 330; And run through packing colloid 340 towards surface 342 away from the direction of substrate 310; And second conductive pole 350 comprises a lead foot portion 352 and a lug boss 354; Lead foot portion 352 is extended by the surface 342 of packing colloid 340 and in order to electrically connect with external circuit (for example circuit board), the lug boss 354 of second conductive pole 350 is fixed in the holddown groove 334 of first conductive pole 330.Particularly; In the present embodiment; The inwall W of the holddown groove 334 of first conductive pole 330 has one first screw thread 334a, and the sidewall S of the lug boss 354 of second conductive pole 350 has the one second screw thread 354a that cooperates with the first screw thread 334a, and the first screw thread 334a is an internal thread; The second screw thread 354a is an external screw thread, and lug boss 354 screws in the holddown groove 334.In other embodiments, the lug boss 354 of second conductive pole 350 is fixed in that mode in the holddown groove 334 of first conductive pole 330 can be that close-fitting connects, trip interlocking or gummed connect.Relevant gummed connected mode promptly disposes an adhesion coating (not illustrating) between the inwall W of lug boss 354 and holddown groove 334, with the inwall W of engagement convex portion 354 with holddown groove 334, the material of adhesion coating can be conducting resinl.
Because the lead foot portion 352 of second conductive pole 350 of the present invention is extended by the surface 342 of packing colloid 340; Heat dissipation element E is arranged on surperficial 342 facing surfaces 341; Therefore; Lead foot portion 352 and the creepage distance and the space length between the heat dissipation element E of second conductive pole 350 are bigger, make the encapsulating structure can be high voltage withstanding and meet safety requirements.
In addition; When avoiding lug boss 354 being screwed in (or insertion) holddown groove 334; Can make 330 rotations of first conductive pole, move or damage substrate 310 by pressure, present embodiment forms a plurality of groove 336a at the lateral wall 336 of first conductive pole 330, and packing colloid 340 is inserted among the groove 336a.Thus, when lug boss 354 screws in (or insertion) holddown groove 334, the processing strength that packing colloid 340 can disperse 354 pairs of holddown grooves 334 of lug boss to be applied.In the present embodiment, groove 336a is a v-depression.In other embodiments, groove 336a can be a circular groove, a half slot or a helical groove.In addition; The lateral wall 336 of first conductive pole 330 can have a convexity (not illustrating); And packing colloid 340 coats aforementioned convexity, so the processing strength that first conductive pole 330 can be applied 354 pairs of holddown grooves 334 of packing colloid 340 dispersion lug bosses by aforementioned convexity.
Moreover; First conductive pole 330 for example is a polygonal cylinder (like the hexagonal cylinder), an oval cylinder or a cylinder; And when first conductive pole 330 is a polygonal cylinder; The processing strength that packing colloid 340 can disperse 354 pairs of holddown grooves 334 of lug boss to be applied, and first conductive pole 330 is screwed out can avoid lug boss 354 to screw in (or insertion) holddown groove 334 time.
In addition; One stop section 356 can be set between lead foot portion 352 and lug boss 354; Stop section 356 directly contacts with the surface 342 of the packing colloid 340 that is positioned at second conductive pole, 350 peripheries; When avoiding lug boss 354 being screwed in (or insertion) holddown groove 334, lead foot portion 352 gets in the holddown groove 334 together with lug boss 354.In detail, the Breadth Maximum B1 of stop section 356 is greater than the internal diameter B2 of holddown groove 334, and therefore, when lug boss 354 was screwed in (or insertion) holddown groove 334, stop section 356 will bear against on the surface 342.
In addition, the production method of relevant present embodiment chip-packaging structure 300 can be earlier first conductive pole 330 to be disposed on the substrate 310, then, carries out manufacture procedure of adhesive, then, second conductive pole 350 is disposed on first conductive pole 330.In other words, second conductive pole 350 can just be disposed at after manufacture procedure of adhesive on first conductive pole 330.Thus, the pollution of the excessive glue in the time of can avoiding the lead foot portion 352 of second conductive pole 350 to receive manufacture procedure of adhesive is so the process rate of the chip-packaging structure 300 of present embodiment is higher and electrical quality is preferable.Also can earlier second conductive pole 350 be disposed on first conductive pole 330, promptly second conductive pole 350 is one-body molded with first conductive pole 330 earlier, carry out manufacture procedure of adhesive again, and following this mode that is directed against proposes several kinds of manufacture methods.
Fig. 4 A～Fig. 4 C illustrates the processing procedure profile of the chip-packaging structure of first embodiment of the invention.At first, please with reference to Fig. 4 A, a substrate 310, a plurality of chip 320, a heat dissipation element E and a plurality of lead foot 410 are provided.The annexation of the substrate 310 of present embodiment, a plurality of chip 320 and heat dissipation element E is identical with the embodiment of Fig. 3 A, so repeat no more in this.And the lead foot 410 of present embodiment has one first end 412 and one second end 414.The external diameter of lead foot 410 is increased progressively to first end 412 by second end 414, and first end 412 is disposed on the surface 312 of substrate 310, and second end 414 extends towards the direction away from substrate 310.
Then, please once more with reference to Fig. 4 A, a mould 420 is provided; Mould 420 has mold 421A and bed die 421B; Mold 421A and bed die 421B combination back forms a die cavity 423 in inside, and die cavity 423 has interior surface opposing 422A, 422B, and inner surface 422A has the first corresponding groove 424 of a plurality of and lead foot 410; First groove 424 has an opening 424a and a bottom 424b, and the internal diameter of first groove 424 is increased progressively to opening 424a by bottom 424b.
Then, please with reference to Fig. 4 B, substrate 310 is disposed in the die cavity 423 of mould 420, so that second end 414 of lead foot 410 is interfered driving fit with the first corresponding groove 424, heat dissipation element E is smooth in inner surface 422B.In the present embodiment, the external diameter of first end 412 of lead foot 410 is D1, and the external diameter of second end 414 is D2, and the length of lead foot 410 is L, and the internal diameter of the opening 424a of first groove 424 is I1, and the internal diameter of bottom 424b is I2, and the degree of depth of first groove 424 is A, and
In other words, the gradient of the sidewall 416 of lead foot 410 can be greater than the gradient of the inwall 424c of first groove 424.Thus, when lead foot 410 inserted first groove 424, the sidewall 416 of lead foot 410 was easy to the inwall 424c driving fit with first groove 424, avoiding in follow-up manufacture procedure of adhesive, in packing colloid overflow to the first groove 424 and pollute mould.
Afterwards; Please once more with reference to Fig. 4 B; Carry out a manufacture procedure of adhesive (molding process), be about to colloid and be filled in the die cavity 423, to form a packing colloid 340 (like Fig. 4 C); It coats the part outside first groove 424 that is exposed to of substrate 310, chip 320, part heat dissipation element E and lead foot 410; Packing colloid 340 has two opposite surfaces 341,342, and wherein a surface 341 exposes the surface away from substrate 310 of heat dissipation element E, and respectively the part of this lead foot 410 is extended by another surface 342 of packing colloid 340.At last, please with reference to Fig. 4 C, remove mould 420.
Owing to when removing mould 420, need peel of mould 420 and lead foot 410, therefore, lead foot 410 can receive a pulling force towards the bottom 424b of first groove 424.For avoiding lead foot 410 come off by the influence of aforementioned pulling force, can form one second groove 416a in the part that is positioned at packing colloid 340 of lead foot 410, and packing colloid 340 is inserted among the second groove 416a.Thus, packing colloid 340 can disperse the suffered pulling force of lead foot 410.In the present embodiment, the second groove 416a can be a conical socket.In other embodiments, the second groove 416a can be a circular groove, a half slot or a helical groove.In addition, in other embodiments, also can form a convexity (not illustrating), and packing colloid 340 coats aforementioned convexity, and make packing colloid 340 disperse the suffered pulling force of lead foot 410 by aforementioned convexity in the part that is positioned at packing colloid 340 of lead foot 410.
Fig. 5 A～Fig. 5 C illustrates the processing procedure profile of the chip-packaging structure of second embodiment of the invention.Fig. 6 illustrates the top view of the catch ring among Fig. 5 A.At first, please with reference to Fig. 5 A, a substrate 310, a plurality of chip 320, a heat dissipation element E and a plurality of lead foot 510 are provided.The annexation of the substrate 310 of present embodiment, a plurality of chip 320 and heat dissipation element E is identical with the embodiment of Fig. 3 A, so repeat no more in this.And the lead foot 510 of present embodiment is the column of a uiform section, for example is a polygonal cylinder or a cylinder.One first end 512 of lead foot 510 is disposed on the surface 312 and with substrate 310 and electrically connects, and the other end 514 of lead foot 510 extends to the direction away from substrate 310.
Then, please once more with reference to Fig. 5 A, a mould 520 and a plurality of catch ring 530 are provided.Mould 520 has mold 521A and bed die 521B, and mold 521A and bed die 521B combination back form a die cavity 523 in inside, and die cavity 523 has interior surface opposing 522A, 522B, and inner surface 522A has a plurality of and lead foot 510 corresponding groove 524.Please with reference to Fig. 6, catch ring 530 has an opening 532, and lead foot 510 is arranged in opening 532, and lead foot 510 and opening 532 be for closely cooperating, and opening 532 is a circular open or a polygonal opening (like square aperture).Catch ring 530 is a circular circulus or a polygonal circulus (like square circulus).It should be noted that Fig. 6 only illustrates and has circular open and be the catch ring 530 of circular circulus, but be not in order to limit the present invention.In other words, but the shape of the circulus of catch ring 530 with and the opening shape combination in any.The cross sectional shape of catch ring 530 for example is O shape, ellipse, L shaped, T shape or square (it is representative that Fig. 5 A only illustrates O shape).The material of catch ring 530 comprises the material that plastic cement or other are suitable for sealing.
Then, please with reference to Fig. 5 B, substrate 310 is disposed in the die cavity 523 of mould 520; The surface 312 of substrate 310 is towards inner surface 522A; Surface 314 is towards inner surface 522B, and heat dissipation element E is smooth in inner surface 522B, and the other end 514 of lead foot 510 is inserted in the corresponding groove 524.Catch ring 530 is placed on the lead foot 510 respectively and is bearing on the edge of opening 524a of groove 524.In other words, catch ring 530 is between lead foot 510 and mould 520, with sealed groove 524.
Afterwards; Please, carry out a manufacture procedure of adhesive, be about to colloid and be filled in the die cavity 523 once more with reference to Fig. 5 B; To form a packing colloid 340 (like Fig. 5 C), it coats the part outside groove 524 and the catch ring 530 that is exposed to of substrate 310, chip 320, part heat dissipation element E and lead foot 510.It should be noted that because catch ring 530 sealed grooves 524, therefore, can avoid packing colloid 340 in manufacture procedure of adhesive overflow to groove 524 in and pollute mould 520, and then the useful life of prolongation mould 520.Then, please with reference to Fig. 5 C, remove mould 520.Afterwards, remove catch ring 530.Mould 520 can be to remove respectively or remove simultaneously with catch ring 530.
In sum, the manufacture method of chip-packaging structure of the present invention and chip-packaging structure has advantage at least:
1. lead foot of the present invention is to be extended by the surface towards away from the direction of substrate of packing colloid, and heat dissipation element E is arranged on the above-mentioned surperficial facing surfaces, and therefore, creepage distance and space length between second conductive pole and the heat dissipation element are bigger.And the present invention does not need housing of the prior art, so but the area of substrate carries chips is big and size substrate is less.Thus, the cost of substrate is lower.
2. second conductive pole of the present invention can just be disposed on first conductive pole after manufacture procedure of adhesive, so the pollution of the excessive glue can avoid the lead foot portion of second conductive pole to receive manufacture procedure of adhesive the time.Therefore, the process rate of chip-packaging structure of the present invention is higher and electrical quality is preferable.
3. in the manufacture method that the present invention proposes, a manufacture procedure of adhesive capable of using is promptly accomplished packing colloid 340, can save existing step of making housing and configuration enclosing cover, reaches the simplification fabrication schedule.
4. the inwall of first groove of the sidewall of lead foot of the present invention and mould all has a gradient.Therefore, when lead foot inserted first groove, the sidewall of lead foot was easy to the inwall driving fit with first groove, avoiding in follow-up manufacture procedure of adhesive, in packing colloid overflow to the first groove and pollute mould, and then prolonged the useful life of mould.
5. because the salable groove of catch ring of the present invention, thus can avoid packing colloid in manufacture procedure of adhesive overflow to groove and pollute mould, and then useful life of prolongation mould.
Though the present invention discloses as above with preferred embodiment; Right its is not that any those skilled in the art are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little modification and perfect, so protection scope of the present invention is when being as the criterion with what claims defined.
Claims (18)
1. chip-packaging structure comprises:
One substrate has a relative first surface and a second surface;
At least one chip is disposed on this first surface of this substrate;
At least one first conductive pole; Have relative both ends of the surface; Wherein an end face is disposed on this first surface of this substrate and with this substrate and electrically connects, and extend towards the direction away from this substrate the other end, between these both ends of the surface a holddown groove is set and it runs through this other end;
One heat dissipation element is disposed on this second surface of this substrate;
One packing colloid coats this substrate, this chip, this heat dissipation element of part and this first conductive pole, and this packing colloid has two opposite surfaces, and wherein a surface exposes the surface away from this substrate of this heat dissipation element; And
At least one second conductive pole be arranged on another surface on these two surfaces of this packing colloid, and this second conductive pole comprises a lead foot portion and a lug boss that this lug boss of this second conductive pole is fixed in this holddown groove of this first conductive pole.
2. chip-packaging structure as claimed in claim 1; It is characterized in that; The inwall of this holddown groove of this first conductive pole has one first screw thread, and the sidewall of this lug boss of this second conductive pole has one second screw thread with this first threaded engagement, and this lug boss screws in this holddown groove.
3. chip-packaging structure as claimed in claim 1; It is characterized in that; This second conductive pole more comprises a stop section, and this stop section is between this lead foot portion and this lug boss, and this stop section directly contacts with this another surface of this packing colloid that is positioned at this second conductive pole periphery.
4. chip-packaging structure as claimed in claim 1 is characterized in that, this lug boss of this second conductive pole is fixed in that mode in this holddown groove of this first conductive pole can be that close-fitting connects, trip interlocking or gummed connect.
5. chip-packaging structure as claimed in claim 1 is characterized in that, this first conductive pole is a polygonal cylinder, an oval cylinder or a cylinder.
6. chip-packaging structure as claimed in claim 1 is characterized in that, the lateral wall of this first conductive pole has at least one groove or at least one convexity, and this packing colloid is inserted in this groove or coating should convexity.
7. chip-packaging structure as claimed in claim 6 is characterized in that, this groove is a v-depression, a circular groove, a half slot or a helical groove.
8. chip-packaging structure comprises:
One substrate has a relative first surface and a second surface;
At least one chip is disposed on this first surface of this substrate;
A plurality of lead foots, respectively this lead foot has one first end and one second end, and respectively the external diameter of this lead foot is increased progressively to first end by second end, and this first end is disposed on this first surface of this substrate, and this second end extends towards the direction away from this substrate;
One heat dissipation element is disposed on this second surface of this substrate; And
One packing colloid; Coat the part of this substrate, this chip, this heat dissipation element of part and those lead foots; This packing colloid has two opposite surfaces; Wherein a surface exposes the surface away from this substrate of this heat dissipation element, and respectively the part of this lead foot is extended by another surface on these two surfaces of this packing colloid.
9. chip-packaging structure as claimed in claim 8 is characterized in that, respectively this lead foot is the cone that cuts off.
10. chip-packaging structure as claimed in claim 8 is characterized in that, respectively the part that is positioned at this packing colloid of this lead foot has a groove or a convexity, and this packing colloid is inserted in this groove or coating should convexity.
11. the manufacture method of a chip-packaging structure comprises:
One substrate, at least one chip, a plurality of lead foot and a heat dissipation element are provided; Wherein this chip configuration is on this substrate; Respectively this lead foot has one first end and one second end, and respectively the external diameter of this lead foot is increased progressively to first end by second end, and this first end is disposed on this substrate; And this second end extends towards the direction away from this substrate, and this heat dissipation element is disposed at the surface away from those lead foots of this substrate;
One mould is provided, and this mould has a die cavity, and the inner surface of this die cavity has a plurality of first grooves, and respectively this first groove has an opening and a bottom, and respectively the internal diameter of this first groove is increased progressively to this opening by this bottom;
This substrate is disposed in this die cavity of this mould, so that respectively this second end of this lead foot is interfered driving fit with this corresponding first groove;
Carry out a manufacture procedure of adhesive, to form a packing colloid, it coats the part outside those first grooves that is exposed to of this substrate, this chip, this heat dissipation element of part and those lead foots; And
Remove this mould.
12. manufacture method as claimed in claim 11 is characterized in that, respectively the external diameter of this first end of this lead foot is D1; And the external diameter of this second end is D2; Respectively the length of this lead foot is L, and respectively the internal diameter of this opening of this first groove is I1, and the internal diameter of this bottom is I2; Respectively the degree of depth of this first groove is A, and
13. manufacture method as claimed in claim 11 is characterized in that, respectively this lead foot is the cone that cuts off, and this corresponding first groove is the taper groove that cuts off.
14. the manufacture method of a chip-packaging structure comprises:
One substrate, at least one chip, a heat dissipation element and a plurality of lead foot are provided; Wherein this chip configuration is on this substrate; Respectively this lead foot is a column; And first end of those lead foots is disposed on this substrate and with this substrate and electrically connects, and second end of this lead foot extends to the direction away from this substrate, and this heat dissipation element is disposed at the surface away from those lead foots of this substrate;
One mould and a plurality of catch ring are provided, and this mould has a die cavity, and the inner surface of this die cavity has a plurality of grooves, and those catch rings are arranged at respectively in those grooves;
This substrate is disposed in this die cavity of this mould, those lead foots are inserted in those grooves and those catch rings are placed on those lead foots respectively and are bearing on the edge of opening of those grooves;
Carry out a manufacture procedure of adhesive, to form a packing colloid, it coats the part outside those grooves and those catch rings that is exposed to of this substrate, this chip, this heat dissipation element of part and those lead foots;
Remove this mould; And
Remove those catch rings.
15. manufacture method as claimed in claim 14 is characterized in that, respectively this catch ring has an opening, and respectively this lead foot runs through this opening of corresponding this catch ring, and this opening is a polygonal opening or a circular open.
16. manufacture method as claimed in claim 14 is characterized in that, this catch ring is a polygonal circulus or a circular circulus.
17. manufacture method as claimed in claim 14 is characterized in that, the cross sectional shape of this catch ring is O shape, ellipse, L shaped, T shape or square.
18. manufacture method as claimed in claim 14 is characterized in that, the material of this catch ring comprises plastic cement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2008101768094A CN101740527B (en) | 2008-11-21 | 2008-11-21 | Chip packaging structure and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101768094A CN101740527B (en) | 2008-11-21 | 2008-11-21 | Chip packaging structure and manufacture method thereof |
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| CN101740527B true CN101740527B (en) | 2012-06-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| NL2023711A (en) * | 2018-12-19 | 2020-07-08 | Shindengen Electric Mfg | Semiconductor device and semiconductor device manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102270616A (en) * | 2011-08-19 | 2011-12-07 | 日月光半导体制造股份有限公司 | Wafer level packaging structure and manufacturing method thereof |
| TWI420627B (en) * | 2011-10-14 | 2013-12-21 | Nan Ya Printed Circuit Board | Pin for semiconductor device |
| CN103531555B (en) * | 2013-10-24 | 2016-01-20 | 江苏宏微科技股份有限公司 | Exempt from the power model of solder terminal |
| CN107785279A (en) * | 2017-10-18 | 2018-03-09 | 天津力芯伟业科技有限公司 | A kind of electronics carbonization silicon |
| CN113224500B (en) * | 2020-01-21 | 2022-12-27 | 华为技术有限公司 | Packaged antenna module, manufacturing method of packaged antenna module and terminal equipment |
| WO2021189877A1 (en) * | 2020-03-23 | 2021-09-30 | 珠海格力电器股份有限公司 | Pin, power device, method for manufacturing power device, and packaging mould |
| EP4053887A1 (en) * | 2021-03-05 | 2022-09-07 | Infineon Technologies AG | Method and device for producing a housing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| NL2023711A (en) * | 2018-12-19 | 2020-07-08 | Shindengen Electric Mfg | Semiconductor device and semiconductor device manufacturing method |
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