CN101739370B - Bus system and operating method thereof - Google Patents
Bus system and operating method thereof Download PDFInfo
- Publication number
- CN101739370B CN101739370B CN 200810174827 CN200810174827A CN101739370B CN 101739370 B CN101739370 B CN 101739370B CN 200810174827 CN200810174827 CN 200810174827 CN 200810174827 A CN200810174827 A CN 200810174827A CN 101739370 B CN101739370 B CN 101739370B
- Authority
- CN
- China
- Prior art keywords
- instruction
- link
- interdependent
- initial order
- newly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Advance Control (AREA)
Abstract
The invention discloses an operating method applied to a non-sequenced executed bus system, which comprises the following steps: linking the instructions using the bus system to form dependent links in sequence according to the dependent limit conditions; and processing the instructions in sequence according to the dependent links.
Description
Technical field
The invention relates to the method for operating of the bus system of non-sequentially (out-of-order) execution, and especially about in the non-bus system of sequentially carrying out, setting up the method for interdependent link according to interdependent restrictive condition.
Background technology
Traditional bus protocol all with sequentially the mode of (in-order) carry out, for example advanced high-effect bus (AHB, Advanced High performance BUS) is namely sequentially carried out according to the sequencing of each instruction.Yet such executive mode has a shortcoming, can incur loss through delay exactly follow-up many data transaction when a larger data trade (transaction) is arranged, and when system is more and more huger, the bus architecture of sequentially carrying out will not apply use.Therefore, at present large-scale system transfers to adopt the bus system of non-sequentially (out-of-order) execution, for example the advanced person extends interface (AXI, AdvancedeXtensible Interface) and open core protocol (OCP, Open Core Protocol) bus system.These non-bus systems of sequentially carrying out can make the master control set (master) on the bus can have more space to go to process the instruction that transmits from bus with slave unit (slave).In the non-bus system of sequentially carrying out, the order of data is not sequentially to arrange, the for example instruction that transmits of the instruction path (commandchannel) by bus system, with the data writing corresponding to this instruction is not sequentially to enter in the slave unit by data writing passage (write-data channel) transmission of bus system, therefore, thread identification code (threadID) or tag recognition code (tagID) just often are used to process these non-sequentially entering and inter-related instruction.Yet, when these thread identification codes or tag recognition code not in order when bus transmits, relevant instruction will sequentially be carried out, thereby easily produced mistake.
Once proposed relevant solution in No. 2007/0067549 case of U.S.'s publication (after this referred to as No. 549 Patent Cases), it adopts traditional first in first out concept to solve.For fear of not finishing writing instruction and with thereafter reading command data danger barriers (datahazard) may occuring of (outstanding), No. 549 Patent Case is temporarily stored in this uncompleted relevant information that writes instruction in the push-up storage, when checking out that its follow-up read operation has the generation of data danger barrier, then suspend this read operation, until this does not finish the read operation of carrying out again after writing instruction and being done in suspending, occur to avoid data danger barrier.Still there are some problems in the method, and for example when this read operation suspended, all read operations after this read operation also suspended execution, even if carry out first them data danger barrier also can not occur.Thereby, if can learn the method that adopts No. 549 patents the usefulness of entire system will be reduced.
Summary of the invention
For addressing the above problem, the present invention proposes a kind of method of operating that is applied to the bus system that non-sequentially (out-of-order) carry out, with the overall efficiency of elevator system, avoid data danger barrier.The method comprises: will use the command chain of bus system to be connected into to have the interdependent link of sequencing according to interdependent restrictive condition; And the processing of those instructions being carried out sequencing according to each interdependent link.
The present invention also proposes a kind of bus system, comprising: instruction registor, and receive and also temporaryly newly to advance instruction, wherein this newly advances instruction and comprises at least a bookmark; And interdependent link generator, be coupled to this instruction registor, produce N interdependent link according to this interdependent restrictive condition that newly advances a command N bookmark, and N is any positive integer; Wherein, this newly to advance each included bookmark of instruction all be to represent that this newly advances instruction and a plurality of previous still unenforced linking relationship that newly advances the sequencing between the instruction.
Description of drawings
Fig. 1 is the process flow diagram according to the method for operating of the bus system of one embodiment of the invention.
Fig. 2 is the calcspar according to the storer scheduler of one embodiment of the invention.
Fig. 3 shows the structure utilize an instruction in the dependent instruction link that single-phase sets up according to restrictive condition.
Fig. 4 is the linking relationship of explanation storer scheduler between each instruction that different time receives.
Fig. 5 shows another structure utilize an instruction in the dependent instruction link that single-phase sets up according to restrictive condition.
Fig. 6 shows again another structure utilize an instruction in the dependent instruction link that single-phase sets up according to restrictive condition.
Fig. 7 shows the structure utilize each instruction in the dependent instruction link that two interdependent restrictive conditions set up.
Fig. 8 is the linking relationship of explanation storer scheduler 200 between each instruction that different time receives.
Fig. 9 is the schematic diagram that comes the data of transmitting on the bus are carried out tracing and debugging according to one embodiment of the invention.
[main element label declaration]
| 110、120、130 | |
200 | The |
| 210 | Instruction |
220 | Interdependent |
| 230 | The Instruction Selection |
240 | Linking relationship removes |
| 300、500、600、700 | Instruction | 310、710、720 | |
| 320、520、620、730 | |
330、530、740、750 | |
| 510 | |
610 | The right of priority mark |
Embodiment
Fig. 1 is the process flow diagram according to the method for operating of the bus system of one embodiment of the invention.The method of operating 100 of bus system comprises the following step:
Step 110: will use a plurality of command chains of this bus system to be connected at least one interdependent link with sequencing according at least one interdependent restrictive condition;
Step 120: those instructions are carried out the processing of this sequencing according to each interdependent link; And
Step 130: reset interdependent link under the executed instruction according to the peer link mark.
Each figure below the method for operating 100 of bus system will be arranged in pairs or groups is described in detail as follows with each embodiment.
Fig. 2 is the calcspar according to the storer scheduler of one embodiment of the invention.Storer scheduler 200 include instruction working storages (request queue) 210, interdependent link generator 220, Instruction Selection device 230 and linking relationship remove device 240.Wherein, interdependent link generator 220 is to be coupled to instruction registor 210, and Instruction Selection device 230 is to be coupled to instruction registor 210, is to be coupled to instruction registor 210 and instruction selector switchs 230 and linking relationship removes device 240.Storer scheduler 200 is to be coupled to the non-bus (not being shown in Fig. 2) of sequentially carrying out, at least one the interdependent link that to use a plurality of instructions of this bus system to be linked into each other to have sequencing according at least one interdependent restrictive condition, select again the instruction of qualified being performed (serve) according to each interdependent link, so that can process those instructions according to this sequencing.
Instruction right and wrong on the bus are passed in order, for fear of mistakes such as generation data danger barriers, some have the instruction of dependence (dependency) to be performed in order, and whether each instruction has dependence each other, must judge from message such as the thread identification code (threadID) of each instruction, the storer page numbers (memory pagenumber).For example, according to bus protocol (bus protocol), each instruction with identical thread identification code (for example the thread identification code is 0) has dependence, and for example between each instruction of the same storer page number of access dependence is also arranged, and this regulation can be avoided the generation of data danger barrier.Therefore, be able to according to thread identification code or the storer page number as interdependent restrictive condition to set up interdependent link, note that, above-mentioned only as the usefulness of example explanation, and those skilled in the art are when being adopted other interdependent restrictive condition to judge the dependence between each instruction.
Fig. 4 is the linking relationship of explanation storer scheduler 200 between each instruction that different time receives.Suppose when time T 5, stored the thread identification code in the instruction registor 210 and be 0 and respectively in time T 0, T1, the instruction R0 (0) that T3 receives, R1 (0), R3 (0), and to have stored the thread identification code be 1 and respectively in time T 2, the instruction R2 (1) that T4 receives, R4 (1), wherein the bookmark of instruction R0 (0) is to illustrate that it does not link to forward any instruction, in other words, it is the initiating terminal of 0 interdependent link (referred to as the first link) for the thread identification code, the bookmark of R1 (0) is to illustrate that it is to be linked at instruction R0 (0) afterwards, the bookmark of R3 (0) is to illustrate that it is to be linked at instruction R1 (0) afterwards, and the end mark of R3 (0) is to illustrate that it is that it is the end of the first link; In addition, the bookmark of instruction R2 (1) is to illustrate that it does not link to forward any instruction, that is, it is the initiating terminal of 1 interdependent link (referred to as the second link) for the thread identification code, the bookmark of R4 (1) is to illustrate that it is to be linked at instruction R2 (1) afterwards, and the end mark of R2 (1) is to illustrate that it is that it is the end of the second link.When time T 5, storer scheduler 200 receive again the thread identification code be 0 newly advance instruction R5, and it is stored among the instruction registor 210.According to interdependent restrictive condition (such as thread identification code 0,1), interdependent link generator 220 is sought the end that the thread identification codes are 0 link, it is instruction R3 (0), make and newly advance the end that instruction R5 is linked in the first link, set the bookmark of instruction R5 for linking to instruction R3 (0) (such as step 110), and set its end mark be first the link end, and the end mark of change directive R3 (0) make its no longer be first the link end.Note that, if the thread identification code of instruction R5 is 1, then interdependent link generator 220 links to the end of the second link to be similar to above-mentioned method with it; If it is identical to there is no the thread identification code of any instruction and instruction R5 in the instruction registor 210, when namely newly advancing instruction R5 and not being inconsistent arbitrary interdependent restrictive condition, the bookmark that interdependent link generator 220 is set instruction R5 makes its initiating terminal that becomes newly-built link, and the end mark of setting instruction R5 makes it become simultaneously the end of newly-built link.
As for carrying out the instruction aspect, Instruction Selection device 230 is selected the qualified instruction that is performed according to being stored in each instruction that not yet is performed in the instruction registor 210 with corresponding interdependent the link, Instruction Selection device 230 must be in the middle of the initial order of each link, picking out one is carried out, such as instruction R0 (0), the qualified instruction R0 (0) that is performed of Instruction Selection device 230 outputs, represent instruction R0 (0) and be performed (such as step 120), linking relationship removes device 240 and then seeks the instruction R1 (0) that links to instruction R0 (0) according to the bookmark of each instruction, bookmark such as instruction R1 (0) is to point out that it is to be linked at instruction R (0) afterwards, then linking relationship removes device 240 and removes instruction R1 (0) and reset the bookmark of instruction R1 (0), makes it replace Instruction Selection device 230 executed instruction R0 (0) and fills vacancies in the proper order the initial order (such as step 130) that becomes the first link.When Instruction Selection device 230 again select be performed instruction the time, then Instruction Selection device 230 must be elected to get instruction R1 (0) as be performed instruction according to the bookmark of instruction R1 (0), and output order R1 (0) is for execution.
Fig. 5 shows another structure utilize an instruction in the dependent instruction link that single-phase sets up according to restrictive condition.The instruction 500 that is stored in instruction registor 210 has a plurality of fields, and start of record mark 510, command content 520 and bookmark 530 note that respectively, and each order of the field of instruction 500 shown in Figure 5 only is the usefulness of explanation, should not be considered as restriction of the present invention.Start mark 510 is to illustrate whether this instruction is the initial order of interdependent link, 520 of command content store the content that this instruction wish is carried out, and bookmark 530 is to indicate this instruction and the linking relationship that is stored in other instruction of instruction registor 210, the first instruction and the second instruction are for example arranged in the bus system, and the bookmark of this first instruction is to point out that this first instruction is to be linked at before this second instruction.Those skilled in the art work as can be under the instruction of the related description that instruction is carried out in interdependent link foundation and the selection of aforementioned instruction 300, carrying out interdependent link with the instruction of instruction 500 forms sets up and selection execution instruction, therefore for the sake of clarity, will repeat no more in this.
Fig. 6 shows again another structure utilize an instruction in the dependent instruction link that single-phase sets up according to restrictive condition.The instruction 600 that is stored in instruction registor 210 has a plurality of fields, records respectively right of priority mark 610 and instruction contents 620, notes that each order of the field of instruction shown in Figure 6 600 only is the usefulness of explanation, should not be considered as restriction of the present invention.Right of priority mark 610 is that this instruction this sequencing in affiliated arbitrary interdependent link is described, and command content 620 is the content that this instruction wish is carried out.Those skilled in the art work as can be under the instruction of the related description that instruction is carried out in interdependent link foundation and the selection of aforementioned instruction 300, carrying out interdependent link with the instruction with instruction 600 forms sets up and selection execution instruction, therefore for the sake of clarity, will repeat no more in this.
The dependence except between each instruction of using single interdependent restrictive condition foundation use bus system, also can set up dependence with a plurality of interdependent restrictive conditions, for example set up dependence according to thread identification code and the storer page number in the lump.Fig. 7 shows the structure utilize each instruction in the dependent instruction link that two interdependent restrictive conditions set up.The instruction 700 that is stored in instruction registor 210 has a plurality of fields, record respectively the first end mark 710, the second end mark 720, command content 730, the first bookmark 740 and the second bookmark 750, note that, each order of the field of instruction 700 shown in Figure 7 only is the usefulness of explanation, should not be considered as restriction of the present invention.The first end mark 710 is to illustrate whether this instruction is the first terminal instruction of complying with link according to the first-phase that first-phase is set up according to restrictive condition (for example thread identification code), the second end mark 720 is to illustrate whether this instruction is the second terminal instruction of complying with link according to the second-phase that second-phase is set up according to restrictive condition (for example storer page number), command content 730 is to store the content that this instruction wish is carried out, the first bookmark 740 be illustrate this instruction be stored in instruction registor 210 other instruction at the linking relationship of first-phase aspect restrictive condition, and the second bookmark 750 be illustrate this instruction be stored in instruction registor 210 other instruction at the linking relationship of second-phase aspect restrictive condition.
Fig. 8 is the linking relationship of explanation storer scheduler 200 between each instruction that different time receives.Suppose when time T 3, stored instruction R0 (0) P0 that receives at time T 0, T1, T2 respectively, R1 (0) P1, R2 (1) P0 in the instruction registor 210.Instruction R0 (0) P0, the thread identification code of R1 (0) P1 is 0, instruction R0 (0) P1, the storer page number of R2 (1) P1 is 0, and the storer page number of instruction R1 (0) P1 is 1, wherein the first bookmark of instruction R0 (0) P0 be explanation its before to have there is no any thread identification code of link be 0 instruction, therefore it is the initial order of 0 interdependent link (referred to as the first link) for the thread identification code, and the second bookmark of instruction R0 (0) P0 illustrates that it before there is no any storer page number of link is 0 instruction, and it is the initial order of 0 interdependent link (linking referred to as second) for the storer page number.
The first bookmark of instruction R1 (0) P1 points out, aspect the interdependent restrictive condition of thread identification code, it is to be linked at after instruction R0 (0) P0, and the first end mark of instruction R1 (0) P1 illustrates that it also is the terminal instruction of the first link; And the second bookmark of instruction R1 (0) P1 is pointed out, aspect the interdependent restrictive condition of the storer page number, it before there is no any storer page number of link is 1 instruction, it is the initial order of 1 interdependent link (referred to as the 3rd link) for the storer page number, and the second end mark of instruction R1 (0) P1 illustrates that it also is the terminal instruction of the 3rd link.
The first bookmark of instruction R2 (1) P0 be explanation its before to have there is no any thread identification code of link be 1 instruction, therefore it is the initial order of 1 interdependent link (referred to as the 4th link) for the thread identification code, and the first end mark of instruction R2 (1) P0 illustrates that it also is the terminal instruction of the 4th link.And the explanation of the second bookmark of instruction R2 (1) P0 is aspect the interdependent restrictive condition of the storer page number, it is to be linked at after instruction R0 (0) P0, and the second end mark of instruction R2 (1) P2 illustrates that it also is the terminal instruction of the second link.
First, second, third and fourth link is four interdependent links that interdependent link generator 220 produces according to the interdependent restrictive condition that newly advances the instruction bookmark, note that, interdependent link generator 220 must produce N interdependent link according to the interdependent restrictive condition that newly advances a command N bookmark, and N is any positive integer, and interdependent link generator 220 more must newly advance the included N of an instruction end mark according to this and represents that this newly advances instruction and is the terminal instruction of this N interdependent link below will describe it in detail newly to advance instruction.
When time T 3, storer scheduler 200 receive again the thread identification code be 0 and the storer page number be 0 instruction R3 (0) P0, and it is stored among the instruction registor 210.According to each interdependent restrictive condition (such as thread identification code 0,1), interdependent link generator 220 is sought the terminal instruction that the thread identification codes are 0 link, be instruction R1 (0) P1, make and newly advance the end that instruction R3 (0) P0 is linked in the first link, set the first bookmark of instruction R3 (0) P0 for linking to instruction R1 (0) P1, and set its first end mark be first the link terminal instruction, and the first end mark of change directive R1 (0) P1 make its no longer be first the link terminal instruction.According to each interdependent restrictive condition (such as the storer page number 0,1), interdependent link generator 220 is sought the terminal instruction that the storer page numbers are 0 link, be instruction R2 (1) P0, make and newly advance the end that instruction R3 (0) P0 is linked in the second link, set instruction R3 (0) P0 the second bookmark for linking to instruction R2 (1) P0, and set its second end mark be second the link terminal instruction, and the second end mark of change directive R2 (1) P2 make its no longer be second the link terminal instruction.
Note that, if it is identical with the thread identification code of newly advancing instruction to there is no any instruction in the instruction registor 210, namely this newly advances instruction when not being inconsistent arbitrary interdependent restrictive condition, then interdependent link generator 220 is set the first bookmark of newly advancing instruction so that it at the initiating terminal that becomes newly-built link aspect the interdependent restrictive condition of thread identification code, and is set and newly advance the first end mark of instruction so that it becomes the end of this newly-built link; If it is identical with the storer page number that newly advances instruction to there is no any instruction in the instruction registor 210, then interdependent link generator 220 is set the second bookmark that newly advances instruction and is made it at the initiating terminal that becomes newly-built link aspect the interdependent restrictive condition of the storer page number, and sets the second end mark that newly advances instruction and make it become the end of this newly-built link.
As for carrying out the instruction aspect, Instruction Selection device 230 is selected the qualified instruction that is performed according to being stored in each instruction that not yet is performed in the instruction registor 210 with a plurality of interdependent links, N the bookmark that the interdependent link of Instruction Selection device 230 interpretations a plurality of (such as N) comprises, judge according to affiliated bookmark whether this instruction is initial order, and find out M initial order of N interdependent link initiating terminal, and pick out one of them and carried out, wherein M initial order comprises all at least a bookmark and represents that it is the initial order that can be performed, and M, N is positive integer, and M is less than N.For example, instruction R0 (0) P0 all is reported to be initial order at the bookmark of (thread identification code and the storer page number) aspect each interdependent restrictive condition, then instruction R0 (0) P0 is the qualified instruction that is performed, instruction R1 (0) P1 then is initial order aspect the storer page number, but be initial order not being aspect the thread identification code, therefore instruction R1 (0) P1 is not the qualified instruction that is performed.In another embodiment, if instruction R1 (0) P1 has majority to be reported to be initial order at the bookmark aspect each interdependent restrictive condition, then instruction R0 (0) P0 also is the qualified instruction that is performed.In another embodiment, if instruction R1 (0) P1 is reported to be initial order at least one bookmark of bookmark aspect each interdependent restrictive condition, then instruction R0 (0) P0 also is the qualified instruction that is performed.Qualified instruction R0 (0) P0 that is performed of presumptive instruction selector switch 230 outputs, linking relationship removes device 240 and then seeks instruction after being linked at instruction R0 (0) P0 aspect each interdependent restrictive condition according to each bookmark of each instruction, aspect the thread identification code, the first bookmark of instruction R1 (0) P1 is to point out that it is to be linked at after instruction R0 (0) P0, linking relationship removes the first bookmark that device 240 is reseted instruction R1 (0) P1, makes it replace the initial order that executed instruction R0 (0) P0 becomes the first link; Aspect the storer page number, the second bookmark of instruction R2 (1) P0 is to point out that it is to be linked at after instruction R0 (0) P0, linking relationship removes the second bookmark that device 240 is reseted instruction R2 (1) P0, makes it replace the initial order that executed instruction R0 (0) P0 becomes the second link.
In addition, instruction 700 must have the form of instruction of being similar to 500, namely have a plurality of start marks of corresponding a plurality of interdependent restrictive conditions and a plurality of bookmarks of corresponding a plurality of interdependent restrictive conditions, and bookmark wherein is that this instruction of explanation is to be linked at before which instruction, those skilled in the art work as can be under the instruction of previous embodiment, understand easily the instruction of this kind form and will how to set up interdependent link and execution, therefore for the sake of clarity, will repeat no more in this.
Moreover, instruction 700 must have the form of instruction of being similar to 600, the a plurality of right of priority marks that namely have corresponding a plurality of interdependent restrictive conditions, and right of priority mark wherein is the sequencing in this instruction of explanation interdependent link of setting up aspect each interdependent restrictive condition, those skilled in the art work as can be under the instruction of previous embodiment, understand easily the instruction of this kind form and will how to set up interdependent link and execution, therefore for the sake of clarity, will repeat no more in this.
Transmit alignment (transfer alignment) in multithreading and the non-bus of sequentially carrying out also is a very difficult job, yet, follow the trail of (debugtracing) if wish is carried out debug to the data of transmitting on the bus, must transmit alignment again can not.One embodiment of the invention are to utilize to set up between instruction the technology of dependence and come that the data of transmitting on the bus are carried out debug and follow the trail of.Fig. 9 carries out the schematic diagram that debug is followed the trail of according to one embodiment of the invention to the data of transmitting on the bus.As shown in the figure, bus has instruction path (command channel) CC, data writing passage (write data channel) WC and response channel (response channel) DC.On instruction path CC, from time T 0 to T5 instruction R0 has appearred respectively to R5, wherein the thread identification code of instruction R0 (0), R5 (0) is 0, the thread identification code of instruction R1 (1), R2 (1), R4 (1) is 1, and the thread identification code of instruction R3 (2) is 2.The instruction that the thread identification code is identical must sequentially be carried out, thereby with the thread identification code as interdependent restrictive condition, when time T 2, debug tracing module (not being shown in Fig. 9) finds that instruction R2 (1) the and instruction R1 (1) on the bus has identical thread identification code, therefore in its instruction registor (not being shown in Fig. 9), set the bookmark of instruction R2 (1) to illustrate that it is to link to instruction R1 (1), the end mark of setting R2 (1) to be illustrating that it is the thread identification code as the terminal instruction of 1 interdependent link (referred to as the first link), and the end mark of reseting instruction R1 (1) is to illustrate that it no longer is the terminal instruction of the first link; When time T 4, the debug tracing module finds that instruction R4 (1) the and instruction R1 (1) on the bus, the thread identification code of instruction R2 (1) are 1, just make instruction R4 (1) become the terminal instruction of the first link according to above-mentioned similar operations, and revise the linking relationship of the first link.
When time T 5, a response data D1 (1) appears in response channel DC, its thread identification code is 1, and do not finish the instruction R1 (1) of (outstanding) in the bus, instruction R2 (1), the thread identification code of instruction R4 (1) is 1, and had to carry out initial order R1 (1) in these three instructions according to aforementioned determining about the method for utilizing end mark and bookmark, therefore can decision instruction R1 (1) be same transaction with response data D1 (1), therefore can finish the data trade of tracking and record trunk by said method.Note that, those skilled in the art work as can be under the instruction of aforementioned each embodiment, utilize a plurality of interdependent restrictive conditions that bus is carried out debug and follow the trail of, perhaps utilize the methods such as relevant start mark, bookmark, right of priority mark that bus is carried out debug and follow the trail of, repeat no more in this.
In sum, embodiments of the invention provide the method for utilizing at least one interdependent restrictive condition to set up dependence between each instruction in the non-multithreading bus system of sequentially carrying out, thereby when relevant treatment is carried out in each instruction, be able to carry out according to the dependence between each instruction the probability that occurs to reduce data danger barrier.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (18)
1. the method for operating of a bus system includes:
Receive and also temporaryly newly to advance instruction, wherein this newly advances instruction and comprises at least a bookmark;
Produce N interdependent link according to this interdependent restrictive condition that newly advances a command N bookmark, and N is any positive integer;
From unenforced M initial order newly advancing to find out the instruction this N interdependent link initiating terminal still, and pick out one of them and carried out, wherein this M initial order comprises that all at least a bookmark represents that this M initial order can carry out, and M is the positive integer less than or equal to N; And
Remove the first performed initial order, and fill vacancies in the proper order at least one new initial order according to the interdependent restrictive condition of this first initial order,
Wherein, this newly to advance each included bookmark of instruction all be to represent that this newly advances instruction and a plurality of previous still unenforced linking relationship that newly advances the sequencing between the instruction.
2. method according to claim 1 also comprises:
According to each interdependent restrictive condition, make and newly advance the end that command chain is connected at least one interdependent link, or newly advance instruction when not being inconsistent arbitrary interdependent restrictive condition at this, this is newly advanced the initiating terminal that instruction is set as newly-built link, and this newly advances instruction and also is simultaneously the end of this newly-built link.
3. method according to claim 1, wherein those instructions comprise an end mark separately at least, in order to represent each instruction whether be under the end of interdependent link.
4. method according to claim 1, wherein when this bookmark showed the first initial order and other instruction all without linking relationship, this first initial order then was the initiating terminal of at least one interdependent link.
5. method according to claim 3, wherein this first initial order comprises one first bookmark at least, in order to point out that this first initial command chain is connected on before this at least one new initial order, or this at least one new initial order comprises one second bookmark at least, is linked at after this first initial order in order to point out this at least one new initial order.
6. method according to claim 1, wherein those instructions comprise a priority flag separately at least, in order to represent each instruction this sequencing in affiliated arbitrary interdependent link.
7. method according to claim 5 wherein produces N interdependent link according to this interdependent restrictive condition that newly advances a command N bookmark, comprising:
Seek the first initial order, wherein the first end mark of comprising of this first initial order represents that this first initial command bits is in the end of first-phase according to link;
To be connected to after this first initial order corresponding to newly the advance command chain of this first-phase according to link;
Set the end that this first-phase is complied with link that is labeled as that this newly advances instruction.
8. method according to claim 7 wherein during according to the initial order of link, is carried out this first initial order for this first-phase when this first bookmark or this second bookmark represent this first initial order.
9. method according to claim 7 also comprises:
Seek this first initial order of expression and be the start mark of this first-phase according to the initial order of link.
10. method according to claim 7 from those unenforced M initial orders newly advancing to find out the instruction this N interdependent link initiating terminal still, and is picked out one of them and is carried out, and comprising:
A plurality of bookmarks that a plurality of interdependent links of interpretation comprise; And
Judge according to those bookmarks whether this first initial order is carried out;
Wherein, those bookmarks are to represent whether this first initial order is the initial order of those interdependent links, and those interdependent links comprise that this first-phase is according to link.
11. method according to claim 10, if wherein those bookmarks all represent this first initial order for this first-phase according to the link initial order, then carry out this first initial order.
12. method according to claim 10 is if wherein this first initial order of the most expression of those bookmarks is then carried out this first initial order for the initial order of this first-phase according to link.
13. method according to claim 1, wherein this interdependent restrictive condition comprise thread identification code, the storer page number and data danger barrier etc. at least one of them.
14. method according to claim 1, wherein this bus system according to this sequencing storer scheduling is carried out in those instructions and carry out debug tracking etc. at least one of them.
15. method according to claim 1 is applied to the non-bus system of sequentially carrying out.
16. a bus system comprises:
Instruction registor receives and also temporaryly newly to advance instruction, and wherein this newly advances instruction and comprises at least a bookmark;
Interdependent link generator is coupled to this instruction registor, produce N interdependent link according to this interdependent restrictive condition that newly advances a command N bookmark, and N is any positive integer;
The Instruction Selection device, be coupled to this instruction registor, in order to from unenforced M initial order newly advancing to find out the instruction this N interdependent link initiating terminal still, and pick out one of them and carried out, wherein this M initial order comprises that all at least a bookmark represents that this M initial order can carry out, and M is the positive integer less than or equal to N; And
Linking relationship removes device, is coupled to this instruction registor and this Instruction Selection device, in order to removing the first performed initial order of this Instruction Selection device, and fills vacancies in the proper order at least one new initial order according to the interdependent restrictive condition of this first initial order,
Wherein, this newly to advance each included bookmark of instruction all be to represent that this newly advances instruction and a plurality of previous still unenforced linking relationship that newly advances the sequencing between the instruction.
17. bus system according to claim 16, wherein this interdependent link generator also newly advances the included N of an instruction end mark according to this and represents that this newly advances instruction and is the terminal instruction of this N interdependent link.
18. the bus system that bus system according to claim 16, right and wrong are sequentially carried out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810174827 CN101739370B (en) | 2008-11-05 | 2008-11-05 | Bus system and operating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810174827 CN101739370B (en) | 2008-11-05 | 2008-11-05 | Bus system and operating method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101739370A CN101739370A (en) | 2010-06-16 |
| CN101739370B true CN101739370B (en) | 2013-04-24 |
Family
ID=42462873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810174827 Active CN101739370B (en) | 2008-11-05 | 2008-11-05 | Bus system and operating method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101739370B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109725245B (en) * | 2017-10-30 | 2021-10-08 | 瑞昱半导体股份有限公司 | Integrated circuit testing device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7320100B2 (en) * | 2003-05-20 | 2008-01-15 | Cray Inc. | Apparatus and method for memory with bit swapping on the fly and testing |
-
2008
- 2008-11-05 CN CN 200810174827 patent/CN101739370B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7320100B2 (en) * | 2003-05-20 | 2008-01-15 | Cray Inc. | Apparatus and method for memory with bit swapping on the fly and testing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101739370A (en) | 2010-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109036493A (en) | A kind of NAND Flash controller with error detection correction mechanism | |
| US7904618B2 (en) | Buffer managing method and buffer managing apparatus | |
| CN103246625B (en) | A kind of method of data and address sharing pin self-adaptative adjustment memory access granularity | |
| JP2021504842A (en) | Address / Command Chip Synchronous Autonomous Data Chip Address Sequencer for Distributed Buffer Memory Systems | |
| CN102622192B (en) | Weak correlation multiport parallel store controller | |
| CN102750257B (en) | On-chip multi-core shared storage controller based on access information scheduling | |
| CN100524538C (en) | Testing apparatus and testing method | |
| CN1329809C (en) | Controller of magnetic disk array and its working method | |
| CN108156823A (en) | The access method and controller of a kind of flash media | |
| CN106503020A (en) | Daily record data processing method and processing device | |
| CN103488565B (en) | A kind of distributed real-time testing system test data collection method | |
| JPWO2010001464A1 (en) | Search device and search method | |
| US20130339638A1 (en) | Status polling of memory devices using an independent status bus | |
| CN104615684A (en) | Mass data communication concurrent processing method and system | |
| CN106773954A (en) | A kind of operating mode control method in microcontroller chip | |
| CN108845829A (en) | Method for executing system register access instruction | |
| CN101281513A (en) | Stream processor IP core based on Avalon | |
| TWI385529B (en) | Bus system and operation method thereof | |
| CN101739370B (en) | Bus system and operating method thereof | |
| CN109656868B (en) | Memory data transfer method between CPU and GPU | |
| CN104035898B (en) | A kind of memory access system based on VLIW type processors | |
| JP2001195353A (en) | Dma transfer system | |
| CN104615458B (en) | A kind of method and system based on json data format module loadings | |
| CN107329807A (en) | Data delay treating method and apparatus, computer-readable recording medium | |
| KR20130048821A (en) | Semiconductor system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |