CN101738796B - Active matrix liquid crystal display and liquid crystal display panel - Google Patents
Active matrix liquid crystal display and liquid crystal display panel Download PDFInfo
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- CN101738796B CN101738796B CN 200810178237 CN200810178237A CN101738796B CN 101738796 B CN101738796 B CN 101738796B CN 200810178237 CN200810178237 CN 200810178237 CN 200810178237 A CN200810178237 A CN 200810178237A CN 101738796 B CN101738796 B CN 101738796B
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 45
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- 239000010409 thin film Substances 0.000 claims description 12
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Abstract
The invention discloses an active matrix liquid crystal display, which comprises a scanner driver and a liquid crystal display panel. The scanner driver is used for outputting a scan driving signal and a compensation signal. When the level of the scan driving signal changes, the level of the compensation signal performs reverse phase change according to the change of the level of the scan driving signal. The liquid crystal display panel comprises a pixel unit, a scan line and a compensation signal line. The pixel unit comprises an active block and a liquid crystal capacitor. The scan line is used for transmitting the scan driving signal to control the active block and the liquid crystal capacitor. The compensation signal line is adjacent to the scan line, and is used for transmitting the compensation signal to reduce the feed through voltage.
Description
Technical field
The present invention relates to a kind of display and display panel, and particularly relate to a kind of active matrix liquid crystal display and display panels.
Background technology
Being widely used and comprising multiple pattern of liquid crystal display.A kind of common liquid crystal display is active matrix liquid crystal display (Active Matrix Liquid Crysta lDisplay, AMLCD).
Traditionally, in the driving process of active matrix liquid crystal display, via sweep trace, transmit sweep signal to the transistor that is arranged in display panel, carry out conducting or end this transistor, to reach the purpose that drives display panel.In more detail, when sweep signal when enabling to there is high level, transistor turns, now, liquid crystal capacitance will be charged and be adjusted pixel voltage according to data voltage, and under the driving of this pixel voltage, makes corresponding pixel show corresponding gray level.When sweep signal transfers disable to and while having low level, the transistor cut-off, now liquid crystal capacitance does not recharge, and can keep stored electric charge, so that corresponding pixel shows corresponding gray level constantly.
Yet, when the level of sweep signal changes, for example, while changing into the low level of disable by the high level enabled, will produce and wear voltage (feed through voltage) then.At this, wear under the impact of satisfying voltage, pixel voltage will depart from original level, makes the shown gray level of liquid crystal capacitance produce mistake.Therefore, how to reduce and wear then voltage, improve the correctness of display gray scale, be one of direction of endeavouring of industry always.
Japanese patent application JP6018851A is and the immediate prior art file of the present invention.
Summary of the invention
The present invention relates to a kind of active matrix liquid crystal display and display panels thereof, can reduce and wear voltage then, and can improve the correctness of display gray scale.
According to a first aspect of the invention, provide a kind of active matrix liquid crystal display, comprising:
Scanner driver, drive signal and compensating signal in order to output scanning; And
Display panels comprises:
Pixel cell, include source component and liquid crystal capacitance;
Sweep trace, in order to transmit described scanning drive signal, to control described active block and described liquid crystal capacitance;
The compensating signal line, adjacent to described sweep trace, wear voltage then in order to transmit described compensating signal with reduction;
It is characterized in that, described display panels also comprises:
The first channel layer, be arranged on described sweep trace; And
The second channel layer, be arranged on described compensating signal line, so that have a stray capacitance between described compensating signal line and described pixel cell;
Data line, be coupled to drain electrode via described the first channel layer;
Wherein, when the level of described scanning drive signal changes to end described active block, the level of described compensating signal carries out anti-phase variation according to the variation of the level of described scanning drive signal
;
Wherein said the first channel layer and described drain electrode partly overlap, and overlapping with described data line part, and described the second channel layer and described drain electrode partly overlap, and not overlapping with described data line part.
According to a second aspect of the invention, provide a kind of display panels, comprising:
Pixel electrode;
Drain electrode, be electrically connected to described pixel electrode;
The public electrode wiring, overlapping with described pixel electrode part;
It is characterized in that, described display panels also comprises:
The compensating signal line, not overlapping with described pixel electrode, and partly overlap with described drain electrode, described compensating signal line is adjacent to described sweep trace, in order to transmit compensating signal;
Sweep trace, not overlapping with described pixel electrode, and partly overlap with described drain electrode, in order to transmit scanning drive signal to control active block;
The first channel layer, be arranged on described sweep trace;
Data line, be coupled to described drain electrode via described the first channel layer; And
The second channel layer, be arranged on described compensating signal line, not overlapping with described data line part;
There is a stray capacitance between wherein said compensating signal line and described pixel electrode, when the level of described scanning drive signal changes with conducting or ends described active block, the level of described compensating signal carries out anti-phase variation according to the variation of the level of described scanning drive signal, with reduction, wears tunnel voltage.
The accompanying drawing explanation
For above and other objects of the present invention, feature, advantage are become apparent more, by reference to the accompanying drawings embodiment is elaborated, in the accompanying drawings:
Fig. 1 means the schematic diagram according to the active matrix liquid crystal display of the embodiment of the present invention;
A kind of equivalent circuit diagram of the pixel cell of Fig. 2 presentation graphs 1;
Fig. 3 A means to be positioned at when voltage is then worn in reduction according to the embodiment of the present invention a kind of sequential chart of the multi-signal on display panels;
Fig. 3 B means to be positioned at when voltage is then worn in reduction according to the embodiment of the present invention the another kind of sequential chart of the multi-signal on display panels;
Fig. 4 means the schematic diagram according to a kind of layout of pixel cell of the display panels of one embodiment of the invention; And
Fig. 5 means the schematic diagram according to the another kind of layout of pixel cell of the display panels of one embodiment of the invention.
[primary clustering symbol description]
100: active matrix liquid crystal display
120: scanner driver
140: display panels
SB: substrate
D: data line
G: sweep trace
GC: compensating signal line
P: pixel cell
PE: pixel electrode
Sg: scanning drive signal
Sgc: compensating signal
Vd: data voltage
Vn: pixel voltage
Embodiment
With reference to Fig. 1, it means the active matrix liquid crystal display (Active according to one embodiment of the invention
3NTD63352Matrix Liquid Crysta lDisplay, AMLCD) schematic diagram.Active matrix liquid crystal display 100 comprises scanner driver 120 and display panels 140.Scanner driver 120 is in order to export anti-phase in fact each other scanning drive signal Sg and compensating signal Sgc.Display panel 140 at least comprises pixel cell P, sweep trace G and compensating signal line GC.Sweep trace G is controlled by scanning drive signal Sg to enable pixel cell P.Compensating signal line GC adjacent, parallel is in sweep trace G, and compensating signal line GC, in order to transmit compensating signal Sgc, wears voltage (Feed Through Voltage) then with reduction.
With reference to Fig. 2, a kind of equivalent circuit diagram of the pixel cell P of its presentation graphs 1.In this embodiment, pixel cell P includes source component, liquid crystal capacitance Clc and storage capacitors Cst.Active block is for example transistor T.In practice, transistor T is for example N-type thin film transistor (TFT) (N-type TFT) or P type thin film transistor (TFT) (P-type TFT).Transistor T is connected to liquid crystal capacitance Clc and storage capacitors Cst by data line D.When scanning drive signal Sg is high level, controlled sweep trace G can turn-on transistor T.The transistor T of conducting is sent to liquid crystal capacitance Clc and storage capacitors Cst by the data voltage Vd on data line D.Liquid crystal capacitance Clc and storage capacitors Cst according to data voltage Vd to be charged, to produce corresponding pixel voltage Vn on pixel electrode PE.
Traditionally, this pixel voltage Vn can be subject to the impact of the stray capacitance Cgs between sweep trace G and pixel electrode PE.That is to say, when the level of scanning drive signal Sg changes, for example, while changing into low level by high level, scanning drive signal Sg can produce and wear the size of satisfying voltage and affecting pixel voltage Vn via stray capacitance Cgs.
In the liquid crystal display proposed at the present embodiment, due to compensating signal line GC adjacent, parallel in sweep trace G, so pixel voltage Vn also can be subject to stray capacitance Cgcs between compensating signal line GC and pixel electrode PE impact.And, when the level of scanning drive signal Sg changes, the level of compensating signal Sgc also can change.Now compensating signal Sgc also can affect pixel electrode PE via stray capacitance Cgs.That is to say, in an embodiment of the present invention, can be when scanning drive signal Sg drives pixel cell P, transmit compensating signal Sgc by scanner driver 120 and reduce while affected by scanning drive signal Sg the voltage then of wearing produced.
The following describes to reduce and wear the principle of voltage then.Continuation is with reference to Fig. 2.Traditionally, wearing the formula of voltage Vp ' then is:
Wherein, Cgs is expressed as the capacitance of the stray capacitance Cgs between sweep trace G and pixel electrode PE; Δ Vg is expressed as the variation of the voltage level of the scanning drive signal Sg that sweep trace G transmits; Cgs Δ Vg is the storage electric charge that pixel electrode PE increases; Ctotal is illustrated in the equivalent capacitance value on pixel electrode PE.Here, Ctotal is expressed as the summation of the capacitance of stray capacitance Cgs, liquid crystal capacitance Clc and storage capacitors Cst.
Therefore in the present embodiment, owing to having used compensating signal line Gc, wear the formula of voltage Vp then and be:
Similarly symbol is as described in equation 1.Different from equation 1, wherein, Cgcs is expressed as the capacitance of the stray capacitance Cgcs between compensating signal line GC and pixel electrode PE; Δ Vgc is expressed as the variation of the voltage level of the compensating signal Sgc that compensating signal line GC transmits; Cgs Δ Vg+Cgcs Δ Vgc is the storage electric charge that pixel electrode PE increases; And the Ctotal here is expressed as the summation of the capacitance of stray capacitance Cgs and Cgcs, liquid crystal capacitance Clc and storage capacitors Cst.
From equation 2, wear voltage Vp then if will reduce, can make the numerical value of Cgs Δ Vg+Cgcs Δ Vgc the smaller the better.Preferably, make Cgs Δ Vg+Cgcs Δ Vgc=0.In an embodiment of the present invention, use anti-phase each other scanning drive signal Sg and compensating signal Sgc, make the polarity of the voltage level variation Δ Vgc of compensating signal Sgc, contrary with the polarity of the voltage level variation Δ Vg of scanning drive signal Sg, to reduce the numerical value of Cgs Δ Vg+Cgcs Δ Vgc, and can reach to reduce, wear the purpose of voltage then.
Below with two examples, illustrate how embodiments of the invention reduce and wear then voltage.In first example, the active block of Fig. 2 (transistor T) is the N-type thin film transistor (TFT).With reference to Fig. 3 A, it means to be positioned at when voltage is then worn in reduction according to one embodiment of the invention a kind of sequential chart of the multi-signal on display panels 140.Scanning drive signal Sg changes between the first voltage V1 and second voltage V2, and the first voltage V1 is greater than second voltage V2.Like this, when scanning drive signal Sg cut-off N-type thin film transistor (TFT), what produce wears voltage Vp then and can make pixel voltage Vn be dragged down, as shown in dotted line DL1.
Compensating signal Sgc changes between tertiary voltage V3 and the 4th voltage V4, and the 4th voltage V4 is greater than tertiary voltage V3.Scanning drive signal Sg is converted to second voltage V2 time point t0 by the first voltage V1 is identical in fact with the time point t1 that compensating signal Sgc is converted to the 4th voltage V4 by tertiary voltage V3.That is to say, in period t, it is for example the first voltage V1 of high level that scanning drive signal Sg has, and compensating signal Sgc is for example for having low level tertiary voltage V3.And time point t0(in this embodiment t0 equal t1) time, scanning drive signal Sg for example has low level second voltage V2 transferring to, compensating signal Sgc transfers the 4th voltage V4 that for example has high level to.
Due to the first voltage V1 higher than second voltage V2(V1 V2), therefore the voltage level variation Δ Vg of scanning drive signal Sg is on the occasion of (Δ Vg=V1-V2 > 0), and due to the 4th voltage V4 higher than tertiary voltage V3(V4 V3), thereby compensating signal Sgc voltage level variation Δ Vgc is negative value (Δ Vgc=V3-V4<0).Because Δ Vg is contrary with the polarity of Δ Vgc, therefore generally speaking, the numerical value of Cgs Δ Vg+Cgcs Δ Vgc can diminish.Therefore, wear that then voltage Vp(is shown in dotted line) will reduce, preferably, make Cgs Δ Vg+Cgcs Δ Vgc become the numerical value that approaches zero, so that wear then voltage Vp close to null value.
In the second example, different from the first example, the active block of Fig. 2 (transistor T) is P type thin film transistor (TFT).With reference to body 3B, it means to be positioned at when voltage is then worn in reduction according to one embodiment of the invention the another kind of sequential chart of the multi-signal on display panels 140.Owing to using P type thin film transistor (TFT), therefore, in this embodiment, the voltage when voltage of scanning drive signal Sg when conducting (turn on) P type thin film transistor (TFT) can be less than cut-off (turn off) P type thin film transistor (TFT).That is to say, in this embodiment, different from first example is, the first voltage V1 of scanning drive signal Sg is less than second voltage V2, like this, and when scanning drive signal Sg cut-off P type thin film transistor (TFT), what produce wears then voltage Vp and can make pixel voltage Vn be drawn high, as shown in dotted line DL2.
The 4th voltage V4 of compensating signal Sgc is less than tertiary voltage V3.And be similar to first example, by compensating signal Sgc when the time point t0, while being scanning drive signal Sg cut-off P type thin film transistor (TFT), according to the variation of the level of scanning drive signal Sg and carry out anti-phase variation, make Δ Vg contrary with the polarity of Δ Vgc, reduce the numerical value of Cgs Δ Vg+Cgcs Δ Vgc.Like this, wear that then voltage Vp(is shown in dotted line) will reduce, preferably, make Cgs Δ Vg+Cgcs Δ Vgc become the numerical value that approaches zero, so that wear then voltage Vp close to null value.
In the present embodiment, the time point t0 of take is same as in fact time point t1 as the example explanation, yet also is not limited to this, and time point t0 and t1 also can be different, and both differ a period of time.For instance, in other embodiments, scanning drive signal Sg is converted to the time point t0 of second voltage V2 by the first voltage V1, be converted to the time point t1 of the 4th voltage V4 by tertiary voltage V3 with compensating signal Sgc, differs and approximately is less than 0.5 micro-(micron) second.
And in the present embodiment, the first voltage V1 is the voltage that is enough to make the active block conducting, and second voltage V2 is the voltage that is enough to make the active block cut-off.Generally speaking, when scanning drive signal Sg changes to end active block (as the transistor T of Fig. 2), the situation of wearing voltage influence pixel voltage then now is the most serious.Therefore, in the present embodiment, by when the time point t0, when transistor T will be cut off, make compensating signal Sgc and the anti-phase variation of scanning drive signal Sg, improve and wear voltage then.Yet, also be not limited to this, as long as can be when scanning drive signal Sg controls (conducting or cut-off) transistor T, change accordingly the level of the voltage that compensating signal Sgc transmits, improve and wear the problem of voltage then, all in protection scope of the present invention.
Below further illustrate the layout of display panels 140 of the present invention.With reference to Fig. 4, it means the schematic diagram according to a kind of layout of the pixel cell P of the display panels 140 of one embodiment of the invention.In Fig. 4, display panels 140 comprises pixel electrode PE, drain electrode (drain electrode) DE, public electrode wiring COM, compensating signal line GC, sweep trace G, the first channel layer CH1, the second channel layer CH2 and data line D.Drain electrode DE is expressed as the transistor T that is connected to Fig. 1 and the electrode between pixel electrode PE, this electrode is called as drain electrode DE in embodiments of the present invention, yet also be not limited to this, the electrode be connected between transistor T and pixel electrode PE also can be called as source electrode (source electrode), need to understand, title used herein is just in order to explanation, not in order to limit the present invention.Drain electrode DE is electrically connected to pixel electrode PE, for example via through hole (via) VIA, is electrically connected to pixel electrode PE.The first channel layer CH1 is arranged on sweep trace G.The second channel layer CH2 is arranged on compensating signal line GC.Data line D is coupled to drain electrode DE via the first channel layer CH1.
In the present embodiment, public electrode wiring COM and pixel electrode PE partly overlap.Sweep trace G is not overlapping with pixel electrode PE, and partly overlaps with drain electrode DE.Compensating signal line GC is not overlapping with pixel electrode PE, and partly overlaps with drain electrode DE.The first channel layer CH1 and drain electrode DE partly overlap, and partly overlap with data line D, and the second channel layer CH2 and drain electrode DE partly overlap, and with data line D, do not partly overlap.
Because the first channel layer CH1 is positioned on sweep trace G, and partly overlap with the drain electrode DE that is electrically connected to pixel electrode PE, therefore, between sweep trace G and pixel electrode PE, can there is stray capacitance Cgs as shown in Figure 2.Similarly, because the second channel layer CH2 is positioned on compensating signal line GC, and partly overlap with the drain electrode DE that is electrically connected to pixel electrode PE, therefore, between compensating signal line GC and pixel electrode PE, can there is stray capacitance Cgcs as shown in Figure 2.Like this, can, by transmit the different signal of the signal online transmitted from scanning on compensating signal line GC, with reduction, wear the effect of voltage then.The signal that sweep trace G and compensating signal line GC transmit and reduction are worn the reason of voltage then and are specified in above stated specification, thereby no longer repeat here.
In addition, different from the second channel layer CH2, the first channel layer CH1 also partly overlaps with data line D, and may there is extra stray capacitance, therefore, preferably, in the display panels proposed at embodiments of the invention, design makes the equivalent resistance of sweep trace G be greater than the equivalent resistance of compensating signal line GC.Like this, can make the width of partial-compensation signal wire GC be less than the width of sweep trace G, so that the equivalent resistance of sweep trace is greater than the equivalent resistance of compensating signal line.For instance, as shown in Figure 4, the width of sweep trace G is W1, and the width of partial-compensation signal wire GC is W2, wherein W2<W1.And, preferably, use the first channel layer CH1 like the property class with the second channel layer CH2, so that the capacitance of stray capacitance Cgcs equals stray capacitance Cgs.For instance, for example can make sweep trace and compensating signal line be made by same gold-tinted processing procedure (process), and sweep trace and the material of compensating signal line be identical metal material, so that both have similar characteristic.
The above-mentioned width by change sweep trace G and compensating signal line GC reaches the purpose of adjusting resistance, yet also is not limited to this.Also can configure by the material with different sweep trace G and compensating signal line GC, make the equivalent resistance of sweep trace G be greater than the equivalent resistance of compensating signal line GC.
In addition, in the example shown in Fig. 4, compensating signal line GC connects up between COM and sweep trace G at public electrode, yet also is not limited to this.With reference to Fig. 5, it means the schematic diagram according to another layout of the display panels 140 of one embodiment of the invention.In this embodiment, sweep trace G is between public electrode wiring COM and compensating signal line GC.Like this, also can reach to reduce by compensating signal line GC and wear the purpose of voltage then.
The disclosed active matrix liquid crystal display of the above embodiment of the present invention and display panels, by using adjacent, parallel in the compensating signal line of sweep trace, and transmit with the anti-phase compensating signal in scanning drive signal, can effectively reduce and wear voltage then, and can improve the correctness of display gray scale.
In sum, although the present invention by preferred embodiment openly as above, so it is not in order to limit the present invention.The general technical staff of the technical field of the invention, without departing from the spirit and scope of the present invention, can make various changes and modification.Therefore, protection scope of the present invention is limited by the accompanying claims.
Claims (19)
1. an active matrix liquid crystal display comprises:
Scanner driver, drive signal and compensating signal in order to output scanning; And display panels, comprising:
Pixel cell, include source component and liquid crystal capacitance;
Sweep trace, in order to transmit described scanning drive signal, to control described active block and described liquid crystal capacitance;
The compensating signal line, adjacent to described sweep trace, wear voltage then in order to transmit described compensating signal with reduction;
It is characterized in that, described display panels also comprises:
The first channel layer, be arranged on described sweep trace; And
The second channel layer, be arranged on described compensating signal line, so that have a stray capacitance between described compensating signal line and described pixel cell;
Data line, be coupled to drain electrode via described the first channel layer;
Wherein, when the level of described scanning drive signal changes to end described active block, the level of described compensating signal carries out anti-phase variation according to the variation of the level of described scanning drive signal
;
Wherein said the first channel layer and described drain electrode partly overlap, and overlapping with described data line part, and described the second channel layer and described drain electrode partly overlap, and not overlapping with described data line part.
2. active matrix liquid crystal display according to claim 1, wherein said scanning drive signal changes between the first voltage and second voltage, described the first voltage is greater than described second voltage, described compensating signal changes between tertiary voltage and the 4th voltage, and described the 4th voltage is greater than described tertiary voltage;
Wherein when described scanning drive signal by described the first voltage transitions, be described second voltage when ending described active block, described compensating signal is converted to described the 4th voltage by described tertiary voltage.
3. active matrix liquid crystal display according to claim 2, wherein said active block is the N-type thin film transistor (TFT).
4. active matrix liquid crystal display according to claim 2, the time point that the time point that wherein said scanning drive signal is described second voltage by described the first voltage transitions and described compensating signal are converted to described the 4th voltage by described tertiary voltage differs and is less than 0.5 microsecond.
5. active matrix liquid crystal display according to claim 2, the time point that wherein said scanning drive signal is described second voltage by described the first voltage transitions is identical in fact with the time point that described compensating signal is converted to described the 4th voltage by described tertiary voltage.
6. according to claim 1 a described active matrix liquid crystal display, wherein said scanning drive signal changes between the first voltage and second voltage, described the first voltage is less than described second voltage, described compensating signal changes between tertiary voltage and the 4th voltage, and described the 4th voltage is less than described tertiary voltage;
Wherein when described scanning drive signal by described the first voltage transitions, be described second voltage when ending described active block, described compensating signal is converted to described the 4th voltage by described tertiary voltage.
7. active matrix liquid crystal display according to claim 6, wherein said active block is P type thin film transistor (TFT) (P type TFT).
8. active matrix liquid crystal display according to claim 6, the time point that the time point that wherein said scanning drive signal is described second voltage by described the first voltage transitions and described compensating signal are converted to described the 4th voltage by described tertiary voltage differs and is less than 0.5 microsecond.
9. active matrix liquid crystal display according to claim 6, the time point that wherein said scanning drive signal is described second voltage by described the first voltage transitions is identical in fact with the time point that described compensating signal is converted to described the 4th voltage by described tertiary voltage.
10. active matrix liquid crystal display according to claim 1, wherein, when the level of described scanning drive signal changes with the described active block of conducting, the level of described compensating signal carries out anti-phase variation according to the variation of the level of described scanning drive signal.
11. active matrix liquid crystal display according to claim 1, wherein said scanner driver, in order to export anti-phase in fact each other described scanning drive signal and described compensating signal;
Wherein said sweep trace, be controlled by described scanning drive signal and enable described pixel cell; And wherein said compensating signal line, adjacent, parallel is in described sweep trace.
12. a display panels comprises:
Pixel electrode;
Drain electrode, be electrically connected to described pixel electrode;
The public electrode wiring, overlapping with described pixel electrode part;
It is characterized in that, described display panels also comprises:
The compensating signal line, not overlapping with described pixel electrode, and partly overlap with described drain electrode, described compensating signal line is adjacent to described sweep trace, in order to transmit compensating signal;
Sweep trace, not overlapping with described pixel electrode, and partly overlap with described drain electrode, in order to transmit scanning drive signal to control active block;
The first channel layer, be arranged on described sweep trace;
Data line, be coupled to described drain electrode via described the first channel layer; And
The second channel layer, be arranged on described compensating signal line, not overlapping with described data line part;
There is a stray capacitance between wherein said compensating signal line and described pixel electrode, when the level of described scanning drive signal changes with conducting or ends described active block, the level of described compensating signal carries out anti-phase variation according to the variation of the level of described scanning drive signal, with reduction, wears tunnel voltage.
13. display panels according to claim 12,
Wherein said the first channel layer and described drain electrode partly overlap, and overlapping with described data line part, and described the second channel layer and described drain electrode partly overlap, and not overlapping with described data line part.
14. display panels according to claim 12, the equivalent resistance of wherein said sweep trace is greater than the equivalent resistance of described compensating signal line.
15. display panels according to claim 14, the partial width of wherein said compensating signal line is less than the width of described sweep trace, so that the equivalent resistance of described sweep trace is greater than the equivalent resistance of described compensating signal line.
16. display panels according to claim 12, wherein said sweep trace is between described public electrode wiring and described compensating signal line.
17. display panels according to claim 12, wherein said compensating signal line is between described public electrode wiring and described sweep trace.
18. display panels according to claim 12, wherein said sweep trace and described compensating signal line are made by same gold-tinted processing procedure.
19. display panels according to claim 12, wherein said sweep trace and the material of described compensating signal line are identical metal material.
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| CN 200810178237 CN101738796B (en) | 2008-11-17 | 2008-11-17 | Active matrix liquid crystal display and liquid crystal display panel |
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| CN 200810178237 CN101738796B (en) | 2008-11-17 | 2008-11-17 | Active matrix liquid crystal display and liquid crystal display panel |
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| CN102087844A (en) * | 2011-02-24 | 2011-06-08 | 华映视讯（吴江）有限公司 | Compensation circuit of liquid crystal display panel |
| CN102332455B (en) * | 2011-09-19 | 2013-01-23 | 福建华映显示科技有限公司 | Active component array substrate and display panel |
| CN103488019B (en) * | 2013-09-25 | 2016-08-10 | 京东方科技集团股份有限公司 | A kind of array base palte and driving method, display device |
| CN104991363A (en) * | 2015-07-17 | 2015-10-21 | 深圳市华星光电技术有限公司 | Compensation feedback voltage pixel unit circuit |
| CN105842947A (en) * | 2016-05-27 | 2016-08-10 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN110751929B (en) | 2019-11-29 | 2022-12-02 | 厦门天马微电子有限公司 | Display panel and display device |
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