CN101728351B - Layout of bonding pads - Google Patents

Layout of bonding pads Download PDF

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Publication number
CN101728351B
CN101728351B CN2008101697436A CN200810169743A CN101728351B CN 101728351 B CN101728351 B CN 101728351B CN 2008101697436 A CN2008101697436 A CN 2008101697436A CN 200810169743 A CN200810169743 A CN 200810169743A CN 101728351 B CN101728351 B CN 101728351B
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China
Prior art keywords
layout
bonding pads
connection pad
perforation
circuit board
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Expired - Fee Related
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CN2008101697436A
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Chinese (zh)
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CN101728351A (en
Inventor
韦启锌
范文纲
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RUGAO QIRUN SPORTS ARTICLES CO., LTD.
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Inventec Corp
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Abstract

The present invention discloses a layout of bonding pads, which is applied to a circuit board. The layout of the bonding pads comprises a plurality of first bonding pads, a plurality of second bonding pads, a plurality of first through holes, a plurality of second through holes, a plurality of first traces and a plurality of second traces, wherein the first and second bonding pads and the first and second through holes are all arranged on the circuit board in a matrix mode. The first bonding pad of the ith column and the jth row is set to be Xi,j and the second bonding pad of the gth column and the hth row is set to be Yg,h, wherein Ym,n is positioned in an area encircled by Xm,n, Xm+1,n, Xm,n+1 and Xm+1,n+1, and m and n are positive integers. The first through hole of the ath column and the bth row is set to be Ra,b and the second through hole of the pth column and the qth row is set to be Sq,p, wherein Rm+1,n is positioned in an area encircled by Xm+1,n, Xm+1,n+1 and Ym,n; and Sm,n is positioned in an area encircled by Xm,n, Xm,n+1 and Ym,n. The first traces are connected with the Xm,n and Rm,n respectively, while the second traces are connected with Ym,n and Sm,n respectively.

Description

Layout of bonding pads
Technical field
The invention relates to a kind of layout of bonding pads, and particularly relevant for a kind of layout of bonding pads with unit element transmission path.
Background technology
Along with the usefulness of integrated circuit (IC) chip (integrated circuit chip) constantly increases, electronic signal transmitting speed in integrated circuit (IC) chip also little by little promotes.At present, in order to improve constantly the requirement of data transmission bauds in response to the up-to-date communication technology, the data-signal speed on the circuit board has reached 5Gbps (Giga bit persecond), and can rise to more than the 10Gbps in future.
Yet, when these electronic signals are transmitted with the high speed of Gpbs, as the coupling assembling that connects electronic signal, for example interlayer connector (Mezzanine connector) or interlayer Connection Card (Mezzanine card), the mode of the circuit arrangement that it is inner just has influence on the transmission of overall signal easily.Thereby in the design of circuit-board laying-out, often need impedance (Impedance), the transmission attenuation of circuit, crosstalk (Cross talk) or reference layer factors such as (Reference layer) is taken into account, avoiding making loading error occurring because of circuit layout is improper, and then cause system's shakiness or data transmission error.
Summary of the invention
The invention provides a kind of layout of bonding pads, its signal bonding pad and ground connection connection pad have the minimum transfer path, make layout of bonding pads be suitable for transmit high-speed signals.
The present invention proposes a kind of layout of bonding pads, is applicable to a circuit board.This layout of bonding pads comprises a plurality of first connection pads, a plurality of second connection pad, a plurality of first perforation, a plurality of second perforation, a plurality of first trace and a plurality of second trace.First connection pad, second connection pad, first perforation and second perforation all are disposed on the circuit board with matrix-style.Making first connection pad of i row (row) j capable (column) is X I, j, it is Y that g is listed as the second capable connection pad of h G, h, Y wherein M, nBe positioned at X M, n, X M+1, n, X M, n+1And X M+1, n+1In the zone that is surrounded, m, n are positive integer.Making a be listed as the first capable perforation of b is R A, b, R wherein M+1, nBe positioned at X M+1, n, X M+1, n+1And Y M, nIn the zone that is surrounded.Making p be listed as the second capable perforation of q is S P, q, S wherein M, nBe positioned at X M, n, X M, n+1And Y M, nIn the zone that is surrounded.First trace connects X respectively M, nWith R M, n, and second trace connects Y respectively M, nWith S M, n
In one embodiment of this invention, the above-mentioned first connection pad X M, nWith the second connection pad Y M, nOne of them be signal bonding pad, and wherein another is the ground connection connection pad.
In one embodiment of this invention, above-mentioned circuit board is electrically connected at a connector via layout of bonding pads, and this connector is interlayer connector (Mezzanine connector).
In one embodiment of this invention, above-mentioned each first connection pad X M, nAnd each adjacent second connection pad Y M, nBe electrically coupled to connector.
In one embodiment of this invention, above-mentioned each first trace and each second trace are an acute angle in fact.
In one embodiment of this invention, above-mentioned each first perforation R M, nIn fact with each second connection pad Y M, n, Y M+1, nBe located along the same line.
In one embodiment of this invention, above-mentioned each second perforation S M, nIn fact with each second connection pad Y M, n, Y M+1, nBe located along the same line.
In one embodiment of this invention, above-mentioned circuit board comprises many high-speed-differentials to line, is electrically connected to these second perforations respectively.
The present invention's layout of bonding pads, owing to having beeline between first perforation that is connected to first connection pad and second connection pad respectively and second perforation, make win connection pad and second connection pad be able to shortest path respectively and connector electrically connects, reduce by this that high speed signal is decayed or factor such as interference in transmission course, make steady signal transmission.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the schematic diagram of a kind of layout of bonding pads of one embodiment of the invention.
Fig. 2 is the partial enlarged drawing of Fig. 1 layout of bonding pads.
Fig. 3 is that Fig. 1 layout of bonding pads and high-speed-differential are to the allocation plan of line at circuit board.
Embodiment
Fig. 1 is the schematic diagram of a kind of layout of bonding pads of one embodiment of the invention.Fig. 2 is the partial enlarged drawing of Fig. 1 layout of bonding pads.Please also refer to Fig. 1 and Fig. 2, layout of bonding pads 100 is applicable to a circuit board 200.This layout of bonding pads 100 comprises a plurality of first connection pads 110, a plurality of second connection pad 120, a plurality of first perforation 130, a plurality of second perforation 140, a plurality of first trace 150 and a plurality of second trace 160.It should be noted that these first connection pads 110, second connection pad 120, first perforation 130 and second perforation 140 all are disposed on the circuit board 200 with matrix-style.
In the present embodiment, make first connection pad 110 of i row (row) j capable (column) be X I, j, g is listed as the second capable connection pad 120 of h and is Y G, h, Y wherein M, nBe positioned at X M, n, X M+1, n, X M, n+1And X M+1, n+1In the zone that is surrounded, and m, n are positive integer.In other words, first connection pad 110 interlocks each other with second connection pad, 120 formed matrixes and does not overlap.Moreover, make a be listed as the first capable perforation 130 of b and be R A, b, R wherein M+1, nBe arranged in first connection pad, 110 matrix X M+1, n, X M+1, n+1And Y in second connection pad, 120 matrixes M, nIn the zone that is surrounded, that is first perforation 130 is configured in the delta-shaped region that arbitrarily adjacent two first connection pads 110 and one second connection pad 120 surrounded.
Moreover, make p be listed as the second capable perforation 140 of q and be S P, q, S wherein M, nBe arranged in first connection pad, 110 matrix X M, n, X M, n+1And Y in second connection pad, 120 matrixes M, nIn the zone that is surrounded, that is second perforation 140 is disposed in the delta-shaped region that second connection pad 120 of two first arbitrarily adjacent connection pads 110 and next column surrounded.In addition, first trace 150 connects first connection pad, 110 matrix X respectively M, nWith first perforation, 130 matrix R M, n, and second trace 160 connects second connection pad, 120 matrix Y respectively M, nWith second perforation, 140 matrix S M, n
In layout of bonding pads 100 of the present invention, by with R in first perforation, 130 matrixes M+1, nBe disposed at X in the matrix of first connection pad 110 M+1, n, X M+1, n+1And Y in the matrix of second connection pad 120 M, nIn the zone that is surrounded, and with S in second perforation, 140 matrixes M, nBe disposed at X in the matrix of first connection pad 110 M, n, X M, n+1And Y in the matrix of second connection pad 120 M, nIn the zone that is surrounded.It is minimum that this measure makes the distance between first perforation 130 and second perforation 140, is minimum via the signal transmission path of first perforation 130 and second perforation 140 respectively to guarantee first connection pad 110 and second connection pad 120.Therefore, circuit board 200 is suitable for transmit high-speed signals by this layout of bonding pads 100, and need not worry to cause transmission attenuation because of transmission path is long or crosstalk etc. to influence the situation of signal transmission and take place.
Explanation further again, in the layout of bonding pads 100 of the present invention, first connection pad 110 is a signal bonding pad, and second connection pad 120 is the ground connection connection pad, and make circuit board 200 be electrically connected at a connector (not illustrating) by this.In the present embodiment, connector for example is an interlayer connector, with the coffret as high speed signal, wherein, in the present embodiment, is positioned at matrix Y M, n First connection pad 110 be adjacent and be positioned at matrix X M, n Second connection pad 120 be electrically coupled to connector.Yet the present invention does not limit the functional configuration of first connection pad 110 and second connection pad 120, and among another embodiment that does not illustrate, first connection pad 110 is the ground connection connection pad in the present invention, and second connection pad 120 is a signal bonding pad.
In the present embodiment, have the shortest signal transmission path respectively in order to make first connection pad 110 and second connection pad 120, therefore first trace 140 and second trace 150 are an acute angle in fact.In other words, matrix R M, nOn first perforation 130 in fact with matrix Y M, n, Y M+1, nOn second connection pad 120 be located along the same line and matrix S M, nOn second perforation 140 in fact with matrix Y M, n, Y M+1, nOn second connection pad 120 be located along the same line.This measure makes the trace 140 of winning be oblique configuration in these matrixes, and second trace 150 then is positioned at delegation with second connection pad 120 and is directly to configuration.Therefore, layout of bonding pads 100 of the present invention makes win perforation 130 and second perforation 140 have beeline to each other, has the shortest signal transmission path when allowing first connection pad 110 and second connection pad 120 be electrically connected to connector respectively.
Fig. 3 is that Fig. 1 layout of bonding pads and high-speed-differential are to the allocation plan of line at circuit board.Please refer to Fig. 3, circuit board 200 comprises that many high-speed-differentials are connected to second perforation 140 of layout of bonding pads 100 of the present invention to line 210, have electrically connected circuit board 200 and connector by this.In the present embodiment, because circuit board 200 adopts these layout of bonding pads 100, therefore when the designer carries out high-speed-differential to the configuration of line 210, all can be according to original live width and line-spacing cabling, and need not change allocation position and the trend of high-speed-differential to line 210.This measure makes high-speed-differential can keep directly to cabling line 210, thereby causes transmission signals disturbed because of line impedance when having avoided transmission.
In sum, layout of bonding pads of the present invention is located along the same line by first perforation, second perforation and second connection pad, makes win trace and second trace be an acute angle, and then first trace presents oblique configuration in layout of bonding pads, and second trace is for directly to configuration.This measure makes win perforation and second perforation have beeline each other, and makes win connection pad and second connection pad have the shortest path that is connected to connector respectively.Therefore, layout of bonding pads of the present invention has avoided the holding wire of connector and the distance of protective wire on circuit board increases and cause signal to strengthen with reference to return path, that is signal can stably transmit the possibility of having avoided the signal generation to crosstalk or decay.
Moreover when circuit board carried out high-speed-differential to the configuration of line, this layout of bonding pads also can avoid changing the move towards configuration of high-speed-differential to line, and it is still kept directly to cabling, used and avoided causing signal transmission errors because of transfer impedance changes.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.

Claims (9)

1. a layout of bonding pads is applicable to a circuit board, and this layout of bonding pads comprises:
A plurality of first connection pads are disposed on this circuit board with matrix-style, and to make i be listed as the first capable connection pad of j be X I, j
A plurality of second connection pads are disposed on this circuit board with matrix-style, and to make g be listed as the second capable connection pad of h be Y G, h, Y wherein M, nBe positioned at X M, n, X M+1, n, X M, n+1And X M+1, n+1In the zone that is surrounded, and m for the row, n for row, m, n are positive integer;
A plurality of first perforations are disposed on this circuit board with matrix-style, and to make a be listed as the first capable perforation of b be R A, b, R wherein M+1, nBe positioned at X M+1, n, X M+1, n+1And Y M, nIn the zone that is surrounded;
Many first traces connect X respectively M, nWith R M, n
A plurality of second perforations are disposed on this circuit board with matrix-style, and to make p be listed as the second capable perforation of q be S P, q, S wherein M, nBe positioned at X M, n, X M, n+1And Y M, nIn the zone that is surrounded; And
Many second traces connect Y respectively M, nWith S M, n
2. layout of bonding pads as claimed in claim 1 is characterized in that, this first connection pad X M, nWith this second connection pad Y M, nOne of them be signal bonding pad, and wherein another is the ground connection connection pad.
3. layout of bonding pads as claimed in claim 1 is characterized in that this circuit board is electrically connected at a connector via this layout of bonding pads.
4. layout of bonding pads as claimed in claim 3 is characterized in that, respectively this first connection pad X M, nAnd adjacent respectively this second connection pad Y M, nBe electrically coupled to this connector.
5. layout of bonding pads as claimed in claim 3 is characterized in that, this connector is the interlayer connector.
6. layout of bonding pads as claimed in claim 1 is characterized in that, respectively this first trace is an acute angle with this second trace respectively.
7. layout of bonding pads as claimed in claim 6 is characterized in that, respectively this first perforation R M, nWith this second connection pad Y respectively M, n, Y M+1, nBe located along the same line.
8. layout of bonding pads as claimed in claim 6 is characterized in that, respectively this second perforation S M, nWith this second connection pad Y respectively M, n, Y M+1, nBe located along the same line.
9. layout of bonding pads as claimed in claim 1 is characterized in that, this circuit board comprises many high-speed-differentials to line, is electrically connected to these second perforations respectively.
CN2008101697436A 2008-10-16 2008-10-16 Layout of bonding pads Expired - Fee Related CN101728351B (en)

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Application Number Priority Date Filing Date Title
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CN101728351B true CN101728351B (en) 2011-07-20

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Publication number Priority date Publication date Assignee Title
CN111739807B (en) 2020-08-06 2020-11-24 上海肇观电子科技有限公司 Wiring design method, wiring structure and flip chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006056473A2 (en) * 2004-11-29 2006-06-01 Fci Improved matched-impedance surface-mount technology footprints
CN101111127A (en) * 2006-07-17 2008-01-23 英业达股份有限公司 Wiring method and system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006056473A2 (en) * 2004-11-29 2006-06-01 Fci Improved matched-impedance surface-mount technology footprints
CN101111127A (en) * 2006-07-17 2008-01-23 英业达股份有限公司 Wiring method and system

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