CN101728333A - Manufacturing method of array substrate - Google Patents
Manufacturing method of array substrate Download PDFInfo
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- CN101728333A CN101728333A CN200810167527A CN200810167527A CN101728333A CN 101728333 A CN101728333 A CN 101728333A CN 200810167527 A CN200810167527 A CN 200810167527A CN 200810167527 A CN200810167527 A CN 200810167527A CN 101728333 A CN101728333 A CN 101728333A
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- array base
- base palte
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Abstract
The invention provides a manufacturing method of an array substrate, which at least comprises the following steps: forming a plurality of metal blocks in a first region and a second region on a substrate; sequentially forming an insulating layer and a semiconductor layer on the substrate, and covering the insulating layer and the semiconductor layer on metal blocks; coating a first photoresist layer on the substrate, and covering the first photoresist layer on the semiconductor layer and the metal blocks below the semiconductor layer; forming a first photoresist pattern and a second photoresist pattern above the metal blocks by using a half-tone photomask; removing the second photoresist pattern and the semiconductor layer and the insulating layer below the second photoresist pattern for exposing the metal blocks in the second region; reserving the first photoresist pattern and removing the residual first photoresist layer; removing the exposed semiconductor layer which is not covered by the first photoresist pattern; and forming a source electrode and a drain electrode on the semiconductor layer in the first region.
Description
Technical field
The present invention is about a kind of manufacture method of array base palte, particularly about a kind of manufacture method that reduces the array base palte of contact hole key size loss.
Background technology
Along with scientific and technological progress, the LCD of multinomial advantage such as have that power saving, the no width of cloth are penetrated, volume is little, low power consumption, flat square, high-res, image quality are stable, traditional iconoscope screen (being called for short CRT) of monopolizing the status for original place has brought greatest impact, especially now various information products as: products such as mobile phone, mobile computer, digital camera, PDA, LCD screen are more and more universal, also make the demand of LCD (LCD) promote greatly.
LCD mainly comprises a display panels and a backlight module (backlightmodule), wherein display panels is made of a colored filter substrate (color filter), a thin-film transistor array base-plate (TFT array substrate) and the liquid crystal layer that is disposed between this two substrates, and backlight module is in order to provide this liquid crystal panel required area source, so that LCD reaches the effect of demonstration.
See also Fig. 1, be the structure vertical view of the thin-film transistor of known technology.LCD has the array type pixel cell of a plurality of marshallings, each pixel cell is made of a pixel electrode 10 and a thin-film transistor 12, and wherein thin-film transistor 12 includes a grid (not icon), a channel layer 122, one source pole 124 and a drain electrode 126.Wherein, channel layer is covered in the grid top, and has a passage 128 between source electrode 124 and the drain electrode 126.Though grid is not with icon display, itself and scanning linear 14 electrically connect self-evident, and source electrode 124 electrically connects data wire 16, and drain electrode 126 is done an electric connection with pixel electrode 10.Wherein, thin-film transistor 12 is used for the switch module as the liquid crystal display pixel unit.
But; in thin-film transistor manufacturing process; regular meeting is because drain electrode and problems such as source channel (SD channel) processing procedure is residual; make the pollutant of some metal particles or conduction after finishing etching and manufacturing process for cleaning; still remain in the passage place of thin-film transistor; produce point defect, cause source electrode in the thin-film transistor and passage between the drain electrode situation that is short-circuited, the effect of destruction thin-film transistor control switch.
See also Fig. 2 A to Fig. 2 H, be the flow chart of the corresponding processing procedure of known array base palte.At present, in the making of base plate of array in active mode, generally via the processing procedure of five roads or four road micro-photographing process, below with thin film transistor region, pixel region and the sectional view in electrode tip subarea that is disposed at the scan line peripheral circuit as explanation.
At first, shown in Fig. 2 A, use sputter plated film modes such as (sputter) and use the first road light shield (not shown) chromium, barium, huge, aluminium, copper, molybdenum or its alloy, selectivity forms a plurality of metal blocks on the surface of glass substrate 2, as the first metal layer 21, with as scan line and grid.
Then use plated film modes such as plasma chemical vapor deposition (CVD), sputter, shown in Fig. 2 B, form an insulating barrier 22, semi-conductor layer 23, one second metal level 24 and a photoresist layer PR in regular turn.Then, utilize the second road light shield HM with the first photoresistance pattern P R of photoresist layer PR exposure with the different thickness of formation unexposed portion, complete exposed portion and halftone exposure part
1, shown in Fig. 2 C.
Then, with the first photoresistance pattern P R
1Be shielding, utilize plasma to carry out the ashing (Ashing) of photoresistance and general dry-etching mode, then impose wet etching processing procedure etching second metal level and form source electrode, drain electrode in regular turn with the etching semiconductor layer, that is, carry out separating of source electrode and drain electrode.Then, remove the first photoresistance pattern P R
1, shown in Fig. 2 D.
Then, shown in Fig. 2 E, utilizing the organic photoresistance 25 of coating photonasty acrylic acid series, is a flatness layer, uses so that the surface of array base palte becomes smooth.
Shown in Fig. 2 F, then, use the 3rd road light shield (not shown), organic photoresistance 25 of ashing (ashing) part photonasty acrylic acid series and insulating barrier 22 make the first metal layer 21 and second metal level, 24 parts expose to arrive the first metal layer 21, second metal level 24.Then, utilize sputtering method or rubbing method etc. to form nesa coating 26 in whole lining of glass substrate.Nesa coating 26 generally is to use tin indium oxide metal oxide films such as (ITO).
Then, use the 4th light shield (not shown), form shown in Fig. 2 G the second photoresistance pattern P R
2Be shielding selective etch nesa coating 26, carry out the patterning of pixel electrode.Then, shown in Fig. 2 H, remove the second photoresistance pattern P R not
2, glass substrate 2 just becomes base plate of array in active mode.
Array base palte that mode is according to this obtained and colored filter substrate are fitted and are made into liquid crystal panel, and then assembling backlight module and drive circuit are to constitute various liquid crystal indicators.
In order to make base plate of array in active mode, above-mentioned manufacture method needs four road light shields, make the processing procedure lead time (lead time) elongate, expose to the open air in the ashing reaction because of planarization film again as the bottom of pixel electrode, have bigger thickness loss, so contact hole has bigger key size loss, and when making contact hole, because second metal level is in the micro-photographing process of flatness layer, after finishing, development exposes, cover again before the nesa coating if at experience one dry ecthing procedure, drain electrode will suffer long plasma bombardment with the source electrode surface, and cause the blemish that drains with source electrode (second metal level) easily, and will influence the contact impedance and the tack of second metal level and nesa coating, making becomes the essential factor that yield reduces.
Therefore the invention provides the manufacture method of array basal plate, utilize a halftoning light shield processing procedure and corresponding change to make flow process, make array base palte can reduce the processing procedure time, and lower the loss of contact hole critical size.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of array base palte, utilizes a halftoning light shield processing procedure and corresponding change to make flow process, with the minimizing processing procedure time, and the loss of lowering the contact hole critical size.
The invention provides a kind of manufacture method of array base palte, its step comprises at least: form a plurality of metal blocks in a suprabasil first area and second area; In substrate, form an insulating barrier and semi-conductor layer in regular turn, and be covered on above-mentioned a plurality of metal blocks; Be coated with one first photoresist layer in substrate, and cover on the metal blocks of semiconductor layer and below thereof; Utilize a halftoning light shield above metal blocks, to form one first photoresistance pattern and one second photoresistance pattern; Remove the semiconductor layer and the insulating barrier of the second photoresistance pattern and below thereof, in order to expose the metal blocks in the second area; Keep the first photoresistance pattern, and remove remaining first photoresist layer; Remove the semiconductor layer that is not exposed to the open air by the first photoresistance pattern covers; An and formation one source pole and a drain electrode on the semiconductor layer of first area.
Therefore, the manufacturing method of array base plate of LCD provided by the present invention is that the making flow process is done a change and utilized the etching that exposes of halftoning light shield, makes second metal level not need to pass through etching again, and can directly plate nesa coating, and yield is improved; In addition, processing procedure of the present invention all carries out in same vacuum cavity, does not need vacuum breaker to move in another vacuum cavity and reacts, and can shorten the overall process time so reduce handling time.
Description of drawings
Fig. 1 is the structural representation of the thin-film transistor of known technology;
Fig. 2 A to Fig. 2 H is the processing flow figure in known array base palte cross section; And
Fig. 3 A to Fig. 3 I is the processing flow figure in one embodiment of the invention array base palte cross section.
[primary clustering symbol description]
10 pixel electrodes, 12 thin-film transistors
14 scanning linears, 16 data wires
312 grids, 122,331 channel layers
124,341 source electrodes, 126,342 drain electrodes
128 passages, 2 glass substrates
21,31 the first metal layers, 22,32 insulating barriers
23,33 semiconductor layers, 24,34 second metal levels
3 substrates, 35 flatness layers
36 pixel electrodes, 310 common electrodes
332 ohmic contact layer HM
1The halftoning light shield
M
3The 3rd light shield PR photoresist layer
PR
1The first photoresistance pattern P R
2The second photoresistance pattern
PR
3The 3rd photoresistance pattern
Embodiment
The relative position relation of technology contents coupling unit of the present invention and the architectural feature of display floater do to be described below with the sectional view of its thin film transistor region and its terminal region on the array base palte, all the other are same as the prior art, so do not add to give unnecessary details.
Please refer to Fig. 3 A to Fig. 3 I, be the processing flow figure of one embodiment of the invention array base palte cross section.At first, as shown in Figure 3A, provide a substrate 3 earlier, its substrate is a transparent insulation substrate, and its material can be glass, quartz or plastics etc.Then sputter one metal material is in substrate 3, form a first metal layer 31 in substrate 3 upper surfaces, then, be coated with a photoresist layer and utilize one first light shield to do exposure, etching, with patterning the first metal layer 31, form a plurality of metal blocks such as a common electrode 310 and a grid 312 in the upper surface of substrate 3.
And the material of common electrode 310 and grid 312 can be conductive single layer or multiple layer metal or its alloy, as aluminium (Al), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW) or its alloy etc.As shown in FIG., will with the first area thin film transistor region below, second area is that terminal region is as explanation; Wherein second area more can comprise capacitance structure, | inner electrostatic defending ring (inner short-ring) or an exterior protection electrostatic ring (outer short-ring) structure, promptly the metal blocks common electrode 310 in the second area (the first metal layer 31) can utilize successive process to reach effect separately to form different assemblies.
Shown in Fig. 3 B, an insulating barrier 32 is formed on common electrode 310 and the metal blocks such as plural number such as gate line 312 grades.Then, a channel layer 331 is deposited on the insulating barrier 32, and an ohmic contact layer 332 is deposited on the channel layer 331; Wherein, channel layer 331 can be considered semi-conductor layer 33 with ohmic contact layer 332, is arranged at insulating barrier 32 tops.
Then, shown in Fig. 3 C, a photoresist layer PR is formed on the semiconductor layer 33.Wherein, photoresist layer PR can form by rotary coating (spin coating) or non-rotating coating modes such as (Spinless coating).Subsequently, with a halftoning light shield HM
1(also can be described as the pellicle light shield) exposes, etching, with patterning photoresist layer PR, according to halftoning light shield HM
1Characteristic exposure region can be divided into first exposure region, second exposure region and the 3rd exposure region.
According to above-mentioned first exposure region of distinguishing, second exposure region and the 3rd exposure region, shown in contrast Fig. 3 D, wherein first exposure region is made a general reference TFT regions, its pairing halftoning light shield HM
1For hiding the district, so the formed first photoresistance pattern P R behind the patterning
1Be unexposed portion, have the thicker photoresist layer PR of projection.
Second exposure region general reference second area, i.e. portion of terminal, capacitance structure, inner electrostatic defending ring or exterior protection electrostatic ring regional structure, its pairing halftoning light shield HM
1Be penetrating region, so the formed second photoresistance pattern P R behind the patterning
2Be complete exposed part, form a recessed and thin photoresist layer PR.
Part beyond the 3rd exposure region general reference first area and the second area, i.e. pixel region, its pairing halftoning light shield HM
1Be half penetrating region,, form an interior thickness (compared to the first photoresistance pattern P R so formed the 3rd photoresistance pattern is a halftoning exposed portion behind the patterning
1And the second photoresistance pattern P R
2Thickness) photoresist layer PR.
Shown in Fig. 3 E, the photoresist layer PR that etching has exposed in successive process, and remove the second photoresistance pattern P R
2And the semiconductor layer 33 of below part and insulating barrier 32, to expose the common electrode 310 in the second area.
Then, shown in Fig. 3 F, utilize the ashing processing procedure, with the first photoresistance pattern P R
1Outside residue photoresist layer PR remove, be about to the 3rd photoresistance pattern P R
3Utilize ashing reaction that it is removed.And part semiconductor layer 33 etching that continue not covered by the photoresistance pattern remove, and form shown in Fig. 3 G.
Subsequently, the photoresistance pattern is removed, and in the first area, deposit one second metal level 34, utilize one second light shield (not shown), to form an one source pole 341 and a drain electrode 342 its second metal level, 34 patternings; Wherein, forming source electrode 341 and draining 342 o'clock, the ohmic contact layer 332 between source electrode 341 and drain electrode 342 can be removed.
Shown in Fig. 3 H, in substrate 3 coatings one flatness layer 35, wherein flatness layer 35 can be made with the acrylic acid series organic material.Utilize one the 3rd light shield M again
3With its flatness layer 35 patternings, and utilize little shadow to make to run through flatness layer 35, to expose common electrode 310 and drain electrode 342 to form a plurality of contact holes; Wherein, in little shadow is made, carry out a blanching step (I-line bleaching) and a cross-linking reaction (Curing) more in regular turn, can make significantly to promote its mechanical strength, acid and alkali-resistance ability and weatherability etc. by the flatness layer 35 inner tridimensional networks that form.
Moreover, shown in Fig. 3 I, on the concavo-convex surface texture of this flatness layer 35, be coated with a nesa coating, for example: metal oxides such as indium oxide, and utilize one the 4th light shield with the electrically conducting transparent film patterning, form pixel electrode 36; Wherein, pixel electrode 36 electrically connects with drain electrode 342 by contact hole and common electrode 310.Hereto, the basic module of the array base palte of LCD is roughly constructed and is finished.
Subsequently, through fitting with colored filter substrate and being made into liquid crystal panel, then assembling backlight module and drive circuit are to constitute various liquid crystal indicators.
According to above-mentioned explanation, can understand technical characterictic of the present invention and be:
(1) do not need to expose to the open air in the ashing reaction for a long time because of flatness layer of the present invention, and it does not need through one dry ecthing procedure, so can reduce the thickness loss of planar film, the phenomenon generation (crosstalk) that can reduce the key size loss of contact hole and influence adjacent domain brightness.
(2) in addition, the blemish that can avoid second metal level to be caused by ion bombardment makes that contact impedance and the tack between second metal level and the nesa coating can effectively be controlled.
(3) for the integral array basal plate making process, can reduce the etch process of making contact hole, shorten the output time.Processing procedure of the present invention all carries out in same vacuum cavity, does not need vacuum breaker to move in another vacuum cavity and reacts, and can shorten the overall process time so reduce handling time.
Though the present invention illustrates as above with preferred embodiments, so it is not only to terminate in the foregoing description in order to limit the present invention's spirit with the invention entity.Usually know the knowledgeable to having in the affiliated technical field, when understanding and utilize other assembly or mode to produce identical effect easily.Be with, the modification of being done in not breaking away from spirit of the present invention and scope all should be included in claims.
Claims (15)
1. the manufacture method of an array base palte is characterized in that, comprises at least:
Form a plurality of metal blocks in a suprabasil first area and second area;
In this substrate, form an insulating barrier and semi-conductor layer in regular turn, and be covered on those metal blocks;
Be coated with a photoresist layer in this substrate, and be covered on those metal blocks of this semiconductor layer and below thereof;
Utilize a halftoning light shield above those metal blocks, to form one first photoresistance pattern and one second photoresistance pattern;
Remove this semiconductor layer and this insulating barrier of this second photoresistance pattern and below thereof, in order to expose those metal blocks in this second area;
Keep this photoresistance pattern, and remove remaining this photoresist layer;
Remove this semiconductor layer that is not exposed to the open air by this photoresistance pattern covers; And
On this semiconductor layer of this first area, form an one source pole and a drain electrode.
2. the manufacture method of array base palte as claimed in claim 1 is characterized in that, one first exposure area and one second exposure area that this first photoresistance pattern and this second photoresistance pattern see through respectively in this first area and this second area form.。
3. the manufacture method of array base palte as claimed in claim 2 is characterized in that, also comprises to form this semiconductor layer top between this first exposure area and this second exposure area, one the 3rd exposure area, in order to form the 3rd photoresistance pattern.
4. the manufacture method of array base palte as claimed in claim 3 is characterized in that, this first exposure area is a unexposed portion, and this second exposure area is that a complete exposed portion and the 3rd exposure area are a halftoning exposed portion.
5. the manufacture method of array base palte as claimed in claim 3, it is characterized in that, this halftoning light shield is used so that the pairing photoresistance pattern in those exposure areas has different thickness, wherein the thickness of this first photoresistance pattern is greater than the 3rd photoresistance pattern, and this second photoresistance pattern is less than the 3rd photoresistance pattern.
6. the manufacture method of array base palte as claimed in claim 3 is characterized in that, removes after the step of this second photoresistance pattern, and remaining this photoresist layer that is removed is the 3rd photoresistance pattern, and its employed method is an ashing processing procedure.
7. the manufacture method of array base palte as claimed in claim 1 is characterized in that, this second area utilizes this metal blocks to contact with a pixel electrode.
8. the manufacture method of array base palte as claimed in claim 1 is characterized in that, this metal blocks of this second area forms a capacitance structure.
9. the manufacture method of array base palte as claimed in claim 1 is characterized in that, after forming this source electrode and draining, also comprises the following step:
Formation one comprises the flatness layer of a plurality of contact holes on this substrate; And
Form a pixel electrode on this flatness layer, wherein this metal blocks of this pixel electrode and this drain electrode or this second area can electrically connect via this contact hole.
10. the manufacture method of array base palte as claimed in claim 9 is characterized in that, the method that forms the flatness layer that includes those contact holes is a micro-photographing process.
11. the manufacture method as the array base palte of claim 10 is characterized in that, after forming this flatness layer, also includes a blanching step and cross-linking reaction in regular turn.
12. the manufacture method of array base palte as claimed in claim 1 is characterized in that, those metal blocks of above-mentioned formation comprise the following step in the step of this upper surface of substrate:
Sputter one metal material layer is in this substrate;
Be coated with another photoresist layer in this metal material layer upper surface; And
Use a light shield that this metal material layer is carried out the lithography program, and form those metal blocks.
13. the manufacture method of array base palte as claimed in claim 1 is characterized in that, forms the step of this semiconductor layer, comprises the following step:
Form a channel layer on this insulating barrier; And
Above this channel layer, form ohmic contact layer.
14. the manufacture method as the array base palte of claim 13 is characterized in that, forms this source electrode and should drain electrode the time, this ohmic contact layer between this source electrode and this drain electrode can be removed on this semiconductor layer.
15. the manufacture method of array base palte as claimed in claim 1 is characterized in that, before the step that forms this source electrode and this drain electrode, also comprises and removes this first photoresistance pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101675278A CN101728333B (en) | 2008-10-10 | 2008-10-10 | Manufacturing method of array substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101675278A CN101728333B (en) | 2008-10-10 | 2008-10-10 | Manufacturing method of array substrate |
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| CN101728333A true CN101728333A (en) | 2010-06-09 |
| CN101728333B CN101728333B (en) | 2011-06-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117284A (en) * | 2013-02-01 | 2013-05-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| WO2016106880A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Manufacturing method for array substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100549791C (en) * | 2007-01-31 | 2009-10-14 | 友达光电股份有限公司 | The method for making of array base palte |
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2008
- 2008-10-10 CN CN2008101675278A patent/CN101728333B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117284A (en) * | 2013-02-01 | 2013-05-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| US9576989B2 (en) | 2013-02-01 | 2017-02-21 | Boe Technology Group Co., Ltd. | Array substrate and the method for making the same, and display device |
| WO2016106880A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Manufacturing method for array substrate |
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| Publication number | Publication date |
|---|---|
| CN101728333B (en) | 2011-06-15 |
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Effective date of registration: 20230515 Address after: Lake 558, Fen Hu Town, Wujiang District, Jiangsu, Suzhou Patentee after: Wujiang FenHu technology entrepreneurship Service Co.,Ltd. Address before: 215217, No. 88, Tung Hing Road, Tongli District, Wujiang Economic Development Zone, Suzhou, Jiangsu Patentee before: CPTW (WUJIANG) Co.,Ltd. Patentee before: Chunghwa Picture Tubes, Ltd. |
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