CN101719104A - Control system and control method of synchronous dynamic memory - Google Patents
Control system and control method of synchronous dynamic memory Download PDFInfo
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Abstract
The invention discloses a control system and a control method of a synchronous dynamic memory. The system comprises an address cache controller, a synchronous dynamic memory controller and a data cache controller, wherein the address cache controller is used for regulating a reading address sequence of an initial reading request and transmitting the reading request of the regulated reading address sequence to a controller of the synchronous dynamic memory; the synchronous dynamic memory controller is connected with the address cache controller, reads data from the synchronous dynamic memory according to the reading request of the regulated reading address sequence, and transmits the read data to a data cache controller; and the data cache controller is respectively connected with the synchronous dynamic memory controller and the address cache controller and is used for sequencing the received data as well as outputting the data outputted according to the sequence of the initial reading request. The invention provides PFH and PH conditions for the synchronous dynamic memory controller maximally by processing an outputted reading address, provides a basis for enhancing the efficiency of the synchronous dynamic memory controller, and also makes the sequence of outputting the data be consistent with the sequence of outputting the request by processing the read data.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to a kind of control system and control method of synchronous dynamic random access memory.
Background technology
SDRAM (synchronous dynamic random access memory, Synchronous Dynamic RAM) is a kind of data storage device commonly used,, needs Precharge at interval between the read-write of SDRAM based on the characteristics of device itself, operations such as active cause the read-write efficiency of device lower.How to improve the efficient of SDRAM, being to use this device is a problem that needs consideration.
The visit of SDRAM has following several situation, and 1, (the physical store body of internal memory is equal to " row "/Row), and all row are closed, and can directly send capable effective order this moment, and this situation is called as page or leaf and hits (PH, Page Hit) to want the Bank of addressing.2, wanting the row of addressing just in time is the work row of previous operation, that is to say, want the row of addressing to be in the gating effective status, at this moment, can directly send the row addressed command, this situation is called as page or leaf and hits (PFH fast, Page Fast Hit) 3, want had a row to be in active state (not closing) among the Bank at capable place of addressing, this phenomenon just is known as the addressing conflict, just must carry out precharge and close the work row this moment, again newline is sent the row effective order, this situation is called as page or leaf and misses (PM, Page Miss).
Obviously, PFH is optimal addressing situation, and PM then is the addressing situation of worst.
For most practice scenes, read the address and provide at random, be example with the device of 4Bank, there is 3/4 probability PH to occur, also have 1/4 probability PM or PFH to occur, wherein the probability of PFH is very little.If the visit that can provide the Bank address to interleave just provides the visit of PH,, then can effectively promote the access efficiency of SDRAM if can also take into account the situation of PFH.
Prior art mainly concentrates in the improvement to sdram controller, for the address that is input to controller except buffer memory so that do the pre-judgement, there is not more disposal route, main cause is that most scenes all requires the sequencing of the sequencing of sense data and request consistent, if the sequence of addresses to input has been done optimization, with regard to requiring the order of sense data is reset, have difficulties.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of control system and control method of synchronous dynamic random access memory, in order to solve the not high problem of prior art access synchronized dynamic storage efficient.
For solving the problems of the technologies described above, on the one hand, the invention provides a kind of control system of synchronous dynamic random access memory, described system comprises:
The address caching controller is used to adjust the sequence of addresses of reading of initial read request, and will adjust the read request of reading sequence of addresses and send to synchronous dynamic storage controller;
Synchronous dynamic storage controller is connected with described address caching controller, according to having adjusted the read request of reading sequence of addresses, and sense data from described synchronous dynamic random access memory, and the data of reading are sent to data cache controller;
Data cache controller is connected with the address caching controller with described synchronous dynamic storage controller respectively, is used for the data that described synchronous dynamic storage controller sends are sorted, according to the order output data of initial read request.
Further, described address caching controller is adjusted the sequence of addresses of reading of initial read request, is specially:
At first, described initial read request is stored, write buffer memory, during storage, store, and deposit the initial serial number that reads rule and read request in according to the address of reading of read request;
Then,, from buffer memory, read initial read request, obtained adjusting the read request of reading sequence of addresses according to the described rule that reads.
Further, described address caching controller comprises:
One or more buffer units; Each buffer unit comprises the first in first out storage FIFO consistent with the physical store body BANK number of described synchronous dynamic random access memory, and the numbering of described FIFO is corresponding with described BANK address respectively;
Mark setting unit is read by company, is connected with described buffer unit, is used for that the identical and adjacent described initial read request of row address is provided with company and reads sign;
Counter is connected with described buffer unit, is used to write down the initial serial number of described initial read request;
Divider, be connected with described buffer unit, be used for the address of reading according to described initial read request, with described initial read request read the address, connect read to indicate and initial serial number deposit in respectively with the corresponding first in first out storage of the physical store body BANK of described synchronous dynamic random access memory FIFO in;
Selector switch is connected with described buffer unit, is used for reading from described FIFO the initial read request of storage, reads sign if this initial read request is provided with to connect, and then continues to read from this FIFO the initial read request of storage; If this initial read request not company of setting is read sign, then from next FIFO, read the initial read request of storage; The read request of gained is to have adjusted the read request of reading sequence of addresses.
Further, described data cache controller comprises numbered memory cell and the data storage cell consistent with described buffer unit number,
Described numbered memory cell, corresponding connection with described buffer unit is used to store the initial serial number of described initial read request;
Described data storage cell is connected with described numbered memory cell, synchronous dynamic storage controller respectively, is used to store the data that described synchronous dynamic storage controller sends, according to described initial serial number, described data are sorted, and output.
Further, described address caching controller comprises two buffer units, is respectively first buffer unit, second buffer unit; Described data cache controller comprises first numbered memory cell, second numbered memory cell and first data storage cell, second data storage cell; Wherein, described first numbered memory cell is connected with first data storage cell with described first buffer unit respectively, and described second numbered memory cell is connected with second data storage cell with described second buffer unit respectively.
Further, described divider writes described second buffer unit after writing completely to described first buffer unit again.
Further, any one FIFO of described first buffer unit or second buffer unit writes full, and then described first buffer unit or second buffer unit are write full.
Further, described selector switch is when reading of data from described first buffer unit or second buffer unit, and described divider can not write described first buffer unit or second buffer unit.
On the other hand, the present invention also provides a kind of control method of synchronous dynamic random access memory, said method comprising the steps of:
Adjust the sequence of addresses of reading of initial read request;
According to having adjusted the read request of reading sequence of addresses, sense data from described synchronous dynamic random access memory;
Sense data from described synchronous dynamic random access memory is sorted, according to the order output data of described initial read request.
Further, adjust the sequence of addresses of reading of initial read request, specifically may further comprise the steps:
Described initial read request is stored, wherein, during storage, according to the address of reading of described initial read request, with described initial read request deposit in respectively with the corresponding first in first out of the physical store body BANK of described synchronous dynamic random access memory storage FIFO in; Identical and the adjacent described initial read request of row address is provided with company reads sign, and store the initial serial number of described initial read request;
From described FIFO, read the initial read request of storage, read sign, then continue from this FIFO, to read the initial read request of storage if this initial read request is provided with to connect; If this initial read request not company of setting is read sign, then from next FIFO, read the initial read request of storage; The read request of gained is to have adjusted the read request of reading sequence of addresses.
Further, sense data from described synchronous dynamic random access memory is sorted, the order output data according to described initial read request specifically may further comprise the steps:
Storage is sense data from described synchronous dynamic random access memory;
According to described initial serial number, described data are sorted, and output.
Beneficial effect of the present invention is as follows:
By input being read the processing of address, the situation that can maximum possible offers synchronous dynamic storage controller PFH and PH, provide the basis for synchronous dynamic storage controller promotes efficient, by processing, data are returned to consistent simultaneously with the sequencing of asking to sense data.And adopt two groups of cache information ping-pong operations, can raise the efficiency.
Description of drawings
Fig. 1 is the structural representation of the control system of 1 one kinds of synchronous dynamic random access memories of the embodiment of the invention;
Fig. 2 is the structural representation of the control system of 2 one kinds of synchronous dynamic random access memories of the embodiment of the invention;
Fig. 3 is the embodiment of the invention 2 is read read request from the address caching unit a process flow diagram;
Fig. 4 is the process flow diagram of the control method of 3 one kinds of synchronous dynamic random access memories of the embodiment of the invention.
Embodiment
In order to solve the not high problem of prior art access synchronized dynamic storage efficient, the invention provides a kind of control system and control method of synchronous dynamic random access memory, below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, does not limit the present invention.
As shown in Figure 1, the embodiment of the invention 1 relates to a kind of control system of synchronous dynamic random access memory, comprise address caching controller 101, SDRAM (synchronous dynamic random access memory) controller 102 and data cache controller 103, wherein, address caching controller 101 is used for buffer memory and the read request of management from the outside; Data cache controller 103 is used for the output of buffer memory and control data.This patent does not comprise the implementation method of sdram controller 102, and sdram controller 102 can be existing any sdram controller.
Synchronous dynamic storage controller 102 is connected with address caching controller 101, according to having adjusted the read request of reading sequence of addresses, and sense data from synchronous dynamic random access memory 104, and the data of reading are sent to data cache controller 103;
As shown in Figure 2, the embodiment of the invention 2 relates to a kind of control system of synchronous dynamic random access memory, comprises address caching controller 201, synchronous dynamic storage controller 202 and data cache controller 203.
Wherein, address caching controller 201 also comprises divider 2011, connects and read mark setting unit 2012, first buffer unit 2013, second buffer unit 2014, selector switch 2015 sum counters 2016, divider 2011, company read mark setting unit 2012 and are connected with first buffer unit 2013, second buffer unit 2014 respectively with selector switch 2015, and first buffer unit 2013, second buffer unit 2014 are respectively arranged with counter 2016.First buffer unit 2013 and second buffer unit 2014 are used for cache read address and relevant information, each buffer unit is by a plurality of FIFO (first in first out, the first in first out storage) constitutes, the BANK number of the number of FIFO and SDRAM is consistent, the numbering of FIFO and BANK address correspondence, for example SDRAM has 4 Bank (this kind situation under the present embodiment), and then the FIFO number is 4, is numbered 0-3; The degree of depth of each FIFO is set according to system requirements.
Data cache controller 203 comprises first numbered memory cell 2031, second numbered memory cell 2032, first data storage cell 2033 and second data storage cell 2034, wherein, first numbered memory cell 2031 is connected with first buffer unit 2013 in the address caching controller 201, and second numbered memory cell 2032 is connected with second buffer unit 2014 in the address caching controller 201; First data storage cell 2033 is connected with synchronous dynamic storage controller 202 respectively with second data storage cell 2034, and synchronous dynamic storage controller 202 is connected with synchronous dynamic random access memory 204.
When the control system of synchronous dynamic random access memory receives initial read request data, address caching controller 201 need carry out the operation of write-then-read to initial read request data, promptly earlier initial read request data are stored, and then read this data, mode by write-then-read, change the sequence of addresses of reading of initial read request, improve the access efficiency of synchronous dynamic storage controller 202.
When 201 pairs of initial read requests of address caching controller are stored, need among the FIFO to write and study in the address, connect and to read sign and initial serial number.Reading the address obtains from initial read request.Even read sign and be provided with by even reading mark setting unit 2012, even reading mark setting unit 2012 judges whether the row address of adjacent initial read request is identical, if identical, then sign is read by the company of setting, the company of being about to reads sign and is set to 1, otherwise then company reads sign and is set to 0.Initial serial number is by counter 2016 records, and buffer unit is counter 2016 of correspondence respectively, and when each buffer unit began to write, counter whenever received a read request to be written since 0 counting, and counter adds 1;
Divider 2011 is assigned to read request in first buffer unit 2013 and second buffer unit 2014, and two buffer units write in turn, one write full after, write another one again; All writing for two groups expires, and then stops the response external request.Buffer unit is write and is full of finger: any one FIFO in the buffer unit writes full, represents that then the buffer unit under it is write full.To read the address, even read to indicate and number and write among the FIFO of reference numeral according to the Bank address of reading the address, for example, the Bank address of reading the address is 1, and the storage unit that this moment, divider was selected is first data storage cell 2033, then above information is written to being numbered among 1 the FIFO of first data storage cell 2033.
In two buffer units any one write full after, for example first buffer unit 2013 is write full, and first numbered memory cell 2031 has been read sky, perhaps second buffer unit 2014 is write full, and second numbered memory cell 2032 has been read sky, begin from first buffer unit 2013 or second buffer unit, 2014 sense datas, till the direct-reading sky.The principle of reading is: the full state of sky according to FIFO is read sign with connecting, a plurality of FIFO of the same buffer unit of poll, and sense data from FIFO if the company of reading reads to be masked as 1, then continues to read this FIFO, otherwise reads the next FIFO in the buffer unit.Set up timer, after read request is not received in the time slot of setting, and first numbered memory cell 2031 or second numbered memory cell 2032 read sky, and the request of storage in first buffer unit 2013 and second buffer unit 2014 is read.
As shown in Figure 3, from address caching controller 201, read read request and comprise following steps:
Step S301, beginning.
Step S302 judges whether counter 2016 reaches setting-up time, if, then change step S305, if not, then change step S303.
Step S303 judges whether this buffer unit is filled with, if, then change step S304, if not, then change step S302.
Step S304 judges whether the numbered memory cell corresponding with this buffer unit reads sky, if, then change step S305, if not, then continue this numbered memory cell and whether read sky.
Step S305 judges whether the FIFO in this buffer unit is empty, if, then change step S306, if not, then change step S307.Usually, begin to read from first FIFO.
Step S306 inquires about next FIFO, and changes step S305.
Step S307 then reads read request from this FIFO.
Step S308 judges to connect and reads whether sign is 1, promptly judges whether to need to connect to read, if, then change step S309, if not, then change step S306.
Step S309 reads the next address among the same FIFO.
Step S310 judges whether this buffer unit reads sky, if then change step S301, the data read of a beginning new round; If not, then change step S306.
Instantiation is as follows: for example, second buffer unit 2014 is write full, and second numbered memory cell 2032 has been read sky, then begin to read from the address 0 that is numbered 0 FIFO, if the company of reading reads to be masked as 1, then continue to be numbered the address 1 of 0 FIFO, if the company of reading reads to be masked as 0, then number of queries is 1 fifo status, if be numbered 1 FIFO for empty, then read FIFO2, otherwise read to be numbered 1 fifo address, and the like, till second buffer unit 2014 is read sky.
Sdram controller is sent in the address of reading of reading from FIFO, finishes processing to the address by sdram controller, produces each instruction and the address of SDRAM, and sdram controller is sense data from SDRAM.
The numbering of reading is sent to first numbered memory cell 2031 and second numbered memory cell, 2032, the first numbered memory cells 2031 and second numbered memory cell 2032 and stores respectively and first buffer unit 2013 and the corresponding numbering of second buffer unit 2014;
Set up the read request counter, calculate total number of the read request read from first buffer unit 2013 and second buffer unit 2014, be respectively CNTA and CNTB, CNTA and CNTB be zero clearing when first buffer unit 2013 or second buffer unit 2014 are read sky respectively.
, should follow following steps and carry out data rearrangement after sdram controller is read in data: inner buffer first data buffer storage unit 2033 and second data buffer storage unit 2034 are set, and buffer memory is from the data of sdram controller; The data of first data buffer storage unit 2033 and the storage of second data buffer storage unit 2034 respectively with the read request correspondence of first buffer unit 2013 and 2014 storages of second buffer unit;
After the data number that writes first data buffer storage unit 2033 is equal with CNTA, read numbering from first numbered memory cell 2031; After the data number that writes second data buffer storage unit 2034 is equal with CNTB, read numbering from second numbered memory cell 2032; The numbering of reading with the numbering of reading from first numbered memory cell 2031 or second numbered memory cell 2032 is as the address of reading of first data buffer storage unit 2033 or second data buffer storage unit 2034, sense data, data are delivered to the outside, the order correspondence of its order and external read request.
The address caching controller also can only comprise a buffer unit or a plurality of buffer unit, the situation that comprises a buffer unit for the address caching controller, read-write process and above-mentioned steps are basic identical, be exactly to write data directly for this buffer unit, read after writing completely, write identical with the step of reading, method and above-mentioned steps.The data cache controller corresponding with comprising buffer unit also includes only a numbered memory cell and a data buffer unit, and the read-write operation of numbered memory cell and data buffer storage unit is identical with above-mentioned steps.For this kind situation, owing to have only a buffer unit, so data-handling efficiency is lower.Comprise the situation of a plurality of buffer units for the address caching controller, write with the method for reading, step is basic with comprise that two buffer units are consistent that difference is, to a buffer unit write full after, successively remaining buffer unit is write.Data cache controller is corresponding with it, comprises the numbered memory cell identical with the buffer unit number and a data buffer unit, respectively with buffer unit to corresponding, the read-write operation of numbered memory cell and data buffer storage unit is identical with above-mentioned steps.
As shown in Figure 4, the embodiment of the invention 3 relates to a kind of control method of synchronous dynamic random access memory, may further comprise the steps:
S401 adjusts the sequence of addresses of reading of initial read request; Specifically may further comprise the steps:
Initial read request is stored successively, wherein, during storage, according to the address of reading of initial read request, with initial read request deposit in respectively with the corresponding first in first out of the physical store body BANK of synchronous dynamic random access memory storage FIFO in; Identical and the adjacent initial read request of row address is provided with company reads sign, and store the initial serial number of initial read request;
From FIFO, read the initial read request of storage, read sign, then continue from this FIFO, to read the initial read request of storage if this initial read request is provided with to connect; If this initial read request not company of setting is read sign, then from next FIFO, read the initial read request of storage; The read request of gained is to have adjusted the read request of reading sequence of addresses.
S402 is according to having adjusted the read request of reading sequence of addresses, sense data from synchronous dynamic random access memory;
S403, storage sense data from synchronous dynamic random access memory; According to described initial serial number, described data are sorted, and output.
As can be seen from the above-described embodiment, the present invention is by reading the processing of address to input, the situation that can maximum possible offers synchronous dynamic storage controller PFH and PH, for promoting efficient, synchronous dynamic storage controller provides the basis, by processing, data are returned to consistent simultaneously with the sequencing of asking to sense data.And adopt two groups of cache information ping-pong operations, can raise the efficiency.
Although be the example purpose, the preferred embodiments of the present invention are disclosed, it also is possible those skilled in the art will recognize various improvement, increase and replacement, therefore, scope of the present invention should be not limited to the foregoing description.
Claims (11)
1. the control system of a synchronous dynamic random access memory is characterized in that, described system comprises:
The address caching controller is used to adjust the sequence of addresses of reading of initial read request, and will adjust the read request of reading sequence of addresses and send to synchronous dynamic storage controller;
Synchronous dynamic storage controller is connected with described address caching controller, according to having adjusted the read request of reading sequence of addresses, and sense data from described synchronous dynamic random access memory, and the data of reading are sent to data cache controller;
Data cache controller is connected with the address caching controller with described synchronous dynamic storage controller respectively, is used for the data that described synchronous dynamic storage controller sends are sorted, according to the order output data of described initial read request.
2. the control system of synchronous dynamic random access memory as claimed in claim 1 is characterized in that, described address caching controller is adjusted the sequence of addresses of reading of initial read request, is specially:
At first, described initial read request is stored, write buffer memory, during storage, store, and deposit the initial serial number that reads rule and read request in according to the address of reading of read request;
Then,, from buffer memory, read initial read request, obtained adjusting the read request of reading sequence of addresses according to the described rule that reads.
3. the control system of synchronous dynamic random access memory as claimed in claim 2 is characterized in that, described address caching controller comprises:
One or more buffer units; Each buffer unit comprises the first in first out storage FIFO consistent with the physical store body BANK number of described synchronous dynamic random access memory, and the numbering of described FIFO is corresponding with described BANK address respectively;
Mark setting unit is read by company, is connected with described buffer unit, is used for that the identical and adjacent described initial read request of row address is provided with company and reads sign;
Counter is connected with described buffer unit, is used to write down the initial serial number of described initial read request;
Divider, be connected with described buffer unit, be used for the address of reading according to described initial read request, with described initial read request read the address, connect read to indicate and initial serial number deposit in respectively with the corresponding first in first out storage of the physical store body BANK of described synchronous dynamic random access memory FIFO in;
Selector switch is connected with described buffer unit, is used for reading from described FIFO the initial read request of storage, reads sign if this initial read request is provided with to connect, and then continues to read from this FIFO the initial read request of storage; If this initial read request not company of setting is read sign, then from next FIFO, read the initial read request of storage; The read request of gained is to have adjusted the read request of reading sequence of addresses.
4. the control system of synchronous dynamic random access memory as claimed in claim 3 is characterized in that, described data cache controller comprises numbered memory cell and the data storage cell consistent with described buffer unit number,
Described numbered memory cell, corresponding connection with described buffer unit is used to store the initial serial number of described initial read request;
Described data storage cell is connected with described numbered memory cell, synchronous dynamic storage controller respectively, is used to store the data that described synchronous dynamic storage controller sends, according to described initial serial number, described data are sorted, and output.
5. the control system of synchronous dynamic random access memory as claimed in claim 4 is characterized in that, described address caching controller comprises two buffer units, is respectively first buffer unit, second buffer unit; Described data cache controller comprises first numbered memory cell, second numbered memory cell and first data storage cell, second data storage cell; Wherein, described first numbered memory cell is connected with first data storage cell with described first buffer unit respectively, and described second numbered memory cell is connected with second data storage cell with described second buffer unit respectively.
6. the control system of synchronous dynamic random access memory as claimed in claim 5 is characterized in that, described divider writes described second buffer unit after writing completely to described first buffer unit again.
7. the control system of synchronous dynamic random access memory as claimed in claim 6 is characterized in that, any one FIFO of described first buffer unit or second buffer unit writes full, and then described first buffer unit or second buffer unit are write full.
8. the control system of synchronous dynamic random access memory as claimed in claim 5, it is characterized in that, described selector switch is when reading of data from described first buffer unit or second buffer unit, and described divider can not write described first buffer unit or second buffer unit.
9. the control method of a synchronous dynamic random access memory is characterized in that, said method comprising the steps of:
Adjust the sequence of addresses of reading of initial read request;
According to having adjusted the read request of reading sequence of addresses, sense data from described synchronous dynamic random access memory;
Sense data from described synchronous dynamic random access memory is sorted, according to the order output data of described initial read request.
10. the control method of synchronous dynamic random access memory as claimed in claim 9 is characterized in that, adjusts the sequence of addresses of reading of initial read request, specifically may further comprise the steps:
Described initial read request is stored, wherein, during storage, according to the address of reading of described initial read request, with described initial read request deposit in respectively with the corresponding first in first out of the physical store body BANK of described synchronous dynamic random access memory storage FIFO in; Identical and the adjacent described initial read request of row address is provided with company reads sign, and store the initial serial number of described initial read request;
From described FIFO, read the initial read request of storage, read sign, then continue from this FIFO, to read the initial read request of storage if this initial read request is provided with to connect; If this initial read request not company of setting is read sign, then from next FIFO, read the initial read request of storage; The read request of gained is to have adjusted the read request of reading sequence of addresses.
11. the control method of synchronous dynamic random access memory as claimed in claim 10 is characterized in that, sense data from described synchronous dynamic random access memory is sorted, the order output data according to described initial read request specifically may further comprise the steps:
Storage is sense data from described synchronous dynamic random access memory;
According to described initial serial number, described data are sorted, and output.
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| CN111723027A (en) * | 2020-05-14 | 2020-09-29 | 江苏方天电力技术有限公司 | Dynamic storage buffer area reading control method based on power edge gateway |
| CN111723027B (en) * | 2020-05-14 | 2022-06-24 | 江苏方天电力技术有限公司 | Dynamic storage buffer area reading control method based on power edge gateway |
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