CN101710940A - Video stabilization equipment and video stabilization method - Google Patents
Video stabilization equipment and video stabilization method Download PDFInfo
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- CN101710940A CN101710940A CN200910312187A CN200910312187A CN101710940A CN 101710940 A CN101710940 A CN 101710940A CN 200910312187 A CN200910312187 A CN 200910312187A CN 200910312187 A CN200910312187 A CN 200910312187A CN 101710940 A CN101710940 A CN 101710940A
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Abstract
The invention relates to video stabilization equipment and a video stabilization method, which solve the technical problems of a plurality of noise points and image jitter in the prior art. The video stabilization equipment comprises a video signal decoding circuit, a video conversion circuit, a liquid crystal screen driving circuit, an I2C bus control unit and at least three random access memories. In the method, video stabilization is realized through the steps of decoding, converting, the splicing of odd and even fields and scheduling. The stabilization of video images is realized by scheduling video signals through the plurality of RAMs.
Description
Technical field
The present invention relates to video processing circuit and video signal processing method.
Background technology
The needs of employed liquid crystal display displays interlaced television signal in the prior art, and corresponding product can not satisfy actual demand on the market.
Along with developing rapidly of liquid crystal technology, LCD is used more and more widely as video reception apparatus now, if video source is a VESA signal line by line then display effect is very desirable, and we also often run into will make a video recording interlaced television signal that first-class equipment produces of requirement and deliver to LCD and show in the reality, give LCD after so just need handling to interlaced television signal, if and processing method is improper, the not good situation of display effect will appear, common phenomena is that noise is many, flating phenomenons such as (still image are jumped up and down, the dynamic image edge jitter).These phenomenons why occur, main cause has two: the first, TV signal digitlization (decoding) processing of circuit is bad, digitlization appears and after deviation too big, cause image flickering to the people feel image the shake; Second, because TV signal is an interlace signal, and the signal that LCD needs is generally progressive signal, and field frequency is also different, if so directly interlace signal parity field " splicing " is become progressive signal, owing to adjacent two time difference shows as the alternate position spike of motion object on plane space, thereby when the picture motion, particularly will around contour of object, tangible uneven phenomenon occur during rapid movement in the horizontal direction, make the people feel flating
Summary of the invention
The object of the invention provides a kind of video and removes to tremble Apparatus and method for, and is many to overcome the noise that exists in the prior art, the technical problem of flating.
Technical scheme of the present invention is:
A kind of video removes to tremble equipment, and its special character is: comprise vision signal decoding circuit, video conversion circuit, liquid crystal display screen drive circuit, I
2C bus control unit and at least three random asccess memory; Described I
2The C bus control unit is used for the initialization of vision signal decoding circuit, and described vision signal decoding circuit is used for the vision signal of input is converted to digital video signal and sends into video conversion circuit; Described video conversion circuit carries out the parity field splicing to the digital video signal after changing to be handled and scheduling, described three random asccess memory are used for the digital video signal after interim storage splicing is handled, and described liquid crystal display screen drive circuit is used for the digital video signal after the video conversion circuit processing is sent into liquid crystal display screen.
The quantity of above-mentioned memory is 4 RAM, and described video conversion circuit (U2) also will carry out smoothing processing to the digital video signal after the conversion.
Above-mentioned video removes to tremble equipment and comprises push-up storage, and described push-up storage is used for the digital video signal after the interim storage signal decoding circuit conversion frequently and this signal is sent into video conversion circuit.
Above-mentioned I
2The C bus control unit is I
2The C bus control unit; Described video conversion circuit, liquid crystal display screen drive circuit, I
2C bus control unit and push-up storage are realized by fpga chip.
Above-mentioned I
2The C bus control unit is I
2C bus control single chip computer; Described video conversion circuit, liquid crystal display screen drive circuit and push-up storage are realized by fpga chip.
A kind of video of realizing goes the method for trembling, and its special character is to comprise following steps:
1) passes through I
2C bus control single chip computer initialization video decode circuit;
2) original incoming video signal is undertaken sending in the video conversion circuit after the digitlization by the video decode circuit;
3) carrying out the parity field splicing by the vision signal of video conversion circuit after to digitlization handles;
4) spliced vision signal is sent into random asccess memory and dispatch, described scheduling process in turn includes the following steps:
41) first frame video signal being write first RAM is RAM1;
42) second frame video signal being write second RAM is RAM2; From first RAM, read first frame video signal and demonstration;
43) the 3rd frame video signal being write the 3rd RAM is RAM3, continues to read first frame video signal and show until its display cycle from first RAM and finish;
44) from second RAM, read second frame video signal and demonstration; Continuation writes RAM3 with the 3rd frame video signal and finishes until writing;
45) continue from second RAM, to read second frame video signal and demonstration until its display cycle end; It is RAM1 that the 4th frame video signal is write first RAM;
46) write and reading step more than three RAM circulations, finish until of the scheduling demonstration of the vision signal of sending into video conversion circuit by three RAM.
Above-mentioned steps 3) concrete steps are as follows:
Original incoming video signal is undertaken sending into push-up storage FIFO after the digitlization by the video decode circuit temporarily store, send into then in the video conversion circuit of fpga chip.
A kind of video of realizing goes the method for trembling, and its special character is to comprise following steps:
1) passes through I
2C bus control single chip computer initialization video decode circuit;
2) original incoming video signal is undertaken sending in the video conversion circuit after the digitlization by the video decode circuit;
3) carrying out the parity field splicing by the vision signal of video conversion circuit after to digitlization handles;
4) spliced vision signal is sent into random asccess memory and dispatch, described scheduling process in turn includes the following steps:
411) first frame video signal being write first RAM is RAM1;
412) second frame video signal being write second RAM is RAM2; First frame video signal among first RAM is carried out smoothing processing;
413) second frame video signal is carried out smoothing processing; The 3rd frame video signal is write RAM3; From RAM1, read first frame video signal and demonstration;
414) finish from resume studies out first frame video signal and showing of RAM1 relaying until its display cycle; The 3rd frame video signal is carried out smoothing processing; It is RAM4 that the 4th frame video signal is write the 4th RAM;
415) from RAM2, read second frame video signal and demonstration; Continuation is carried out smoothing processing to the 3rd frame video signal and is finished until processing; Continuation writes RAM4 with the 4th frame video signal and finishes until writing;
416) the 5th frame video signal being write first RAM is RAM1; Finish from resume studies out second frame video signal and showing of RAM2 relaying until its display cycle; The 4th frame video signal is carried out smoothing processing;
417) continue the 5th frame video signal is write first RAM; From RAM3, read the 3rd frame video signal and demonstration; Continuation is carried out smoothing processing to the 4th frame video signal and is finished until processing;
418) write more than four RAM circulation, processing and reading step, show until the scheduling of the vision signal of sending into video conversion circuit by four RAM to finish.
Above-mentioned steps 3) concrete steps are as follows:
Original incoming video signal is undertaken sending into push-up storage FIFO after the digitlization by the video decode circuit temporarily store, send into then in the video conversion circuit of fpga chip.
The algorithm that above-mentioned smoothing processing adopted is the difference algorithm.
The present invention mainly realizes the stable of video image by multi-disc RAM to the scheduling of vision signal.
Description of drawings
Fig. 1 is first kind of structure principle chart of present device.
Fig. 2 is second kind of structure principle chart of present device.
Fig. 3 is first kind of scheduling process schematic diagram of the inventive method.
Fig. 4 is second kind of scheduling process schematic diagram of the inventive method.
Embodiment
Referring to Fig. 1 and Fig. 2, the present invention includes vision signal decoding circuit U1, video conversion circuit U2, liquid crystal display screen drive circuit U3, I
2C bus control unit U4 and at least three random access memory rams 1, RAM2, RAM3; I
2The C bus control unit is used for the initialization of vision signal decoding circuit, and the vision signal decoding circuit is used for the vision signal of input is converted to digital video signal and sends into video conversion circuit; Video conversion circuit U2 carries out the parity field splicing to the digital video signal after changing to be handled and scheduling, three random asccess memory are used for the digital video signal after the interim storage splicing processing, and liquid crystal display screen drive circuit U3 is used for the digital video signal after the video conversion circuit processing is sent into liquid crystal display screen.
When the quantity of memory is 4 RAM, i.e. RAM1, RAM2, RAM3, RAM4, video conversion circuit U2 also can carry out smoothing processing to the digital video signal after the conversion.
Video removes to tremble equipment can comprise push-up storage FIFO, and described push-up storage FIFO is used for the digital video signal after the interim storage signal decoding circuit conversion frequently and this signal is sent into video conversion circuit.
I
2C bus control unit U4 can be I
2The C bus control unit; Described video conversion circuit U2, liquid crystal display screen drive circuit U3, I
2C bus control unit U4 and push-up storage FIFO are realized by fpga chip.
I
2C bus control unit U4 also can be I
2C bus control single chip computer; Described video conversion circuit U2, liquid crystal display screen drive circuit U3 and push-up storage FIFO are realized by fpga chip.
Vision signal with input is that the PAL vision signal is an example, describes realization video jitter removing method of the present invention.
Referring to Fig. 3, realize that for the present invention is a kind of video goes the method for trembling, and comprises following steps:
1) passes through I
2C bus control single chip computer initialization video decode circuit;
2) original incoming video signal is undertaken sending in the video conversion circuit after the digitlization by the video decode circuit;
3) carrying out the parity field splicing by the vision signal of video conversion circuit after to digitlization handles;
4) spliced vision signal is sent into random asccess memory and dispatch, described scheduling process in turn includes the following steps:
41) first frame video signal being write first RAM is RAM1, needs 40ms;
42) second frame video signal being write second RAM is RAM2, needs 40ms; From first RAM, read first frame video signal and demonstration; Because the display cycle is about 16.6ms, therefore in the 40ms of RAM2 write signal, the vision signal that is stored in RAM1 shows 2 times, and is carrying out the 3rd demonstration;
43) the 3rd frame video signal being write the 3rd RAM is RAM3, continues to read first frame video signal and show until its display cycle from first RAM and finish; Read vision signal by RAM1 simultaneously and continue to be shown in vision signal display cycle end in RAM1 on the liquid crystal display screen, because being stored in vision signal remaining display cycle time of RAM1 in previous step is rapid is 16.6ms-7ms=9.6ms, be about 10ms, therefore only need this step of 10ms to finish;
44) from second RAM, read second frame video signal and demonstration; Continuation writes RAM3 with the 3rd frame video signal and finishes until writing; Because RAM3 had write the time of 10ms during previous step was rapid, thus the time that writes RAM3 in this step be about 30ms;
45) continue from second RAM, to read second frame video signal and demonstration until its display cycle end; Because the vision signal of reading from RAM2 during previous step is rapid is about 30ms, so only need in this step to show that more about 3.3ms can finish the display cycle one time; Simultaneously again the 4th frame video signal being write first RAM is RAM1;
46) write and reading step more than three RAM circulations, finish until of the scheduling demonstration of the vision signal of sending into video conversion circuit by three RAM.
In step 3), original incoming video signal can be carried out sending into push-up storage FIFO after the digitlization by the video decode circuit and temporarily store, send into then in the video conversion circuit of fpga chip.
Referring to Fig. 4, realization video involved in the present invention goes the method for trembling, and can also better realize as follows:
1) passes through I
2C bus control single chip computer initialization video decode circuit;
2) original incoming video signal is undertaken sending in the video conversion circuit after the digitlization by the video decode circuit;
3) carrying out the parity field splicing by the vision signal of video conversion circuit after to digitlization handles;
4) spliced vision signal is sent into random asccess memory and dispatch, described scheduling process in turn includes the following steps:
411) first frame video signal being write first RAM is RAM1, needs 40ms;
412) second frame video signal being write second RAM is RAM2, needs 40ms; First frame video signal among first RAM is carried out smoothing processing, and the processing time is less than 40ms;
413) second frame video signal is carried out smoothing processing; The 3rd frame video signal is write RAM3, need 40ms; Read first frame video signal and also show from RAM1, because the display cycle is about 16.6ms, therefore in the 40ms of RAM3 write signal, the vision signal that is stored in RAM1 shows 2 times, and is carrying out the 3rd demonstration;
414) finish from resume studies out first frame video signal and showing of RAM1 relaying until its display cycle, because being stored in vision signal remaining display cycle time of RAM1 in previous step is rapid is 16.6ms-7ms=9.6ms, be about 10ms, therefore in this step, only need show again that 10ms can finish a display cycle; Simultaneously the 3rd frame video signal is carried out smoothing processing; It is RAM4 that the 4th frame video signal is write the 4th RAM;
415) from RAM2, read second frame video signal and demonstration; Continuation is carried out smoothing processing to the 3rd frame video signal and is finished until processing; Continuation writes RAM4 with the 4th frame video signal and finishes until writing; Since during previous step is rapid with processing and write time of about 10ms, so this step process that need about 30ms finish processing and write; The vision signal that will be stored in RAM2 simultaneously in this 30ms reads out to the liquid crystal display screen drive circuit by video conversion circuit, and then is shown on the liquid crystal display screen;
416) the 5th frame video signal being write first RAM is RAM1; Finish from resume studies out second frame video signal and showing of RAM2 relaying until its display cycle and since previous step rapid in time of reality be about 30ms, so only need in this step to show that more about 3.3ms can finish the display cycle one time; And in this 3.3ms, the 4th frame video signal is carried out smoothing processing;
417) continuing that the 4th frame video signal is carried out smoothing processing finishes until processing, owing to carried out the smoothing processing time of about 3.3ms during previous step is rapid, thus the time that only needs to handle about 36.7ms in this step can finish work to vision signal smoothing processing among the RAM4; And in this 36.7ms, continue the 5th frame video signal is write first RAM; The vision signal that will be stored in RAM3 simultaneously reads out to the liquid crystal display screen drive circuit by video conversion circuit, and then is shown on the liquid crystal display screen
418) write more than four RAM circulation, processing and reading step, show until the scheduling of the vision signal of sending into video conversion circuit by four RAM to finish.
In step 3), original incoming video signal can be carried out sending into push-up storage FIFO after the digitlization by the video decode circuit and temporarily store, send into then in the video conversion circuit of fpga chip.
The above-mentioned algorithm that smoothing processing adopted is the difference algorithm.
The present invention mainly adopts 1 PAL decoder, and 1 fpga chip and 4 RAM realize that the overall structure of whole proposal as shown in drawings.Wherein the PAL decoder is responsible for TV signal is carried out digitlization, and fpga chip is realized interlaced television signal parity field " splicing ", smoothing processing and scheduling, and 4 RAM are used for depositing raw decoded data and handle the frame data that reach after handling.
Since the PAL video this as the 50Hz interlace mode, and finally be shown as the 60Hz progressive scan mode, therefore show it is to carry out frequency inverted, in order to reach the shortest delay and optimum display effect, but this programme has adopted 4 independent access RAM.
In normal work stage, 1 RAM is used to store initial data (need carry out strange field and even field data and be spliced to form 1 complete picture), 1 RAM is used for storage through hardware convergent-divergent and level and smooth (going shake) ephemeral data when handling, 1 RAM is used to do display buffer and goes (data after the processing), and 1 RAM is used for scheduling to be handled.
RAM in three work carries out concurrent working by frequency separately, and when having stored 1 complete PAL frame, memory address switches to idle that sheet RAM; Judge whether new data (new whole frame) when work of treatment finishes, it's not true waits by the time have till the new data always, and that sheet RAM that switches to the storage end then handles; After having shown 1 frame picture, flow for displaying also judges whether new data (Frame after the processing), and it's not true shows present frame once more, and the words that have are switched.
Claims (10)
1. a video removes to tremble equipment, it is characterized in that: comprise vision signal decoding circuit (U1), video conversion circuit (U2), liquid crystal display screen drive circuit (U3), I2C bus control unit (U4) and at least three random asccess memory (RAM1, RAM2, RAM3); Described I2C bus control unit is used for the initialization of vision signal decoding circuit, and described vision signal decoding circuit is used for the vision signal of input is converted to digital video signal and sends into video conversion circuit; Described video conversion circuit (U2) carries out the parity field splicing to the digital video signal after changing to be handled and scheduling, described three random asccess memory are used for the digital video signal after interim storage splicing is handled, and described liquid crystal display screen drive circuit (U3) is used for the digital video signal after the video conversion circuit processing is sent into liquid crystal display screen.
2. video according to claim 1 removes to tremble equipment, it is characterized in that: the quantity of described memory is 4 RAM (RAM1, RAM2, RAM3, RAM4), and described video conversion circuit (U2) also will carry out smoothing processing to the digital video signal after the conversion.
3. video according to claim 1 and 2 removes to tremble equipment, it is characterized in that: described video removes to tremble equipment and comprises push-up storage (FIFO), and described push-up storage (FIFO) is used for the digital video signal after the interim storage signal decoding circuit conversion frequently and this signal is sent into video conversion circuit.
4. video according to claim 3 removes to tremble equipment, it is characterized in that: described I2C bus control unit (U4) is the I2C bus control unit; Described video conversion circuit (U2), liquid crystal display screen drive circuit (U3), I2C bus control unit (U4) and push-up storage (FIFO) are realized by fpga chip.
5. video according to claim 3 removes to tremble equipment, it is characterized in that: described I2C bus control unit (U4) is an I2C bus control single chip computer; Described video conversion circuit (U2), liquid crystal display screen drive circuit (U3) and push-up storage (FIFO) are realized by fpga chip.
6. realize that video goes the method for trembling for one kind, it is characterized in that, comprise following steps:
1) by I2C bus control single chip computer initialization video decode circuit;
2) original incoming video signal is undertaken sending in the video conversion circuit after the digitlization by the video decode circuit;
3) carrying out the parity field splicing by the vision signal of video conversion circuit after to digitlization handles;
4) spliced vision signal is sent into random asccess memory and dispatch, described scheduling process in turn includes the following steps:
41) first frame video signal being write first RAM is RAM1;
42) second frame video signal being write second RAM is RAM2; From first RAM, read first frame video signal and demonstration;
43) the 3rd frame video signal being write the 3rd RAM is RAM3, continues to read first frame video signal and show until its display cycle from first RAM and finish;
44) from second RAM, read second frame video signal and demonstration; Continuation writes RAM3 with the 3rd frame video signal and finishes until writing;
45) continue from second RAM, to read second frame video signal and demonstration until its display cycle end; It is RAM1 that the 4th frame video signal is write first RAM;
46) write and reading step more than three RAM circulations, finish until of the scheduling demonstration of the vision signal of sending into video conversion circuit by three RAM.
7. realization video according to claim 6 goes the method for trembling, it is characterized in that, the concrete steps of described step 3) are as follows: original incoming video signal is undertaken sending into push-up storage FIFO after the digitlization by the video decode circuit temporarily store, send into then in the video conversion circuit of fpga chip.
8. realize that video goes the method for trembling for one kind, it is characterized in that, comprise following steps:
1) by I2C bus control single chip computer initialization video decode circuit;
2) original incoming video signal is undertaken sending in the video conversion circuit after the digitlization by the video decode circuit;
3) carrying out the parity field splicing by the vision signal of video conversion circuit after to digitlization handles;
4) spliced vision signal is sent into random asccess memory and dispatch, described scheduling process in turn includes the following steps:
411) first frame video signal being write first RAM is RAM1;
412) second frame video signal being write second RAM is RAM2; First frame video signal among first RAM is carried out smoothing processing;
413) second frame video signal is carried out smoothing processing; The 3rd frame video signal is write RAM3; From RAM1, read first frame video signal and demonstration;
414) finish from resume studies out first frame video signal and showing of RAM1 relaying until its display cycle; The 3rd frame video signal is carried out smoothing processing; It is RAM4 that the 4th frame video signal is write the 4th RAM;
415) from RAM2, read second frame video signal and demonstration; Continuation is carried out smoothing processing to the 3rd frame video signal and is finished until processing; Continuation writes RAM4 with the 4th frame video signal and finishes until writing;
416) the 5th frame video signal being write first RAM is RAM1; Finish from resume studies out second frame video signal and showing of RAM2 relaying until its display cycle; The 4th frame video signal is carried out smoothing processing;
417) continue the 5th frame video signal is write first RAM; From RAM3, read the 3rd frame video signal and demonstration; Continuation is carried out smoothing processing to the 4th frame video signal and is finished until processing;
418) write more than four RAM circulation, processing and reading step, show until the scheduling of the vision signal of sending into video conversion circuit by four RAM to finish.
9. realization video according to claim 8 goes the method for trembling, it is characterized in that, the concrete steps of described step 3) are as follows: original incoming video signal is undertaken sending into push-up storage FIFO after the digitlization by the video decode circuit temporarily store, send into then in the video conversion circuit of fpga chip.
According to Claim 8 or 9 described videos go the method for trembling, it is characterized in that: the algorithm that described smoothing processing adopted is the difference algorithm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910312187A CN101710940A (en) | 2009-12-24 | 2009-12-24 | Video stabilization equipment and video stabilization method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910312187A CN101710940A (en) | 2009-12-24 | 2009-12-24 | Video stabilization equipment and video stabilization method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103024290A (en) * | 2013-01-10 | 2013-04-03 | 深圳市长江力伟股份有限公司 | Method and system for eliminating odd-even disorder by video mosaic and electronic device |
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2009
- 2009-12-24 CN CN200910312187A patent/CN101710940A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103024290A (en) * | 2013-01-10 | 2013-04-03 | 深圳市长江力伟股份有限公司 | Method and system for eliminating odd-even disorder by video mosaic and electronic device |
| CN103024290B (en) * | 2013-01-10 | 2017-02-08 | 深圳市长江力伟股份有限公司 | Method and system for eliminating odd-even disorder by video mosaic and electronic device |
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Open date: 20100519 |