CN2791800Y

CN2791800Y - AC-PDP storge and control circuit based on digital signal processor

Info

Publication number: CN2791800Y
Application number: CNU2005200786330U
Authority: CN
Inventors: 王进锋
Original assignee: Irico Group Electronics Co Ltd
Current assignee: Sichuan Sterope Orion Display Co., Ltd.
Priority date: 2005-04-18
Filing date: 2005-04-18
Publication date: 2006-06-28
Anticipated expiration: 2015-04-18

Abstract

The utility model discloses an AC-PDP storage and control circuit based on a digital signal processor, which comprises a DSP digital signal processor, an FPGA image data collection and output circuit unit, an input interface buffer unit, an output drive control buffer unit, an SDRAM memory and a FLASH memory, wherein the DSP digital signal processor is respectively connected with the SDRAM memory and the FLASH memory. The DSP digital signal processor is connected with the FPGA image data collection and output circuit unit, and the FPGA image data collection and output circuit unit is respectively connected with the input interface buffer unit and the output drive control buffer unit. The utility model can smartly accomplish different screen structures, the displayed pictures are more abundance, natural and fluent, the utility model improves picture quality and creates perfect visual effect, and image display speed and quality are greatly increased.

Description

AC-PDP storage and control circuit based on digital signal processor

Technical field

The utility model relates to a kind of AC-PDP of being applied to color plasma display storage and control circuit, particularly a kind of AC-PDP storage and control circuit based on the DSP digital signal processor.

Background technology

Along with the explosive increase of people to information requirement, the particularly continual renovation of social informatization degree and multimedia information technology, various applications are also more and more higher for the requirement of display device, and giant-screen, high definition, low radiation have become the important indicator of weighing a kind of display device superiority.To be easy to make large screen display be the desirable display device of digital color TV high-definition television HDTV and multimedia terminal owing to be operated in totally digitilized pattern at various display device ionic medium volumetric displays (PDP Plasma Display Panel), especially has very strong competitive power in 40 to 60 inches scopes.Colour plasma display becomes the first-selection of large screen display device with superior performance, the large-sized solor plasma display device has begun to come into the market at present, especially AC type AC-PDP has advantages such as type of drive is simple and obtains extensive studies and application, and can progressively be popularized in recent years.And in the research field of AC-PDP, Circuits System accounts for very part and parcel, and Circuits System mainly comprises interface circuit, storage and control circuit, driving circuit and four parts of power circuit, and storage and control circuit are to enliven part most in the PDP circuit studies.Storage and control circuit receive the digital signal from interface circuit, export to driving circuit, finish the demonstration of image.Storage and control circuit can increase substantially the display frame quality under the structure situation that does not change display screen and driving circuit, reduce circuit cost.In the storage and control circuit specific implementation of Color AC-PDP, many companies have adopted the ASIC designing technique and have released special chip separately, and these chips only occur with finished product PDP often, and closely related with the realization of other circuit.And universal storage and control circuit, mostly adopted jumbo FPGA (Field Programmable Gate Array), be that field programmable gate array is realized, and along with the development of HDTV, and the enhancing of TV functions, because FPGA itself limits and makes processing power and processing speed restricted.

The groundwork flow process is as follows: usually finished collection by FPGA and its structure according to display screen is finished the upper and lower shunting that shows electricity level view data after from the digital signal of interface in general PDP circuit, the view data that belongs to upper and lower electrode gives upper/lower electrode corresponding FPGA process chip, finish data by this fpga chip and separate by son and write the SDRAM storer, and in address period, the pictorial data of write store read and carry out that simple view data is handled, output.Foregoing circuit is generally realized by a slice or multi-disc high capacity fpga chip.Because the FPGA function is limit, FPGA does not generally have special data-carrier store interface, has reduced storage, reading speed like this.FPGA also is difficult to realize specific image processing algorithm simultaneously, makes image quality be difficult to be improved.

Summary of the invention

The purpose of this utility model is to provide a kind of AC-PDP storage and control circuit based on digital signal processor, by high-speed dsp digital signal processor spare, the display image processing speed is accelerated, make picture more natural, also simplify hardware circuit simultaneously, reduced cost.

The technical solution of the utility model is achieved in that and comprises digital signal processor, FPGA image data acquiring and output circuit unit, the input interface buffer unit, output drive controlling buffer unit, SDRAM storer and FLASH storer, digital signal processor connects SDRAM storer and FLASH storer respectively, digital signal processor is connected with output circuit unit with the FPGA image data acquiring, and the FPGA image data acquiring is connected input interface buffer unit and output drive controlling buffer unit respectively with output circuit unit.

Described digital signal processor adopts the chip of TMS320C62XX model.

The SDRAM memory data bus is 32.

Digital signal processor is connected with the SDRAM storer by the EMIF mouth, takies the CEO space outerpace of digital signal processor.

Digital signal processor is connected with the FLASH storer by the EMIF mouth, takies the CE1 space outerpace of digital signal processor.

Digital signal processor is connected with output circuit unit with the FPGA image data acquiring by the EMIF mouth, takies the CE2 space outerpace of digital signal processor.

The input interface buffer unit can be selected the use in parallel of multi-disc 74LVC541 chip for use.

Output drive controlling buffer unit can be selected the use in parallel of multi-disc 74F541 chip for use.

The utility model adopts the method for high-speed dsp digital signal processor and other high-speed interface control circuit combination to realize AC-PDP storage and control circuit, the DSP digital signal processor is as main control chip, in conjunction with other peripheral high speed device, can make the display image data processing speed faster, can realize various drivings and control method neatly, simplified hardware circuit simultaneously, can make that AC-PDP display frame is abundanter, nature, smoothness, greatly improved image quality.

Description of drawings

Fig. 1 is a principle of work block scheme of the present utility model;

Fig. 2 is high speed digital signal processor of the present utility model and SDRAM storer connecting circuit figure;

Fig. 3 is high speed digital signal processor of the present utility model and FLASH storer connecting circuit figure;

Fig. 4 is the connecting circuit figure of high speed digital signal processor of the present utility model and FPGA image data acquiring and output circuit unit, input interface buffer unit, output drive controlling buffer unit.

Embodiment

Accompanying drawing is a specific embodiment of the utility model;

Below in conjunction with accompanying drawing content of the present utility model is described in further detail:

With reference to shown in Figure 1, Fig. 1 is based on the AC-PDP storage that the DSP digital signal processor is a kernel control chip and the principle of work and the block scheme of control circuit.Comprise digital signal processor 1, FPGA image data acquiring and output circuit unit 2, input interface buffer unit 3, output drive controlling buffer unit 4, SDRAM storer 5 and FLASH storer 6, digital signal processor 1 connects SDRAM storer 5 and FLASH storer 6 respectively, and digital signal processor 1 is connected with output circuit unit 2 with the FPGA image data acquiring, and output circuit unit 2 connects input interface buffer unit 3 and output drive controlling buffer unit 4 respectively.

Based on the DSP digital signal processor be the AC-PDP storage of kernel control chip and control circuit mainly be DSP digital signal processor TMS320C62XX 1, it connects and controls other module respectively by system bus, finish the processing and the computing of data, DSP digital signal processor TMS320S62XX1 can realize the fixed-point arithmetic ability that 1600MIPS is above, and the time of finishing 1024 fixed point FFT is less than 70 μ s.Based on digital signal processor is that the AC-PDP storage of kernel control chip comprises with control circuit: the FPGA image data acquiring is connected with digital signal processor 1 by system bus with output circuit unit 2, carry out the high speed exchange and the processing of data, by connecting input interface buffer unit 3, output drive controlling buffer unit 4, finish simultaneously the reception processing of input signal and the control of output signal; Input interface buffer unit 3 is connected with the AC-PDP display interface circuit, the level signal that the conversion of signals that interface circuit is sent here becomes FPGA image data acquiring and output circuit unit 2 to receive; Output drive controlling buffer unit 4 is connected with output circuit unit 2 with the FPGA image data acquiring, and the drive control signal of its output is changed into the level signal that the AC-PDP driving circuit can receive, and output signal arrives driving circuit; SDRAM storer 5 is connected with DSP digital signal processor 1 by system bus, as the interim buffer area of exchanges data and processing; FLASH storer 6 is connected with DSP digital signal processor 1 by system bus, as the storage space of program and the image processing algorithm and the tables of data of DSP digital signal processor 1.

Shown in Fig. 2,3,4, digital signal processor 1 is connected with SDRAM storer 5 by the EMIF mouth, takies the CEO space outerpace of digital signal processor 1.

Digital signal processor 1 is connected with FLASH storer 6 by the EMIF mouth, takies the CE1 space outerpace of digital signal processor 1.

Digital signal processor 1 is connected with output circuit unit 2 with the FPGA image data acquiring by the EMIF mouth, takies the CE2 space outerpace of digital signal processor 1.

Input interface buffer unit 3 can be selected the use in parallel of multi-disc 74LVC541 chip for use.

Output drive controlling buffer unit 4 can be selected the use in parallel of multi-disc 74F541 chip for use.

Wherein digital signal processor 1 can adopt 32 fixed-point processor TMS320C62XX family chips of TI company, and FPGA image data acquiring and output circuit unit 2 can select for use the EP1C6Q240 chip of Cyclone series of ALTERA company or the FPGA device of other company to realize according to input, output requirement.Interface circuit and driving circuit that input interface buffer unit 3 and output drive controlling buffer unit 4 are connected respectively in the AC-PDP Circuits System.And SDRAM storer 5 can select for use one or more pieces to finish according to operand and data-bus width, and FLASH storer 6 can be selected the chip of suitable capacity according to the size of program.

The course of work is as follows: circuit is by the output digital signal in the interface circuit in the external AC-PDP circuit of input interface buffer unit 3 connections, this signal is changed into FPGA image data acquiring and output circuit unit 2 receivable operation level signals, 2 pairs of these digital signals of FPGA image data acquiring and output circuit unit are handled, change into 32 data-signal, give digital signal processor TMS320S62XX 1 by system bus with the picture signal high-speed transfer, the various image processing algorithms that digital signal processor TMS320S62XX 1 reads the program in the FLASH storer 6 and stored by the system bus guiding during powering on.1 pair of view data that transmits of digital signal processor TMS320S62XX is divided into two parts according to the distribution of A electrode on the AC-PDP display screen with pictorial data, i.e. top electrode part and bottom electrode part.Then pictorial data is separated by a son principle step-by-step that shows, be written among SDRAM storer 5 or the inside Cache of self after data after separating are compensated and handle, when data deposit wherein a field memory in, from an other field memory, pictorial data read and in address period according to the form of addressing A electrode with arrange and require to send to again FPGA image data acquiring and output circuit unit 2, here digital signal processor TMS320S62XX 1 can be according to the view data of input, judge, because the Color AC-PDP circuit all adopts addressing and display separation (ADS) technology, thereby aspect image quality, there are various defectives, need carry out various judgements and correction to view data, thereby improve image quality.Owing to adopt DSP to adopt specific Processing Algorithm, can effectively reduce dynamic false contours, improve the motion image signal loss, but make smoothly nature of image border by carrying out interpolation arithmetic removal of images edge sawtooth.DSP digital signal processor TMS320S62XX 1 goes back may command FPGA image data acquiring and output circuit unit 2 produces the required scanning of display screens demonstration, keeps and various timing controlled driving logical signals.FPGA image data acquiring and output circuit unit 2 are according to the result of DSP digital signal processor TMS320S62XX 1, output data is transferred to output drive controlling buffer unit 4, output drive controlling buffer unit 4 signals with input change into the level signal that driving circuit can receive in the AC-PDP circuit, finish the demonstration of image.

High-speed dsp (digital signal processor) technology can greatly improve data-handling capacity and speed, simultaneously also simplified hardware circuit, software programming is simple, has reduced the entire circuit cost, can carry out the realization of various image processing algorithms fast, improve image quality to greatest extent.

The utility model is implemented in AC plasma display (AC-PDP) storage and the control circuit and realizes at a high speed, flexible way processes and displays view data, realize various raising display image image quality algorithms, thereby make the display image picture more natural, smooth, reduce circuit cost.

Claims

1. the AC-PDP based on digital signal processor stores and control circuit, comprise DSP digital signal processor (1), FPGA image data acquiring and output circuit unit (2), input interface buffer unit (3), output drive controlling buffer unit (4), SDRAM storer (5) and FLASH storer (6), it is characterized in that, DSP digital signal processor (1) connects SDRAM storer (5) and FLASH storer (6) respectively, DSP digital signal processor (1) is connected with output circuit unit (2) with the FPGA image data acquiring, and the FPGA image data acquiring is connected input interface buffer unit (3) and output drive controlling buffer unit (4) respectively with output circuit unit (2).

2. AC-PDP storage and control circuit based on digital signal processor according to claim 1 is characterized in that DSP digital signal processor (1) adopts the chip of TMS320C62XX model.

3. AC-PDP storage and control circuit based on digital signal processor according to claim 1 is characterized in that SDRAM storer (5) data bus is 32.

4, AC-PDP storage and control circuit based on digital signal processor according to claim 1, it is characterized in that, DSP digital signal processor (1) is connected with SDRAM storer (5) by the EMIF mouth, takies the CE0 space outerpace of DSP digital signal processor (1).

5, AC-PDP storage and control circuit based on digital signal processor according to claim 1, it is characterized in that, DSP digital signal processor (1) is connected with FLASH storer (6) by the EMIF mouth, takies the CE1 space outerpace of DSP digital signal processor (1).

6, AC-PDP storage and control circuit based on digital signal processor according to claim 1, it is characterized in that, DSP digital signal processor (1) is connected with output circuit unit (2) with the FPGA image data acquiring by the EMIF mouth, takies the CE2 space outerpace of DSP digital signal processor (1).

7, AC-PDP storage and control circuit based on digital signal processor according to claim 1 is characterized in that, input interface buffer unit (3) can be selected the use in parallel of multi-disc 74LVC541 chip for use.

8, AC-PDP storage and control circuit based on digital signal processor according to claim 1 is characterized in that, output drive controlling buffer unit (4) can be selected the use in parallel of multi-disc 74F541 chip for use.