CN101710271B - Mixed numerical system summator - Google Patents
Mixed numerical system summator Download PDFInfo
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- CN101710271B CN101710271B CN2009102357188A CN200910235718A CN101710271B CN 101710271 B CN101710271 B CN 101710271B CN 2009102357188 A CN2009102357188 A CN 2009102357188A CN 200910235718 A CN200910235718 A CN 200910235718A CN 101710271 B CN101710271 B CN 101710271B
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Abstract
The mixed numerical system summator is mainly composed of a plurality of four-digit mixed summator units, wherein each mixed summator unit comprises an input data gate, an operand a data latch controller, an operand b data latch controller, a four-digit summator, a numerical system carry synthesizer, a numeric overflow judger, a numerical system normalizing device and a mixed numerical system four-digit operation result gate. The invention can realize stop-motion binary operation and triple-motion decimal number operation represented by a BCD code and can realize operation of different numerical systems with a hardware method, thus avoiding the numerical system conversion of software and improving the operation efficiency of the mixed numerical system. The calculation digit of the mixed numerical system summator can be flexibly expanded according to the calculation requirement. The summator has simple structure, small area, low power consumption and strong practicability and is convenient to realize on a chip.
Description
Technical field
The present invention relates to a kind of mixed numerical system summator, specially refer to a kind of implementation method of mixed numerical system summator and the structure of particular hardware, can be used for the design and the manufacturing of the arithmetical unit among flush bonding processor, controller and the special-purpose soc.
Background technology
Mixing the numeral system computing uses very extensive; For example: in numerous electronic products such as the electronic electricity meter of pre-payment, electronic water meter, electromedical equipment CT, electronic sphygmomanometer; All have the problem of mixing numeral system computing and conversion, computing mainly is a binary arithmetic, and traditional way is to accomplish through software; This mode treatment effeciency is low, and is unfavorable for the development and maintenance of built-in applied system.In today of processor, controller and special-purpose soc fast development; Shorter and shorter in the face of the embedded system application and development cycle, reliability requirement is increasingly high, processing speed requires the more and more faster market demand to drive down, integrated mixing numeral system calculation function has become the only selection of flush bonding processor, embedded controller and special-purpose soc product supplier in a single-chip., the design of specific function arithmetical unit is external core technology of blocking always, also rarely has the report of clear and definite, detailed implementation method and structure in the document of publishing.
Summary of the invention
Technology of the present invention is dealt with problems: the deficiency that overcomes prior art; A kind of mixed numerical system summator is provided; Hybrid adder cellular construction area of the present invention is little, computing is low in energy consumption; Be convenient on chip, realize, can calculate figure place to totalizer according to the calculating needs and carry out flexible expansion, can realize the decimal number computing that binary arithmetic and binary-coded decimal are represented.
Technical solution of the present invention: a kind of mixed numerical system summator; Constitute by n four hybrid adder unit; Each hybrid adder unit comprises that input data strobe device, operand a data latching controller, operand b data latching controller, four totalizers, numeral system carry compositor, numerical value overflow determining device, numeral system normalizer, mix numeral system four bit arithmetics gate as a result; Four positional operand a and four positional operand b insert the data input pin of input data strobe device respectively; The input data strobe device carries out gating to the four positional operand a and the four positional operand b of input under the control of numeral system control signal and performance period counting controling signal; The input end of gating result transmission to the operand a data latching controller of input data strobe device and the input end of operand b data latching controller; Operand a data latching controller and operand b data latching controller four positional operand a and the four positional operand b to gating under the control of numeral system control signal and performance period counting controling signal latch; The latch result of operand a data latching controller and operand b data latching controller inserts four positional operand input ends of four totalizers; Wherein the latch result of operand a data latching controller inserts the four positional operands input a end of four totalizers; The latch result of operand b data latching controller inserts the four positional operands input b end of four totalizers; Four totalizers are carried out the tetrad additive operation to four positional operand a and the four positional operand b that latch; Four bit arithmetic results of four totalizers insert numerical value respectively and overflow determining device, numeral system normalizer and mix the numeral system four bit arithmetics input end of gate as a result; The computing carry output of four totalizers inserts the input end of numeral system carry compositor; Numerical value overflows determining device to carry out numerical value according to four bit arithmetic results of four totalizers and overflows and judge output decimal number binary-coded decimal spill over; Decimal number binary-coded decimal spill over inserts numeral system normalizer and numeral system carry compositor; The numeral system normalizer becomes four bit arithmetic results of four totalizers the numeral system standardizing number of standard binary-coded decimal through the decimal normalization operational transition according to decimal number binary-coded decimal spill over; Numeral system carry compositor carries out gating according to the numeral system control signal to the computing carry and the decimal number binary-coded decimal spill over of four totalizers; Output inserts in the adjacent high-order hybrid adder unit carry input in four totalizers as the carry of hybrid adder at the corresponding levels unit in the output of numeral system carry compositor; The numeral system standardizing number of numeral system normalizer output inserts mixes numeral system four bit arithmetics gate and the selection input end of importing data strobe device as a result; Mix numeral system four bit arithmetics as a result gate under the control of numeral system control signal and performance period counting controling signal, four of four totalizers are exported the result and the numeral system standardizing number is carried out the four bit arithmetic results that gating is exported hybrid adder at the corresponding levels unit, wherein n is a natural number.
Said input data strobe device is 4 bit parallel structures; Every bit architecture is identical; Wherein one structure comprises: the one or two input and door, the two or two input and door, the three or two input and door, the four or two input and door, first not gate, second not gate, the 3rd not gate, two input nand gates, two inputs or door, the one or two input selector and the two or two input selector; The low level of performance period counting controling signal connects an input end of the one or two input and door; The high position of performance period counting controling signal connects another input end of the one or two input and door through first not gate; The one or two input and output termination the two or two input of door and an input end of door; The numeral system control signal connects another input end of the two or two input and door; The AS control end of output termination the one or two input selector of the two or two input and door, the low level of performance period counting controling signal and high-order two input ends as two input nand gates, the numeral system control signal connects an input end of two inputs or door through second not gate; Output termination two inputs of two input nand gates or another input end of door; AS control end and the BS control end of the one or two input selector of output termination the two or two input selector of two inputs or door, the high position of performance period counting controling signal connect an input end of the three or two input and door, and the low level of performance period counting controling signal connects another input end of the three or two input and door through the 3rd not gate; The three or two input and output termination the four or two input of door and an input end of door; The numeral system control signal connects another input end of the four or two input and door, the BS control end of output termination the two or two input selector of the four or two input and door, and wherein a positional operand a connects the B data terminal of the one or two input selector; Connect the A data terminal of the two or two input selector with the operand b of operand a identical bits; Connect the A data terminal of the one or two input selector and the B data terminal of the two or two input selector with the numeral system standardizing number of operand a identical bits, the one or two input selector is output as a operand of gating, and the two or two input selector is output as the b operand of gating.
Said operand a data latching controller is identical with the structure of operand b data latching controller; Be 4 bit parallel structures; Every structure comprises: the one or two input and door, the two or two input and door, the three or two input and door, first phase inverter, second phase inverter, the 3rd phase inverter, two inputs or door, two input rejection gate, two input selectors and triggers; The non-AS control end that connects two input selectors of numeral system control signal; The numeral system control signal connects the BS control end of two input selectors; The operand of gating connects the A data terminal of two input selectors and the D data terminal of trigger respectively; The low level of performance period counting controling signal connects an input end of the two or two input and door and the three or two input and door; The performance period counting controling signal through second phase inverter connect the one or two the input with the door an input end, the high position of performance period counting controling signal through the 3rd phase inverter connect the one or two the input with the door with the three or two the input with the door another input end, the high position of performance period counting controling signal connect the two or two the input with another input end; The one or two input is imported two input ends that connect two inputs or door with the output of door with door and the two or two; The output of two inputs or door connects the clock end of trigger, and the output of trigger connects an input end of two input rejection gates through first phase inverter, and the three or two input and the output of door connect another input end of two input rejection gates; The output of two input rejection gates connects the B data terminal of two input selectors, the operand after two input selectors are output as and latch.
The structure of said four totalizers comprises: first full adder, second full adder, the 3rd full adder, the 4th full adder, four input rejection gate, phase inverter and two input selectors; First full adder, second full adder, the 3rd full adder and the 4th full adder are connected by ripple carry; Latch a data and receive the A data input pin of first full adder, second full adder, the 3rd full adder and the 4th full adder respectively; Latch the b data and receive the B data input pin of first full adder, second full adder, the 3rd full adder and the 4th full adder respectively; The carry composite signal of low one-level connects the carry input C of first full adder and the B data terminal of two input selectors; The carry output terminal CA of first full adder meets the carry input C of second full adder; The carry output terminal CA of second full adder meets the carry input C of the 3rd full adder; The carry output terminal CA of the 3rd full adder meets the carry input C of the 4th full adder, and the carry output terminal CA of the 4th full adder connects the A data terminal of two input selectors, and four carries of first full adder, second full adder, the 3rd full adder and the 4th full adder are transmitted four input ends that signal end PN connects four input rejection gates; The output of four input rejection gates connects the AS control end of two input selectors and the input end of phase inverter respectively; The output of phase inverter connects the BS control end of two input selectors, the S end output four bit arithmetic results of first full adder, second full adder, the 3rd full adder and the 4th full adder, and two input selectors are output as the carry signal of four totalizers.
The structure of said full adder comprises: two input rejection gates, the one or two input nand gate, the two or two input nand gate, the three or two input nand gate, the four or two input nand gate, the five or two input nand gate, the one or two input or door, the two or two input or door, first phase inverter and second phase inverter; A data input pin and B data input pin are as two inputs of two input rejection gates; Two input rejection gates are output as carry and transmit signal end PN; A data input pin and B data input pin are as two inputs of the one or two input nand gate simultaneously; The one or two input nand gate is output as carry and produces signal end GN; A data input pin and B data input pin are as two inputs of the one or two input or door; The output of the one or two input or door and the output of the one or two input nand gate connect two inputs of the two or two input nand gate; The two or two input nand gate is output as the false add operation result, and the false add operation result connects the input of first phase inverter, and the output of first phase inverter connects an input end of the two or two input or door and the three or two input nand gate; Carry input C connects another input of the two or two input or door and the three or two input nand gate; The output of the two or two input or door and the output of the three or two input nand gate connect two inputs of the four or two input nand gate, and the output of the four or two input nand gate connects the input of second phase inverter, and second phase inverter is output as the operation result of full adder; The output of the one or two input nand gate and the output of the three or two input nand gate connect two inputs of the five or two input nand gate, and the five or two input nand gate is output as the carry output terminal CA of full adder.
The structure that said numerical value overflows determining device comprises: two inputs or door, two input nand gates and phase inverter; Second of four totalizer and tertiary operation result connect two input ends of two inputs or door; The output of four totalizer most significant digit operation results and two inputs or door connects two input ends of two input nand gates, and the output of two input nand gates obtains decimal number binary-coded decimal spill over after through phase inverter.
The structure of said numeral system carry compositor comprises: two input selectors and phase inverter; The numeral system control signal connects the AS control end of two input selectors and the input end of phase inverter respectively; The output of phase inverter connects the BS control end of two input selectors; Decimal number binary-coded decimal spill over connects the A data terminal of two input selectors, and the carry signal of four totalizers connects the B data terminal of two input selectors, and two input selectors are output as the carry composite signal of hybrid adder at the corresponding levels unit.
The structure of said numeral system normalizer comprises: first full adder, second full adder and XOR gate; The lowest order operation result of four totalizers is directly output as the lowest order of decimal normalization number; The second bit arithmetic result of four totalizers inserts the A input end of first full adder; The 3rd bit arithmetic result of four totalizers inserts the A data terminal of second full adder; Decimal number binary-coded decimal spill over connects the B data terminal of first full adder, second full adder, the carry input C ground connection of first full adder, and the carry output terminal CA of first full adder meets the carry input C of second full adder; The carry output terminal CA of second full adder and the most significant digit operation result of four totalizers connect two input ends of XOR gate respectively; XOR gate is output as the most significant digit of decimal normalization number, and the operation result of first full adder is output as second of decimal normalization number, and the operation result of second full adder is output as the 3rd of decimal normalization number.
Said mixing numeral system four bit arithmetics gate as a result are four bit parallel structures; Every bit architecture is identical; Wherein one structure comprises: first phase inverter, second phase inverter, the one or two input and door, the two or two input and door and two input selectors; The numeral system control signal connects the input of second phase inverter; The output of second phase inverter connects the AS control end of two input selectors; The low level of performance period counting controling signal connects the input of first phase inverter, and the high position of the output of first phase inverter and performance period counting controling signal connects two input ends of the one or two input and door, output and the numeral system control signal of the one or two input and door connect the two or two input with two input ends; The output of the two or two input and door connects the BS control end of two input selectors; A wherein bit arithmetic result of four totalizers connects the A data terminal of two input selectors, connects the B data terminal of two input selectors with the decimal normalization number of the operation result identical bits of four totalizers, and two input selectors are output as a bit arithmetic result of hybrid adder unit.
The present invention compared with prior art has the following advantages:
(1) mixed numerical system summator cellular construction of the present invention is simple, area is little, low in energy consumption, be convenient on chip, realize, strengthened the practicality of Embedded Application.
(2) calculating figure place of the present invention can be expanded according to computation requirement flexibly, and adaptability is strong.
(3) the present invention adopts hardware approach to realize the computing of different numeral systems, has avoided the conversion of software numeral system, has improved the operation efficiency that mixes numeral system.
(4) the present invention can realize the decimal number computing that binary arithmetic and binary-coded decimal are represented, treatment scheme is simple, is easy to control, has improved mixing numeral system computation's reliability.
Description of drawings
Fig. 1 is that the structure of mixed numerical system summator of the present invention is formed synoptic diagram;
Fig. 2 is the workflow diagram of hybrid adder of the present invention unit;
Fig. 3 is that the present invention imports in the data strobe device wherein one structure and forms synoptic diagram;
Fig. 4 is wherein one a structure composition synoptic diagram of operand a data latching controller of the present invention;
Fig. 5 is wherein one a structure composition synoptic diagram of operand b data latching controller of the present invention;
Fig. 6 is that the structure of 4 totalizers of the present invention is formed synoptic diagram;
Fig. 7 is that the structure of full adder among Fig. 6 is formed synoptic diagram;
Fig. 8 is the structure composition synoptic diagram that numerical value of the present invention overflows determining device;
Fig. 9 is that the structure of numeral system carry compositor of the present invention is formed synoptic diagram;
Figure 10 is that the structure of numeral system normalizer of the present invention is formed synoptic diagram;
Figure 11 be the present invention mix numeral system 4 bit arithmetics as a result gate wherein one structure form synoptic diagram.
Embodiment
Understand the present invention for clearer, the present invention is made further detailed description below in conjunction with accompanying drawing.
As shown in Figure 1, mixed numerical system summator mainly is made up of the hybrid adder unit, realizes a n (n=4i; I=1 wherein, 2,3; 4; 5.......) hybrid adder of position, need n/4 hybrid adder unit to form, the ripple carry of carry employing little-endian is the carry input in 4 totalizers of the output of the numeral system carry compositor of the low level hybrid adder unit hybrid adder unit that inserts an adjacent high position.Additive operation and one group of decimal number computing that 4 binary-coded decimals are represented of one group 4 binary number can be realized in a hybrid adder unit.Hybrid adder unit by an input data strobe device, operand a data latching controller, operand b data latching controller, 4 totalizer, numeral system carry compositor, numerical value overflow determining device, numeral system normalizer, one mix numeral system 4 bit arithmetics as a result gate form.The annexation of functional module is as shown in Figure 2 in the mixed adder unit, and two output terminals (opa_sel and opb_sel) of input data strobe device are connected respectively to the input end of operand a data latching controller and operand b data latching controller; The output opa_out of operand a data latching controller is connected to the 4 positional operands input a end of 4 totalizers of 4 totalizers, and the output opb_out of operand b data latching controller is connected to the 4 positional operands input b end of 4 totalizers; The operation result s of 4 totalizers is connected to numerical value and overflows determining device and numeral system normalizer and mix the numeral system 4 bit arithmetics input end of gate as a result; The computing carry output (c_out) of 4 totalizers is connected to the input end of numeral system carry compositor; The output (ov) that numerical value overflows determining device is connected to numeral system normalizer and numeral system carry compositor; The output of numeral system normalizer (s_n) is connected to and mixes numeral system 4 bit arithmetics gate and input data strobe device as a result; The output of numeral system carry compositor (c_mix_out (n)) is the carry output of n hybrid adder unit; Mixing the numeral system 4 bit arithmetics outputs of gate as a result (s_out) is the operation result output of n hybrid adder unit.Structure with Fig. 1 is the basis, according to the treatment scheme of Fig. 2 hybrid adder unit, realizes that binary addition needs one-period.Realize that metric addition needs 3 cycles, first cycle standardizes to a operand, latchs the b operand simultaneously; The 2nd cycle standardizes to latching the b operand, latchs the normalized result of a operand simultaneously; The 3rd cycle latched the normalized result of b operand, carries out the decimal addition of two normalization operation numbers simultaneously.Realize the mixed numerical system summator of a n=16 position; Want n/4=4 hybrid adder unit; Its connected mode is with to form structure as shown in Figure 1, and it is the carry input in 4 totalizers of the numeral system carry compositor output of the low level hybrid adder unit hybrid adder unit that inserts an adjacent high position that carry adopts the ripple carry of little-endian.
The input signal of input data strobe device is that operand a, operand b, normalization operation count s_n, performance period counting controling signal cycle, numeral system control signal type; The output signal is the operand opa_sel and the opb_sel of gating, and performance period counting controling signal cycle adopts binary representation, cycle=0; Be cycle (0)=0, cycle (1)=0, cycle=1; Be cycle (0)=1, cycle (1)=0, cycle=2; Be cycle (0)=0, cycle (1)=1.The function of input data strobe device is: according to numeral system control signal type and performance period counting controling signal cycle, and control gating operand; When type=0, expression is a binary arithmetic, simultaneously gating operand a and operand b; When type=1, expression is decimal arithmetic, and according to cycle gating operand, cycle=0 is gating operand a and operand b simultaneously, cycle=1, and it is opa_sel that s_n is counted in the gating normalization operation, cycle=2, it is opb_sel that s_n is counted in the gating normalization operation.The input data strobe device is the structure of 4 bit parallels; Every bit architecture is identical; One structure is as shown in Figure 3 in the input data strobe device: performance period counting controling signal cycle (0) connects the input of the one or two input and door And_1; Cycle (1) connects another input of the one or two input and door And_1 through the first not gate Inv_1; The output of the one or two input and door And_1 connects the input of the two or two input and door And_2, and numeral system control signal type connects another input of the two or two input and door And_2, and the two or two input connects the AS control end of the one or two input selector mux_1 with the output of door And_2; Performance period counting controling signal cycle (0) and cycle (1) connect two input ends of two input nand gate Nand_1; Numeral system control signal type connects the input end of the second not gate Inv_2; The output of the output of two input nand gate Nand_1 and the second not gate Inv_2 connects two inputs of two inputs or door Or_1, and the output of two inputs or door Or_1 connects the AS control end of the two or two input selector mux_2 and the BS control end of the one or two input selector mux_1; Performance period counting controling signal cycle (1) connects the input of the three or two input and door And_3; Performance period counting controling signal cycle (0) connects the input of the 3rd not gate Inv_3; The output of the 3rd Inv_3 connects another input of the three or two input and door And_3; The output of the three or two input and door And_3 connects the input of the four or two input and door And_4; Numeral system control signal type connects another input of the four or two input and door And_4, and the four or two imports the BS control end that meets the two or two input selector mux_2 with the output of an And_4; Operand a (i) connects the B data terminal of the one or two input selector mux_1, and the A data terminal that s_n (i) meets the one or two input selector mux_1 is counted in normalization operation, and the one or two input selector mux_1 is output as the operand opa_sel (i) of gating; The B data terminal that s_n (i) meets the two or two input selector mux_2 is counted in normalization operation, and operand b (i) connects the A data terminal of the two or two input selector mux_2, and the two or two input selector mux_2 is output as the operand opb_sel (i) of gating.
The input signal of operand a data latching controller is operand opa_sel, performance period counting controling signal cycle, the numeral system control signal type of gating; The output signal is opa_out.The function of operand a data latching controller is: latch a operand according to numeral system control signal type and performance period counting controling signal cycle control; When type=0; Expression is a binary arithmetic, and the operand opa_sel of gating directly is connected to the 4 positional operands input a end of 4 totalizers as output signal opa_out; When type=1, expression is decimal arithmetic, latchs the control operation number according to cycle; Cycle=0; Latch opa_sel and latch result outputed to the 4 positional operands inputs a end of 4 totalizers, cycle=1, latch opa_sel and with latch result put 0 output to 4 totalizers 4 positional operands input a end; Cycle=2 outputs to latch result at the 4 positional operands input a end of 4 totalizers.Operand a data latching controller is the structure of 4 bit parallels, and every bit architecture is identical, and one structure is as shown in Figure 4 in the operand a data latching controller: the non-type of type signal connects the AS control end of two input selector mux_1; The type signal connects the BS control end of two input selector mux_1; Opa_sel (i) connects the A data terminal of mux_1; The operand opa_sel (i) of gating connects the D data terminal of trigger DFF_1; Cycle (0) connects the input end of the two or two input and door And_2 and the three or two input and door And_3; Cycle (0) connects the input end of the one or two input and door And_1 through the second phase inverter Inv_2; Cycle (1) connects the one or two input and door And_1 the three or two input another input end with door And_3 through the 3rd phase inverter Inv_3; Cycle (1) connects another input end of the two or two input and door And_2; The one or two input and door And_1 and the two or two input and the output of door And_2 connect two input ends of two inputs or door Or_1, and the output of two inputs or door Or_1 connects the CLK clock end of trigger DFF_1, the output of trigger DFF_1 through the first phase inverter Inv_1 connect two import rejection gate Nor_1 an input end; The output of the three or two input and door And_3 connects another input end of two input rejection gate Nor_1, and the output of two input rejection gate Nor_1 connects the B data terminal of two input selector mux_1; Two input selector mux_1 are output as output signal opa_out (i).
The structure of operand b data latching controller is identical with the structure of operand a data latching controller.The input signal of operand b data latching controller is operand opb_sel, performance period counting controling signal cycle, the numeral system control signal type of gating; The output signal is opb_out.The function of operand a data latching controller is: latch the b operand according to numeral system control signal type and performance period counting controling signal cycle control; When type=0; Expression is a binary arithmetic, and the operand opb_sel of gating directly is connected to the 4 positional operands input b end of 4 totalizers as output signal opb_out; When type=1, expression is decimal arithmetic, latchs the control operation number according to cycle; Cycle=0; Latch opb_sel and latch result outputed to the 4 positional operands inputs b end of 4 totalizers, cycle=1, latch opb_sel and with latch result put 0 output to 4 totalizers 4 positional operands input b end; Cycle=2 outputs to latch result at the 4 positional operands input b end of 4 totalizers.Operand b data latching controller is the structure of 4 bit parallels, and every bit architecture is identical, and one structure is as shown in Figure 5 in the operand b data latching controller: the non-type of type signal connects the AS control end of two input selector mux_1; The type signal connects the BS control end of two input selector mux_1; Opb_sel (i) connects the A data terminal of mux_1; The operand opb_sel (i) of gating connects the D data terminal of trigger DFF_1; Cycle (0) connects the input end of the two or two input and door And_2 and the three or two input and door And_3; Cycle (0) connects the input end of the one or two input and door And_1 through the second phase inverter Inv_2; Cycle (1) connects another input end of the one or two input and a door And_1, the three or two input and door And_3 through the 3rd phase inverter Inv_3; Cycle (1) connects another input end of the two or two input and door And_2; The one or two input and door And_1 and the two or two input and the output of door And_2 connect two input ends of two inputs or door Or_1, and the output of two inputs or door Or_1 connects the CLK clock end of trigger DFF_1, the output of trigger DFF_1 through the first phase inverter Inv_1 connect two import rejection gate Nor_1 an input end; The output of the three or two input and door And_3 connects another input end of two input rejection gate Nor_1, and the output of two input rejection gate Nor_1 connects the B data terminal of two input selector mux_1; Two input selector mux_1 are output as output signal opb_out (i).
The input signal of 4 totalizers is operational data opa_out, opb_out, the carry composite signal c_mix_out (n-1) of low one-level; The output signal is operation result s, carry signal c_out.Its function is: carry out the computing of 4 bit additions.In order to improve the speed of transmitting; Ripple carry adder structure to traditional is improved; The structure of 4 totalizers is as shown in Figure 6: 4 full adder FA_1, FA_2, FA_3 and FA_4 are connected by ripple carry; Input data opa_out (i+3; I), opb_out (i+3; I) by in proper order separately parallel A data input pin and the B data input pin of receiving full adder FA_1, FA_2, FA_3 and FA_4 of high low level, the carry composite signal c_mix_out (n-1) of low one-level connects the carry input C of lowest order full adder FA_1 and the B data terminal of two input selector mux_1, and the carry output signals CA of full adder FA_2 meets the carry input C of full adder FA_3; The carry output signals CA of full adder FA_3 meets the carry input C of full adder FA_4, and the carry output signals CA of full adder FA_4 connects the A data terminal of two input selector mux_1; 4 carries of full adder FA_1, FA_2, FA_3 and FA_4 are transmitted 4 input ends that signal PN meets four input rejection gate Nor_1; The output of four input rejection gate Nor_1 connects the AS control end of two input selector mux_1 and the input end of phase inverter Inv_1 respectively, the BS control end of the output two input selector mux_1 of phase inverter Inv_1; The S of full adder FA_1, FA_2, FA_3 and FA_4 end be output as operation result s (i+3, i); Two input selector mux_1 are output as the carry signal c_out of 4 totalizers.
In 4 totalizers, the structure of each full adder is identical, and is as shown in Figure 7: A data input pin and B data input pin connect two inputs of two input rejection gate Nor_1, and Nor_1 is output as carry and transmits signal PN; A data input pin and B data input pin connect two inputs of the one or two input nand gate Nand_1 simultaneously, and the one or two input nand gate Nand_1 is output as carry and produces signal GN; A data input pin and B data input pin connect two inputs of the one or two input or door Or_1; The output of the one or two input or door Or_1 and the output of the one or two input nand gate Nand_1 connect two inputs of the two or two input nand gate Nand_2, and the two or two input nand gate Nand_2 is output as false add operation result HN; False add operation result HN connects the input of the first phase inverter Inv_1; The output of the first phase inverter Inv_1 connects the input of the two or two input or door Or_2 and the three or two input nand gate Nand_3; Carry input C connects another input of the two or two input or door Or_2 and the three or two input nand gate Nand_3; The output of the two or two input or door Or_2 and the output of the three or two input nand gate Nand_3 connect two input ends of the four or two input nand gate Nand_4; The output of the four or two input nand gate Nand_4 connects the input of the second phase inverter Inv_2, and the second phase inverter Inv_2 is output as the operation result S of full adder; The output of the one or two input nand gate Nand_1 and the output of the three or two input nand gate Nand_3 connect two inputs of the five or two input nand gate Nand_5, and the five or two input nand gate Nand_5 is output as the carry output signals CA of full adder.
The input signal that numerical value overflows determining device is the operation result S of 4 totalizers; Be output as decimal number binary-coded decimal spill over OV.The function that numerical value overflows determining device is: produce the carry signal in the decimal arithmetic.Overflowing judgment mode has a variety ofly, in order to reduce circuit power consumption, to reduce chip area, has adopted a kind of method of deciphering judgement, promptly when decimal system binary-coded decimal value greater than 1010, then overflow determining device and produce spill over OV.Its structure is as shown in Figure 8: import the Senior Three position among the operation result S that only needs 4 totalizers; S (i+3), S (i+2) and S (i+1); S (i+2) and S (i+1) connect two inputs of two inputs or door Or_1; The output of two inputs or door Or_1 and two inputs that S (i+3) meets two input nand gate Nand_1, the output of two input nand gate Nand_1 connects the input of phase inverter Inv_1, and phase inverter Inv_1 is output as the output OV that numerical value overflows determining device.
The input signal of numeral system carry compositor is decimal number binary-coded decimal spill over OV, computing carry signal c_out, numeral system control signal type.Its effect is: according to numeral system control signal type, and gating computing carry signal c_out.The structure of numeral system carry compositor is as shown in Figure 9: numeral system control signal type signal connects the AS control end of two input selector mux_1 and the input end of phase inverter Inv_1 respectively, and the output of phase inverter Inv_1 connects the BS control end of two input selector mux_1; Decimal number binary-coded decimal spill over OV connects the A data terminal of two input selector mux_1; Computing carry signal c_out connects the B data terminal of two input selector mux_1, and two input selector mux_1 are output as the carry composite signal c_mix_out (n) of (the harmless n level that is assumed to be) at the corresponding levels.
The input signal of numeral system normalizer is the operation result S of 4 totalizers, decimal number binary-coded decimal spill over OV; The output signal is standardizing number s_n.The effect of numeral system normalizer: the operation result to 4 totalizers carries out metric normalization operation, makes it become the binary-coded decimal of standard.Normalized method, for the decimal normalization operation, common way is (s-10)
10=(s-1010)
2, in order to simplify computing, improving processing speed, the present invention has adopted the method for addition constant, i.e. (s-1010)
2=(s)
Mend-(1010)
Mend=(s)
Mend+ (0101+0001)
Mend=(s+0110)
2The structure of numeral system normalizer is shown in figure 10: the lowest order s (i) of the operation result of 4 totalizers is directly output as the lowest order s_n (i) of decimal normalization number; S (i+1), the parallel respectively A input end that inserts full adder FA_1, FA_2 in s (i+2) position; Decimal number binary-coded decimal spill over OV connects the B input end of full adder FA_1, FA_2; The carry input C ground connection of FA_1; The carry output terminal CA of full adder FA_1 meets the carry input C of full adder FA_2, and the carry output terminal CA of full adder FA_2 and s (i+3) connect two input ends of XOR gate Xor_1; XOR gate Xor_1 is output as the most significant digit s_n (i+3) of decimal normalization number; The operation result of full adder FA_2 is output as the inferior high-order s_n (i+2) of decimal normalization number; The operation result of full adder FA_1 is output as s_n (i+1) position of decimal normalization number.The structure of full adder FA_1, FA_2 is identical with full adder structure shown in Figure 7 among Figure 10.
The mixing numeral system 4 bit arithmetics input signal of gate as a result are that s_n is counted in decimal normalization, the operation result s of 4 totalizers, performance period counting controling signal cycle, numeral system control signal type; The output signal is the operation result s_out of hybrid adder unit.Mix the effect of gate as a result of numeral system 4 bit arithmetics: be according to numeral system control signal type and performance period counting controling signal cycle gating output operation result; When type=0, expression is a binary arithmetic, directly exports the operation result of 4 totalizers; During type=1, expression is decimal arithmetic, when cycle=2, and the result of output numeral system normalizer.Mixing numeral system 4 bit arithmetics gate as a result are the structures of 4 bit parallels; Every bit architecture is identical; Mix numeral system 4 bit arithmetics as a result in the gate one structure shown in figure 11: numeral system control signal type signal connects the input of the second phase inverter Inv_2, and the output of the second phase inverter Inv_2 connects the AS control end of two input selector mux_1; Performance period counting controling signal cycle (0) connects the input of the first phase inverter Inv_1; The output of the first phase inverter Inv_1 and performance period counting controling signal cycle (1) connect two inputs of the one or two input and door And_1; The output of the one or two input and door And_1 and numeral system control signal type connect two inputs of the two or two input and door And_2, and the two or two imports the BS control end that meets two input selector mux_1 with the output of door And_2; I position s (i) of operation result connects the A data terminal of two input selector mux_1; The several i of decimal normalization position s_n (i) connect the B data terminal of two input selector mux_1; Two input selector mux_1 are output as the operation result i position s_out (i) of hybrid adder unit.
The present invention not detailed description is a technology as well known to those skilled in the art.
Claims (9)
1. mixed numerical system summator; It is characterized in that: constitute by n four hybrid adder unit; Each hybrid adder unit comprises that input data strobe device, operand a data latching controller, operand b data latching controller, four totalizers, numeral system carry compositor, numerical value overflow determining device, numeral system normalizer, mix numeral system four bit arithmetics gate as a result; Four positional operand a and four positional operand b insert the data input pin of input data strobe device respectively; The input data strobe device carries out gating to the four positional operand a and the four positional operand b of input under the control of numeral system control signal and performance period counting controling signal; The input end of gating result transmission to the operand a data latching controller of input data strobe device and the input end of operand b data latching controller; Operand a data latching controller and operand b data latching controller four positional operand a and the four positional operand b to gating under the control of numeral system control signal and performance period counting controling signal latch; The latch result of operand a data latching controller and operand b data latching controller inserts four positional operand input ends of four totalizers; Wherein the latch result of operand a data latching controller inserts four positional operand first input ends of four totalizers; The latch result of operand b data latching controller inserts four positional operands, second input end of four totalizers; Four totalizers are carried out the tetrad additive operation to four positional operand a and the four positional operand b that latch; Four bit arithmetic results of four totalizers insert numerical value respectively and overflow determining device, numeral system normalizer and mix the numeral system four bit arithmetics input end of gate as a result; The computing carry output of four totalizers inserts the input end of numeral system carry compositor; Numerical value overflows determining device to carry out numerical value according to four bit arithmetic results of four totalizers and overflows and judge output decimal number binary-coded decimal spill over; Decimal number binary-coded decimal spill over inserts numeral system normalizer and numeral system carry compositor; The numeral system normalizer becomes four bit arithmetic results of four totalizers the numeral system standardizing number of standard binary-coded decimal through the decimal normalization operational transition according to decimal number binary-coded decimal spill over; Numeral system carry compositor carries out gating according to the numeral system control signal to the computing carry and the decimal number binary-coded decimal spill over of four totalizers; Output inserts in the adjacent high-order hybrid adder unit carry input in four totalizers as the carry of hybrid adder at the corresponding levels unit in the output of numeral system carry compositor; The numeral system standardizing number of numeral system normalizer output inserts mixes numeral system four bit arithmetics gate and the selection input end of importing data strobe device as a result; Mix numeral system four bit arithmetics as a result gate under the control of numeral system control signal and performance period counting controling signal, four of four totalizers are exported the result and the numeral system standardizing number is carried out the four bit arithmetic results that gating is exported hybrid adder at the corresponding levels unit, wherein n is a natural number.
2. a kind of mixed numerical system summator according to claim 1; It is characterized in that: said input data strobe device is 4 bit parallel structures; Every bit architecture is identical; Wherein primary structure comprises: the one or two input and door, the two or two input and door, the three or two input and door, the four or two input and door, first not gate, second not gate, the 3rd not gate, two input nand gates, two inputs or door, the one or two input selector and the two or two input selector; The low level of performance period counting controling signal connects an input end of the one or two input and door; The high position of performance period counting controling signal connects another input end of the one or two input and door through first not gate; The one or two input and output termination the two or two input of door and an input end of door; The numeral system control signal connects another input end of the two or two input and door; The AS control end of output termination the one or two input selector of the two or two input and door, the low level of performance period counting controling signal and high-order two input ends as two input nand gates, the numeral system control signal connects an input end of two inputs or door through second not gate; Output termination two inputs of two input nand gates or another input end of door; AS control end and the BS control end of the one or two input selector of output termination the two or two input selector of two inputs or door, the high position of performance period counting controling signal connect an input end of the three or two input and door, and the low level of performance period counting controling signal connects another input end of the three or two input and door through the 3rd not gate; The three or two input and output termination the four or two input of door and an input end of door; The numeral system control signal connects another input end of the four or two input and door, the BS control end of output termination the two or two input selector of the four or two input and door, wherein first of four positional operand a B data terminal that connects the one or two input selector; First A data terminal that connects the two or two input selector of four positional operand b; The first figure place system standardizing number connects the A data terminal of the one or two input selector and the B data terminal of the two or two input selector, and the one or two input selector is output as first among the four positional operand a of gating, and the two or two input selector is output as first among the four positional operand b of gating.
3. a kind of mixed numerical system summator according to claim 1; It is characterized in that: said operand a data latching controller is identical with the structure of operand b data latching controller; Be 4 bit parallel structures; Every structure comprises: the one or two input and door, the two or two input and door, the three or two input and door, first phase inverter, second phase inverter, the 3rd phase inverter, two inputs or door, two input rejection gate, two input selectors and triggers; The non-AS control end that connects two input selectors of numeral system control signal; The numeral system control signal connects the BS control end of two input selectors; The operand of gating connects the A data terminal of two input selectors and the D data terminal of trigger respectively, the low level of performance period counting controling signal connect the two or two the input with the door with the three or two the input with the door an input end, the performance period counting controling signal through second phase inverter connect the one or two the input with an input end; The high position of performance period counting controling signal connects another input end of the one or two input and door and the three or two input and door through the 3rd phase inverter; The high position of performance period counting controling signal connects another input end of the two or two input and door, and the one or two input and door and the two or two input and the output of door connect two input ends of two inputs or door, two inputs or output connect the clock end of trigger; The output of trigger connects an input end of two input rejection gates through first phase inverter; The output of the three or two input and door connects another input end of two input rejection gates, and the output of two input rejection gates connects the B data terminal of two input selectors, the operand after two input selectors are output as and latch.
4. a kind of mixed numerical system summator according to claim 1; It is characterized in that: the structure of said four totalizers comprises: first full adder, second full adder, the 3rd full adder, the 4th full adder, four input rejection gate, phase inverter and two input selectors; First full adder, second full adder, the 3rd full adder and the 4th full adder are connected by ripple carry; Latch a data and receive the A data input pin of first full adder, second full adder, the 3rd full adder and the 4th full adder respectively; Latch the b data and receive the B data input pin of first full adder, second full adder, the 3rd full adder and the 4th full adder respectively; The carry composite signal of low one-level connects the carry input C of first full adder and the B data terminal of two input selectors; The carry output terminal CA of first full adder meets the carry input C of second full adder; The carry output terminal CA of second full adder meets the carry input C of the 3rd full adder; The carry output terminal CA of the 3rd full adder meets the carry input C of the 4th full adder, and the carry output terminal CA of the 4th full adder connects the A data terminal of two input selectors, and four carries of first full adder, second full adder, the 3rd full adder and the 4th full adder are transmitted four input ends that signal end PN connects four input rejection gates; The output of four input rejection gates connects the AS control end of two input selectors and the input end of phase inverter respectively; The output of phase inverter connects the BS control end of two input selectors, the S end output four bit arithmetic results of first full adder, second full adder, the 3rd full adder and the 4th full adder, and two input selectors are output as the carry signal of four totalizers.
5. a kind of mixed numerical system summator according to claim 4; It is characterized in that: the structure of said full adder comprises: two input rejection gates, the one or two input nand gate, the two or two input nand gate, the three or two input nand gate, the four or two input nand gate, the five or two input nand gate, the one or two input or door, the two or two input or door, first phase inverter and second phase inverter; A data input pin and B data input pin are as two inputs of two input rejection gates; Two input rejection gates are output as carry and transmit signal end PN; A data input pin and B data input pin are as two inputs of the one or two input nand gate simultaneously; The one or two input nand gate is output as carry and produces signal end GN; A data input pin and B data input pin are as two inputs of the one or two input or door; The output of the one or two input or door and the output of the one or two input nand gate connect two inputs of the two or two input nand gate; The two or two input nand gate is output as the false add operation result, and the false add operation result connects the input of first phase inverter, and the output of first phase inverter connects an input end of the two or two input or door and the three or two input nand gate; Carry input C connects another input of the two or two input or door and the three or two input nand gate; The output of the two or two input or door and the output of the three or two input nand gate connect two inputs of the four or two input nand gate, and the output of the four or two input nand gate connects the input of second phase inverter, and second phase inverter is output as the operation result of full adder; The output of the one or two input nand gate and the output of the three or two input nand gate connect two inputs of the five or two input nand gate, and the five or two input nand gate is output as the carry output terminal CA of full adder.
6. a kind of mixed numerical system summator according to claim 1; It is characterized in that: the structure that said numerical value overflows determining device comprises: two inputs or door, two input nand gates and phase inverter; Second of four totalizer and tertiary operation result connect two input ends of two inputs or door; The output of four totalizer most significant digit operation results and two inputs or door connects two input ends of two input nand gates, and the output of two input nand gates obtains decimal number binary-coded decimal spill over after through phase inverter.
7. a kind of mixed numerical system summator according to claim 1; It is characterized in that: the structure of said numeral system carry compositor comprises: two input selectors and phase inverter; The numeral system control signal connects the AS control end of two input selectors and the input end of phase inverter respectively; The output of phase inverter connects the BS control end of two input selectors; Decimal number binary-coded decimal spill over connects the A data terminal of two input selectors, and the carry signal of four totalizers connects the B data terminal of two input selectors, and two input selectors are output as the carry composite signal of hybrid adder at the corresponding levels unit.
8. a kind of mixed numerical system summator according to claim 1; It is characterized in that: the structure of said numeral system normalizer comprises: first full adder, second full adder and XOR gate; The lowest order operation result of four totalizers is directly output as the lowest order of decimal normalization number; The second bit arithmetic result of four totalizers inserts the A input end of first full adder; The 3rd bit arithmetic result of four totalizers inserts the A data terminal of second full adder; Decimal number binary-coded decimal spill over connects the B data terminal of first full adder, second full adder, the carry input C ground connection of first full adder, and the carry output terminal CA of first full adder meets the carry input C of second full adder; The carry output terminal CA of second full adder and the most significant digit operation result of four totalizers connect two input ends of XOR gate respectively; XOR gate is output as the most significant digit of decimal normalization number, and the operation result of first full adder is output as second of decimal normalization number, and the operation result of second full adder is output as the 3rd of decimal normalization number.
9. a kind of mixed numerical system summator according to claim 1; It is characterized in that: said mixing numeral system four bit arithmetics gate as a result are four bit parallel structures; Every bit architecture is identical; Wherein one structure comprises: first phase inverter, second phase inverter, the one or two input and door, the two or two input and door and two input selectors; The numeral system control signal connects the input of second phase inverter, and the output of second phase inverter connects the AS control end of two input selectors, and the low level of performance period counting controling signal connects the input of first phase inverter; The high position of the output of first phase inverter and performance period counting controling signal connects two input ends of the one or two input and door; The output of the one or two input and door and numeral system control signal connect two input ends of the two or two input and door, and the two or two imports the BS control end that connects two input selectors with the output of door, and a wherein bit arithmetic result of four totalizers connects the A data terminal of two input selectors; Connect the B data terminal of two input selectors with the decimal normalization number of the operation result identical bits of four totalizers, two input selectors are output as a bit arithmetic result of hybrid adder unit.
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