CN101707183B - Method for increasing breakdown voltage of power MOS field effect transistor - Google Patents
Method for increasing breakdown voltage of power MOS field effect transistor Download PDFInfo
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- CN101707183B CN101707183B CN200910199438A CN200910199438A CN101707183B CN 101707183 B CN101707183 B CN 101707183B CN 200910199438 A CN200910199438 A CN 200910199438A CN 200910199438 A CN200910199438 A CN 200910199438A CN 101707183 B CN101707183 B CN 101707183B
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Abstract
The invention provides a method for increasing breakdown voltage of a power MOS field effect transistor, comprising the following steps: etching out a first shallow groove in the substrate of the power MOS field effect transistor; depositing a first oxide layer in the first shallow groove; etching out a plurality of second shallow grooves in the first oxide layer; forming two polysilicon gates on the substrate and the first oxide layer; carrying out ion implantation on the surface of the substrate on the outer sides of the two polysilicon gates, thereby forming a first active region and a second active region; depositing a second oxide layer on the polysilicon gate; and fabricating a field plate on the second oxide layer. The method not only eliminates the included angle formed during the growth process of the polysilicon in the power MOS field effect transistor, but also disperses the electric field strength on the surface of the power MOS field effect transistor, thereby reducing the electric field strength on the surface of the power MOS field effect transistor to the utmost extent and increasing the breakdown voltage of power MOS field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method that improves breakdown voltage of power MOS field effect transistor.
Background technology
MOS field effect tube uses existing historical for many years, the improvement that its design and manufacturing approach are continuing always.The English full name of MOS is that Metal-Oxide-Semiconductor is a Metal-oxide-semicondutor; Definite says; This WD the structure of MOS field effect tube in the integrated circuit, that is: on the semiconductor device of a fixed structure, add silicon dioxide and metal.Say from structure; Metal-oxide-semiconductor can be divided into enhancement mode (E type) and depletion type (D type); MOS field effect tube effect pipe generally has 3 electrodes: source (source) utmost point, leakage (drain) utmost point and grid (gate) utmost point, and the circuit that MOS field effect tube forms is commonly referred to as the MOS circuit, but difference is arranged; The PMOS logical circuit is called the PMOS circuit; The NMOS logical circuit is called nmos circuit, and the common logical circuit of forming of PMOS and NMOS is called the CMOS integrated circuit, and the circuit that MOS and BJT (Bipolar Junction Transistor bipolar junction transistor) form is called the Bi-CMOS integrated circuit.Because the MOS field effect tube quiescent dissipation is almost 0, all power consumptions all concentrate in the process of switch transition, therefore relative BJT, and the power consumption of MOS field effect tube is lower.Therefore, in the industrial design, MOS field effect tube is mainly used in and realizes switching logic (0,1 logic) in the Digital Logical Circuits in modern times.On performance, MOS field effect tube mainly is to develop towards low on-resistance (Rdson), high withstand voltage, high-frequency direction.
Terminal protection structure is an important link of MOS field effect tube design.MOS field effect tube; Need bear higher reverse voltage during work; The surface potential that is positioned between each parallelly connected unit cell array of active area in the middle of the device is roughly the same; And be positioned at the unit cell at active area edge (being the terminal) and the current potential of substrate surface differs greatly, thereby the surface field that often causes the outer ring unit cell is too concentrated and is caused the edge of device breakdown.Therefore, need increase terminal protection structure in the outer ring of unit cell array, reduce the terminal electric field density, play and improve the withstand voltage effect of MOS field effect tube, the general terminal protection structure that adopts is a field plate.
Fig. 1 is the structural representation of prior art MOS field effect tube; Only provided the structural representation in MOS field effect tube left side among the figure; The making step of MOS field effect tube is following: growth first oxide layer 12 on the substrate 10 of MOS field effect tube; And first oxide layer 12 carried out etching, so that carry out the preparation of active area; On first oxide layer 12, form two polysilicon gates, polysilicon gate is made up of gate oxide 13 and polysilicon layer 14, carries out ion again in the outside of two polysilicon gates and injects, and forms two active areas 11 (only showing one of which among the figure); Growth regulation dioxide layer 15 on polysilicon layer 14; On second oxide layer 15, make field plate 16.In the prior art; The preparation technology of first oxide layer is very big to the influence of device performance; Because when active area 11 carries out the transition to first oxide layer 12, can form angle at polysilicon gate in transition region 55, thereby make electric field concentrate the place to become breakdown point, more bad is when puncture occurs in angle; Electronics is easy to be injected in the grid oxygen (i.e. second oxide layer 15); Reliability to device makes a big impact, and increase this angle (being equivalent to reduce the wedge angle of first oxide layer) and can weaken concentrating of electric field, but etching first oxide layer and the suitable difficulty of technology of controlling its wedge angle even can not realize.
Summary of the invention
Polysilicon exists angle to cause the MOS field effect to be prone to breakdown problem in the MOS field effect that exists in the prior art in order to solve, and the present invention provides a kind of method of the MOS of raising field effect puncture voltage.
To achieve these goals, the present invention proposes a kind of method that improves breakdown voltage of power MOS field effect transistor, said method comprising the steps of: etching forms first shallow trench in the substrate of said MOS field effect tube; Deposit first oxide layer in said first shallow trench, and said first oxide layer carried out etching and grinding, remove said first oxide layer on the said substrate; Etching forms a plurality of second shallow trenchs in said first oxide layer; On said substrate and said first oxide layer, form two polysilicon gates, again with said polysilicon gate very the substrate surface of barrier layer in two said polysilicon gates outsides carry out ion and inject, form first active area and second active area; Deposit second oxide layer on said polysilicon gate; On said second oxide layer, make field plate.
Optional, said first oxide layer is a silicon oxide layer.
Optional, said second oxide layer is a silicon oxide layer.
Optional, said polysilicon gate is made up of the 3rd oxide layer and polysilicon layer.
Optional, said the 3rd oxide layer is a silicon oxide layer.
Optional, said grinding is a cmp.
Optional, the degree of depth of said second shallow trench is the half the of the said first shallow trench degree of depth.
A kind of useful technique effect that improves the method for breakdown voltage of power MOS field effect transistor of the present invention is: MOS field effect tube provided by the invention; First oxide layer is designed in the substrate of MOS field effect tube; Eliminate the formed angle of polysilicon in the field plate of the prior art, reduced the electric field strength on MOS field effect tube surface; In addition, the present invention etches a plurality of shallow trenchs in first oxide layer, has disperseed the electric field on MOS field effect tube surface, has protected the gate oxide of MOS field effect tube, has improved the puncture voltage of MOS field effect tube.
Description of drawings
Fig. 1 is the structural representation of MOS field effect tube in the prior art;
Fig. 2 improves the structural representation of first embodiment of MOS field effect tube of the method for breakdown voltage of power MOS field effect transistor for the present invention;
Fig. 3 improves the flow chart of the method for breakdown voltage of power MOS field effect transistor for the present invention;
Fig. 4 improves the structural representation of second embodiment of MOS field effect tube of the method for breakdown voltage of power MOS field effect transistor for the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further explanation.
Since in the field plate of MOS field effect tube in the prior art, the angle that exists a polysilicon layer to form, and the existence of angle can attract more electric field to assemble; Increase the electric field strength of angle, it is breakdown to make that MOS field effect tube is prone to, in order to address this problem; The present invention proposes a kind of method that improves breakdown voltage of power MOS field effect transistor, please refer to Fig. 2, on scheming, can see; First oxide layer 12 is positioned at substrate 10 fully; 10, two polysilicon gates of substrate that two active areas 11 are positioned near first oxide layer, 12 both sides are formed on the substrate 10 and first oxide layer 12, and second oxide layer 15 is deposited on the polysilicon gate and first oxide layer 12; Field plate 16 is made on second oxide layer 15; Polysilicon gate is made up of with polysilicon layer 14 the 3rd oxide layer 13, and the 3rd oxide layer 13 is that gate oxide is positioned on the substrate 10 and first oxide layer 12, and polysilicon layer 14 is positioned on the 3rd oxide layer 13.This design designs first oxide layer 12 in the substrate 10 of MOS field effect tube; Thereby eliminated the formed angle of polysilicon in the field plate of the prior art; Also avoided simultaneously electric field, yet also there is another problem in a kind of like this design in the accumulation of angle place.The first oxide layer surface is being carried out in the process of lapping; The center of first oxide layer after existing grinding technique tends to cause grinding is a little less than two ends; Promptly can there be slight subsiding in the center of first oxide layer; This phenomenon still might cause electric field to be assembled at the center of first oxide layer, thereby produces stronger electric field in the first oxide layer center, destroys gate oxide easily.
In order to overcome above-mentioned shortcoming, the present invention improves on original basis, please refer to Fig. 3, and Fig. 3 improves the flow chart of the method for breakdown voltage of power MOS field effect transistor for the present invention, and concrete step is following:
Step 31: etching forms first shallow trench in the substrate of said MOS field effect tube; Said lithographic method is an anisotropic etching; Etching solution can be selected hydrofluoric acid, and purpose is the shallow trench that forms vertical sidewall, and sidewall and substrate surface are 88 degree usually; The etching depth scope is between 1 nanometer to 10 micron, specifically neglects actual conditions greatly and decides;
Step 32: deposit first oxide layer in said first shallow trench; And said first oxide layer carried out etching and grinding, and remove said first oxide layer on the said substrate, said first oxide layer is a silicon oxide layer; Grind and be cmp; After over etching and grinding, the surface of filling up the silicon oxide layer of shallow trench fully flushes at slot wedge and substrate surface, has avoided the appearance of the angle of subsequent deposition polysilicon layer; Electric field is not concentrated at the gate oxide annex, gate oxide is played a protective role;
Step 33: etching forms a plurality of second shallow trenchs in said first oxide layer, and etching is the anisotropic etching, and purpose also is the shallow trench that forms vertical sidewall; Usually sidewall and substrate surface are 88 degree; Etching only in first oxide layer, does not have influence to substrate, and a plurality of second shallow trenchs in etching first oxide layer later can disperse electric field; Thereby avoid electric field panel edges on the scene; Promptly assemble at the center of first oxide layer, preferred, and the degree of depth of said second shallow trench is the half the of the first shallow trench degree of depth;
Step 34: on said substrate and said first oxide layer, form two polysilicon gates, again with said polysilicon gate very the substrate surface of barrier layer in two said polysilicon gates outsides carry out ion and inject, form first active area and second active area;
Step 35: deposit second oxide layer on said polysilicon gate, second oxide layer is a silicon oxide layer also, plays the effect of isolating and protecting;
Step 36: on said second oxide layer, make field plate, the making of field plate also is existing common process, and purpose is in order to protect MOS field effect tube.
Said polysilicon gate is made up of the 3rd oxide layer and polysilicon layer; The 3rd oxide layer is a gate oxide, and said the 3rd oxide layer is a silicon oxide layer, and deposit the 3rd oxide layer and polysilicon layer adopt existing common process; Photoetching and etching are with the 3rd oxide layer and the polysilicon layer separated into two parts of deposit.
At last; Please refer to Fig. 4; Fig. 4 improves the structural representation of second embodiment of MOS field effect tube of the method for breakdown voltage of power MOS field effect transistor for the present invention, Fig. 4 be among Fig. 2 in first oxide layer sketch map behind a plurality of shallow trenchs of etching because Fig. 2 is symmetrical structure; Therefore only showed the sketch map of its left part here, right portions and left part are similar.On scheming, can see; First shallow trench that first oxide layer 12 is filled is positioned at substrate 10; Active area 11 is positioned at the substrate 10 of first oxide layer, 12 both sides, in first oxide layer 12, etches a plurality of second shallow trenchs, is five second shallow trenchs among the figure; Add five shallow trenchs of right side symmetry, totally ten shallow trenchs.The 3rd oxide layer 13 is that gate oxide is positioned on the substrate 10 and first oxide layer 12, and polysilicon layer 14 is positioned on the 3rd oxide layer 13.Second oxide layer 15 is formed on the polysilicon layer 14 with field plate 16 successively, and is identical with Fig. 2.In test process, the puncture voltage of the MOS field effect tube among Fig. 2 is 537V, and the puncture voltage of the MOS field effect tube among Fig. 4 is 596V, and puncture voltage is significantly improved.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field according to the invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (7)
1. a method that improves breakdown voltage of power MOS field effect transistor is characterized in that, may further comprise the steps:
Etching forms first shallow trench in the substrate of said MOS field effect tube;
Deposit first oxide layer in said first shallow trench; And said first oxide layer carried out etching and grinding; Wherein, Said first oxide layer is through over etching with after grinding, and the surface of said first oxide layer flushes at said first shallow trench edge and said substrate surface, removes said first oxide layer on the said substrate;
Etching forms a plurality of second shallow trenchs in said first oxide layer, and wherein to form the method for said first shallow trench and said second shallow trench be anisotropic etching to etching;
On said substrate and said first oxide layer, form two polysilicon gates, again with said polysilicon gate very the substrate surface of barrier layer in two said polysilicon gates outsides carry out ion and inject, form first active area and second active area;
Deposit second oxide layer on said polysilicon gate;
On said second oxide layer, make field plate.
2. the method for raising breakdown voltage of power MOS field effect transistor according to claim 1 is characterized in that said first oxide layer is a silicon oxide layer.
3. the method for raising breakdown voltage of power MOS field effect transistor according to claim 1 is characterized in that said second oxide layer is a silicon oxide layer.
4. the method for raising breakdown voltage of power MOS field effect transistor according to claim 1 is characterized in that said polysilicon gate is made up of the 3rd oxide layer and polysilicon layer.
5. the method for raising breakdown voltage of power MOS field effect transistor according to claim 4 is characterized in that said the 3rd oxide layer is a silicon oxide layer.
6. the method for raising breakdown voltage of power MOS field effect transistor according to claim 1 is characterized in that said grinding is a cmp.
7. the method for raising breakdown voltage of power MOS field effect transistor according to claim 1, the degree of depth that it is characterized in that said second shallow trench are the half the of the said first shallow trench degree of depth.
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| CN200910199438A CN101707183B (en) | 2009-11-26 | 2009-11-26 | Method for increasing breakdown voltage of power MOS field effect transistor |
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| CN101707183B true CN101707183B (en) | 2012-10-17 |
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| CN101777497A (en) * | 2010-01-12 | 2010-07-14 | 上海宏力半导体制造有限公司 | Production method of power MOS field-effect tube |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0849782A1 (en) * | 1996-12-20 | 1998-06-24 | Siemens Aktiengesellschaft | A mos transistor |
| CN1855395A (en) * | 2005-04-20 | 2006-11-01 | 恩益禧电子股份有限公司 | Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0849782A1 (en) * | 1996-12-20 | 1998-06-24 | Siemens Aktiengesellschaft | A mos transistor |
| CN1855395A (en) * | 2005-04-20 | 2006-11-01 | 恩益禧电子股份有限公司 | Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics |
Non-Patent Citations (1)
| Title |
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| JP特开2008-283112A 2008.11.20 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |