CN101702838A

CN101702838A - TD-SCDMA RRU multistage cascaded quick start device and method

Info

Publication number: CN101702838A
Application number: CN200910272469A
Authority: CN
Inventors: 邓标华; 李玮; 杜仲
Original assignee: Wuhan Hongxin Telecommunication Technologies Co Ltd
Current assignee: Wuhan Feng and Zhida information technology limited liability company
Priority date: 2009-10-20
Filing date: 2009-10-20
Publication date: 2010-05-05
Anticipated expiration: 2029-10-20
Also published as: CN101702838B

Abstract

The invention relates to TD-SCDMA RRU multistage cascaded quick start device and method. The device comprises two lasers, an FPGA module and a CPU module, wherein the FPGA module is respectively connected with the two lasers and the CPU module. The method realizes digital signal processing by utilizing a field programmable gate array, wherein a start-over marking signal generated by a central processing unit of a local RRU is used as a reference, and a next-stage RRU being subject to the local RRU is informed through extending an Ir interface protocol; the FPGA of the next-stage RRU extracts an SRF marking whether the local RRU finishes being started or not from the Ir interface; and then the CPU of a next-stage RRU is guided to finish remaining start processes so as to realize the multistage cascaded quick start of the RRUs. The invention has the characteristics of stability and high speed and is beneficial to engineering opening and maintenance.

Description

TD-SCDMA RRU multistage cascaded quick start device and method

Technical field

The present invention relates to a kind of TD-SCDMA RRU multistage cascaded quick start device and method.

Background technology

Remote radio unit (RRU) (RRU) is a part important in the 3G communication system, for being attached to a communication module of base station (NODE B).The remote radio unit (RRU) major function is to finish the blind area to cover, reduce base station number, this module can be delivered to the Base Band Unit (BBU) of the upper-level BTS that is depended on by optical fiber with data, the data of BBU or upper level RRU can also be transmitted to the next stage RRU of institute's subordinate by optical fiber.

Star-like, chain, multiple connected mode such as ring-like can be arranged between RRU and the BBU, satisfy the demand of network agile networking, scalable application scenario.For long narrow bottom lines such as railway, highway, coastlines, can pass through the cascade between RRU, and adopt directional antenna to cover, RRU cascade schematic diagram is as shown in Figure 1.Cascade between RRU is a kind of work in series mode, only after previous stage RRU startup is finished, RRU at the corresponding levels could normally start, the maximum cascade number that Ir (Interface between RRU and BBU) interface protocol requires RRU to support is not less than 6 grades, and single-stage RRU start-up time is the longest to be 5 minutes, therefore in RRU multi-stage cascade application scenario, will be a veryer long process start-up time of RRU.As in single antenna 9 carrier waves (AxC) RRU cascade effect is used, cascade number maximum under 2.4576Gbps optical fiber speed is 6 grades, general single-stage RRU is normal, and the time that starts is about 2 minutes, so all normal times that start of 6 grades of RRU minimum be 12 minutes, under the situation that common 6 grades of RRU start at the same time, always have what RRU and can enter improper startup flow process because of prime RRU is not activated to finish, can't connect as ICP/IP protocol with BBU, lose heartbeat etc. after the startup, thereby cause these RRU after waiting for the quite a while, to be restarted again, so repeatedly, all normal time that starts of final 6 grades of RRU may substantially exceed 12 minutes.This traditional startup method efficient is low, and the stability of a system is poor, is unfavorable for opening and safeguarding of engineering.

Summary of the invention

The objective of the invention is in order to overcome the defective that conventional method exists, provide a kind of stable, fast, the TD-SCDMA RRU multi-stage cascade starting drive and the method that help engineering opening and maintenance, this method is to be core with the Digital Signal Processing, this method utilizes field programmable gate array (FPGA) to realize Digital Signal Processing, wherein RRU startup the finishing marking signal at the corresponding levels that produces with central processing unit (CPU) is a benchmark, notify the next stage RRU of RRU at the corresponding levels institute subordinate by expansion Ir (Interface between RRU and BBU) interface protocol, the FPGA of next stage RRU extracts RRU at the corresponding levels from the Ir interface and whether starts the sign SRF (Start Ready Flag) that finishes, the CPU that reboots next stage RRU finishes remaining startup flow process, thereby realizes the quick startup of RRU multi-stage cascade.

TD-SCDMA RRU multistage cascaded quick start device of the present invention, be made up of following components: two lasers (0,1), FPGA module, CPU module, FPGA module link to each other with two lasers, CPU module respectively.The structure technology scheme of the inventive method institute operative installations is referring to Fig. 2.The function of each module is as follows in this device: laser 0 is used for the reception of down link data and the transmission of uplink data, to finish communicating by letter of RRU at the corresponding levels and upper level RRU or BBU; The FPGA module is used for extracting upper level RRU at down direction and whether starts the sign SRF signal that finishes, and this signal is issued the CPU module, SRF is inserted into after RRU at the corresponding levels finishes startup again and passes to laser 1 in the Ir radio frames, sends to next stage RRU; At up direction FPGA the realization of the inventive method is not processed; The CPU module is used for controlling from the SRF signal that first register of FPGA reads upper level RRU the startup flow process of RRU at the corresponding levels, if RRU at the corresponding levels is the first order, does not then need to judge the SRF signal and directly starts; Simultaneously, after RRU at the corresponding levels starts successfully, the SRF signal configures of RRU at the corresponding levels is given in second register of FPGA, be transmitted to next stage RRU for FPGA; Laser 1 is used for the transmission of down link data and the reception of uplink data, to finish communicating by letter of RRU at the corresponding levels and next stage RRU.

A kind of TD-SCDMA RRU multistage cascaded quick start method of the present invention may further comprise the steps:

(1) RRU electrifying startup at the corresponding levels, the CPU module is at first started working, and after all device initialization made up-downgoing physical link operate as normal in finishing RRU at the corresponding levels, CPU entered cyclic query SRF sign state;

(2) laser 0 is responsible for the reception of down link data and the transmission of uplink data, to finish communicating by letter of RRU at the corresponding levels and upper level RRU or BBU;

(3) conversion of high-speed-differential serial signal and parallel data is responsible for finishing in two of FPGA serial/parallel unit (SerDes), and finishes the 8B/10B encoding and decoding;

(4) the down physical layer processing module of FPGA is responsible for resolving the physical layer control word in the down link, therefrom extracts the SRF sign, sends to the CPU module;

(5) CPU reads the SRF sign from first register of FPGA and judges that if SRF is a logical zero, expression upper level RRU does not start yet and finishes, and continues to wait for; If SRF is a logical one, expression upper level RRU has normally started and has finished, and CPU enters maintenance management (OM) immediately and starts flow process, normally starts to finish RRU at the corresponding levels; Then do not need to judge the SRF sign if RRU at the corresponding levels is the first order, directly forward step (6) to;

(6) after the time delay configuration response flow process (IE931) of CPU in finishing RRU OM startup flow process at the corresponding levels, the SRF of RRU at the corresponding levels sign is set to write after 1 second register of FPGA again, if the IE931 flow process is not carried out, then the SRF of RRU at the corresponding levels sign is set to 0 always;

(7) the down physical layer processing module of FPGA is inserted in the Ir radio frames sign of the SRF in second register to be forwarded to next stage RRU;

(8) laser 1 is responsible for the transmission of down link data and the reception of uplink data, to finish communicating by letter of RRU at the corresponding levels and next stage RRU;

RRU at different levels execute above-mentioned steps (1) respectively to step (8), just can realize the RRU multistage cascaded quick start.

That the present invention has is stable, quick, help engineering opening and maintenance characteristics.

Description of drawings

Fig. 1 is a TD-SCDMA RRU multi-stage cascade schematic diagram in the 3G system.

Fig. 2 is the device block diagram of the RRU multistage cascaded quick start that the inventive method adopted.

Fig. 3 is the key step flow chart that the inventive method adopted.

5ms wireless frame structure schematic diagram when Fig. 4 is 2.4576Gbps for Ir interface rate in the 3G system.

Embodiment

The invention will be further described below in conjunction with accompanying drawing.

Shown in Figure 2, device of the present invention is made up of following components: two lasers (0,1), FPGA module, CPU module, FPGA module link to each other with two lasers, CPU module respectively.The function of each module is as follows in this device: laser 0 is used for the reception of down link data and the transmission of uplink data, to finish communicating by letter of RRU at the corresponding levels and upper level RRU or BBU; The FPGA module is used for extracting upper level RRU at down direction and whether starts the sign SRF signal that finishes, and this signal is issued the CPU module, SRF is inserted into after RRU at the corresponding levels finishes startup again and passes to laser 1 in the Ir radio frames, sends to next stage RRU; At up direction FPGA the realization of the inventive method is not processed; The CPU module is used for controlling from the SRF signal that first register of FPGA reads upper level RRU the startup flow process of RRU at the corresponding levels, if RRU at the corresponding levels is the first order, does not then need to judge the SRF signal and directly starts; Simultaneously, after RRU at the corresponding levels starts successfully, the SRF signal configures of RRU at the corresponding levels is given in second register of FPGA, be transmitted to next stage RRU for FPGA; Laser 1 is used for the transmission of down link data and the reception of uplink data, to finish communicating by letter of RRU at the corresponding levels and next stage RRU.FPGA need extract upper level RRU from the Ir radio frames the startup sign SRF that finishes, and the sign SRF that the startup of RRU at the corresponding levels need be finished is inserted in the Ir radio frames, because the Ir interface protocol does not define the SRF sign, therefore the inventive method is expanded the Ir interface protocol, increased the definition of SRF sign newly, utilize Ir interface protocol physical layer control word redundancy bytes transmission SRF sign, particular location is the lowest order (LSB0) of the 20th byte of first super first group organized in the Ir interface 5ms radio frames, as shown in Figure 4.Because the super group of first in the Ir interface protocol regulation 5ms radio frames is put the physical layer control word, and present defined physical layer control word has only 16, therefore also have 5919 bytes (also have 2 bytes to be used for transmitting the K28.5 sign and surpass group number) to use in the physical layer control word transmitting time of Ir radio frames, these bytes only need be chosen 1 bit wantonly and transmit the SRF sign and get final product.

In device shown in Figure 2, in order to reduce the total time that the RRU multi-stage cascade starts, the startup flow process of single-stage RRU is improved on the basis of compatible Ir agreement, concrete steps of the present invention specifically are that the startup with RRU is divided into two stages as shown in Figure 3, RRU at different levels previous stage executed in parallel simultaneously, the latter half serial is carried out, in order to reach quick startup purpose, should comprise more execution in step previous stage as far as possible, and then a stage should comprise execution in step still less as far as possible.The inventive method is chosen CPU after the initialization of finishing all devices, at the device id (ID) that obtains RRU at the corresponding levels from the down physical layer processing module before, as the stage separation, so promptly can allow long device initialization start-up time executed in parallel simultaneously, can avoid RRU at the corresponding levels to obtain again unsettled ID number or be connected to get nowhere causing restarting with BBU.Have only when CPU when this separation detects SRF that upper level RRU comes by physical layer link transmission and is masked as 1, CPU just enters maintenance management (OM) immediately and starts flow process, comprising the device id (ID) that obtains RRU at the corresponding levels from the down physical layer processing module, to BBU application IP address, passage foundation request etc., otherwise CPU will be in wait state always and be masked as 1 up to SRF.Then do not need to judge the SRF sign if RRU at the corresponding levels is the first order, the flow process of directly carrying out the back is to finish startup.

Enter the startup of second stage at RRU at the corresponding levels after, CPU sends the SRF sign need for next stage RRU, it is oversize that the transmitting time point of this sign promptly can not allow next stage RRU wait for, guarantee that again RRU at the corresponding levels has been in steady-working state, after the inventive method is chosen at RRU at the corresponding levels and executes the time delay configuration order, as the time point that sends SRF to next stage RRU.After RRU at the corresponding levels carries out the time delay configuration, though next also will carry out other OM flow processs such as cell configuration, but the wireless frame head of up-downgoing this moment is fixed up constantly, the physical layer link adjustment is finished, link is in stable state, the data that can reliable reception next stage RRU send up guarantee that important data can not be dropped, and next stage RRU can normally be started.

The down physical layer processing module of FPGA need be resolved the physical layer control word in the down link, and the SRF sign that therefrom extracts upper level RRU sends to the CPU module, and the SRF sign that also needs to receive the RRU at the corresponding levels that CPU sends simultaneously is to be transferred to next stage RRU.

Under the situation of multi-stage cascade, RRU at different levels work according to the method described above in order, just can realize quick startup.In the reality test, TD-SCDMA single antenna 9 carrier wave RRU are under the situation of 6 grades of cascades, and compared traditional startup method and reduced by an order of magnitude less than 3 minutes total start-up time.

The above embodiment of the present invention only is explanation method of the present invention, and protection range of the present invention is limited by claims.

Claims

1.TD-SCDMA the RRU multistage cascaded quick start device is made up of two lasers (0,1), FPGA module, CPU module, it is characterized in that: the FPGA module links to each other with two lasers, CPU module respectively; Laser (0) is used for the reception of down link data and the transmission of uplink data, to finish communicating by letter of RRU at the corresponding levels and upper level RRU or BBU; The FPGA module is used for extracting upper level RRU at down direction and whether starts sign SRF (the Start Ready Flag) signal that finishes, and this signal issued the CPU module, after RRU at the corresponding levels finishes startup, again SRF is inserted in Ir (the Interface between RRU and BBU) radio frames and passes to laser (1), send to next stage RRU; FPGA does not process at up direction; The CPU module is used for controlling from the SRF signal that first register of FPGA reads upper level RRU the startup flow process of RRU at the corresponding levels, if RRU at the corresponding levels is the first order, does not then need to judge the SRF signal and directly starts; Simultaneously, after RRU at the corresponding levels starts successfully, the SRF signal configures of RRU at the corresponding levels is given in second register of FPGA, be transmitted to next stage RRU for FPGA; Laser (1) is used for the transmission of down link data and the reception of uplink data, to finish communicating by letter of RRU at the corresponding levels and next stage RRU.

2.TD-SCDMA RRU multistage cascaded quick start method, step is as follows: utilize field programmable gate array (FPGA) to realize Digital Signal Processing, wherein RRU startup the finishing marking signal at the corresponding levels that produces with central processing unit (CPU) is a benchmark, notify the next stage RRU of RRU at the corresponding levels institute subordinate by expansion Ir (Interface between RRU and BBU) interface protocol, the FPGA of next stage RRU extracts RRU at the corresponding levels from the Ir interface and whether starts the sign SRF (Start Ready Flag) that finishes, the CPU that reboots next stage RRU finishes remaining startup flow process, thereby realizes the quick startup of RRU multi-stage cascade.

3. TD-SCDMA RRU multistage cascaded quick start method according to claim 2, concrete steps are as follows:

(2) laser (0) is responsible for the reception of down link data and the transmission of uplink data, to finish communicating by letter of RRU at the corresponding levels and upper level RRU or BBU;

(3) conversion of high-speed-differential serial signal and parallel data is responsible for finishing in two of FPGA serial/parallel unit, and finishes the 8B/10B encoding and decoding;

(8) laser (1) is responsible for the transmission of down link data and the reception of uplink data, to finish communicating by letter of RRU at the corresponding levels and next stage RRU;