CN101689396B - Concurrent multiple-dimension word-addressable - Google Patents
Concurrent multiple-dimension word-addressable Download PDFInfo
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- CN101689396B CN101689396B CN200880022161.3A CN200880022161A CN101689396B CN 101689396 B CN101689396 B CN 101689396B CN 200880022161 A CN200880022161 A CN 200880022161A CN 101689396 B CN101689396 B CN 101689396B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/276—Interleaving address generation
- H03M13/2764—Circuits therefore
Abstract
The present invention discloses a kind of N-dimensional addressable memory.Described memorizer comprises N-dimensional bit cell array and is configured to the logic using N-dimensional addressing (NDA) to address each unit, and wherein N is at least two, and institute's bit cell array can be addressed by N number of orthogonal address space.Each unit of described N-dimensional addressable memory comprises a position memory element, N number of wordline and N number of bit line.
Description
Technical field
Embodiments of the invention relate to memory architecture.More particularly, embodiments of the invention relate to the memory architecture being optimized for random matrix process capability.
Background technology
Random access memory (RAM) is the assembly generally existed of modern digital architectures.RAM can be self-contained unit or can integrated or be embedded in use RAM device in, such as, microprocessor, microcontroller, special IC (ASIC), system on chip (SoC) and other similar device as those skilled in the art will understand.
The custom integrated circuit memory architecture of such as single ported memory, dual-ported memory and Content Addressable Memory (CAM) only provides one-dimensional data word addressing space/tissue.For example, the explanation simple memory containing four words (0,1,2 or 3) that can address (i.e., only one-dimensional) linearly in Figure 1A.It is limited to read or write selected (through addressing) 4 words 110, as described via the memory access of custom integrated circuit memory architecture.If application requires the position 2 (such as, 120 in Figure 1B) of read/write word 0,1,2 and 3, then will need four store access cycles.For example, in conventional single ported memory, can read/write all 4 words, but each is by still in its corresponding line being read/writing.As those skilled in the art will understand, it would be desirable to operation bidirectional (such as, shift, shield, etc.) handle institute's rheme to obtain individual bit information.
Many performance application such as such as signal processing, Voice & Video coding/decoding etc. use the data being stored in the bit patterns being not limited to conventional word arrangements.Therefore, having a kind of memory architecture being optimized for random matrix operations will be useful.
Summary of the invention
The one exemplary embodiment of the present invention is for the memory architecture being optimized for random matrix operations.
Therefore, embodiments of the invention can comprise a kind of N-dimensional addressable memory, comprising: N-dimensional bit cell array；And it is configured to the logic using N-dimensional to address each unit, wherein N is at least two, and wherein bit cell array can be addressed by N number of orthogonal address space.
Another embodiment of the present invention can comprise a kind of bit location of N orthogonal dimension addressable memory, and institute's bitcell includes: position memory element；N number of wordline and N number of bit line, wherein N is at least two.
Another embodiment of the present invention can comprise a kind of method accessing memorizer, and described method includes: set up the first set of addressable words from N-dimensional bit cell array；And set up the second set of addressable words from N-dimensional bit cell array, wherein N is at least two, and the first set address space and the second set address space are orthogonal.
Accompanying drawing explanation
Present accompanying drawing with auxiliary describe embodiments of the invention, and only for explanation embodiment and non-limiting embodiments and accompanying drawing is provided.
Figure 1A is the block diagram of the memory array that conventional addressing operation is described.
Figure 1B is the block diagram of the memory array that wanted position to be read is described.
Fig. 2 is the block diagram of the memory architecture for vague generalization N-dimensional word addressable memory.
Fig. 3 is the circuit diagram of bit location based on N-dimensional addressing (NDA) static RAM (SRAM).
Fig. 4 A and Fig. 4 B explanation addressing 2 dimension word addressable (DWA) memorizer.
Fig. 5 illustrates 4 × 42 dimension word addressable (DWA) memorizeies.
Fig. 6 illustrates in M × 2 dimension word addressable (DWA) M × N × 2 memorizeies of N matrix ping-pong buffers configuration.
Detailed description of the invention
For the aspect disclosing the present invention in the description below of only certain embodiments of the present invention and correlative type.Alternate embodiment can be designed without departing from the scope of the invention.Maybe the well-known element of the present invention will be omitted, in order to do not make the correlative detail of the present invention obscure it addition, be not described in detail.
Word " exemplary " is in this article in order to represent " serving as example, example or explanation ".Any embodiment here depicted as " exemplary " is not necessarily to be construed as more preferred or favourable than other embodiments.Similarly, term " embodiments of the invention " does not require that all embodiments of the present invention all comprise discussed feature, advantage or operator scheme.
It addition, describe many embodiments according to the action sequence treating the element execution being calculated device by (such as).It will be recognized that particular electrical circuit (such as, special IC (ASIC)) can be passed through, perform various action described herein by the programmed instruction just performed by one or more processors or by a combination of both.Therefore, various aspects of the invention can embody in many different forms, has expected that all described forms are all in the range of the subject matter advocated.Additionally, for each in embodiment described herein, the corresponding form of this type of embodiment any all can be described herein as (such as) " being configured to " and perform " logic " of described action.
Fig. 2 explanation is according to the block diagram of the vague generalization N orthogonal dimension word-addressable memory 200 of at least one embodiment of the present invention.As used herein, N is the integer more than or equal to 2.N orthogonal dimension word-addressable memory contains memory bitcell array, and each in memory bitcell can address (NDA) scheme by N number of orthogonal addressing space or N-dimensional and address.Each in N number of dimension has data word input port (such as, 212), data word address port (such as, 214) and access control line (such as, 216).Each in N number of dimension also has the data word output port (such as, 222) of correspondence.In alternative embodiments, can in the shared input/output end port that can be used for data input and export with data both combination input port 212 and output port 222 functional.
Therefore, embodiments of the invention can comprise N-dimensional addressable memory 200, it has N-dimensional bit cell array 210 and is configured to the logic (such as, decoder 1 to N) using N-dimensional addressing (NDA) to address each unit, and wherein N is at least two.As discussed above, bit cell array 210 can be addressed by N number of orthogonal addressing space.The logic being configured to address each unit can include N number of address decoder (such as, 242).Each address decoder can be configured to receive data word address 214 and dimension access control signal 216.It addition, for each N-dimensional, word can be comprised and selects multiplexer (mux) (such as, 252), it can be with corresponding address decoder (such as, 242) collaborative work, to realize the random matrix addressing for random matrix read/write operations.It addition, memorizer can comprise the logic (such as, sense amplifier, line drive etc.) being configured to read/write for the data of each N-dimensional, its most visual particular memory type and comprised.
Fig. 3 explanation is according to the bit cell implementation scheme based on NDA SRAM of at least one embodiment of the present invention.Can be similar to conventional SRAM bit cell to arrange the NDA SRAM bit cell illustrated by Fig. 3, to form compact N-dimensional word addressable (N-DWA) SRAM.For example, 2 dimension arrays in the one exemplary embodiment of the present invention can occupy the equivalent area of conventional 2 port static random access memorys (SRAM).But, embodiments of the invention are not limited to any particular arrangement.
Therefore, embodiments of the invention can comprise the bit location 300 of N orthogonal dimension addressable memory.Institute's bitcell can comprise a position memory element 310, N number of wordline 320 and N number of bit line 330, and wherein N is at least two.Bit location can be a part of static RAM (SRAM), as discussed above.But, embodiments of the invention are not limited to any particular memory type.As described, each in bit line can comprise and is coupled to the First Line of memory element 310 (such as, 334) and be coupled to the second line of memory element (such as, 332), wherein as well-known in technique, when selecting word d1, place value is determined by the differential voltage between First Line 334 and the second line 332.Similarly, each in N number of wordline 320 is coupled to device (such as, transistor 322 and 324), described device is configured in the case of wordline is activated, the corresponding bit line (332 and 334) from N number of bit line is coupled to memory element 310.It is understood by those skilled in the art that, the wordline being associated by activation, any one in optional N number of bit line, and described bit line can be used to read or the value of writing memory element.Because need not bit location details of operation for understanding embodiments of the invention, and bit location details of operation is well known in the art, is discussed in detail so will not be provided herein.
N-dimensional word addressable (N-DWA) memorizer can have N number of simultaneous memory accesses passage, each of which person includes data word input port Din (i), data word address port Addr (i), data word output port Dout (i) and controls port Ctrl (i), the one during wherein i represents N number of orthogonal addressing space.The bit width of Din (i) or Dout (i) defines the bits number of every word, i.e. word address Addr (i) is addressed the number of the target NDA bit cells of (selection) every time.Ctrl (i) provides one or more control signals for selecting the one in the accessing operation (such as, word read operation or word write operation) supported.Embodiments of the invention are not intended to or force clear and definite N-dimensional addressing (NDA) scheme.For example, embodiments of the invention can comprise N-DWA memory construction, and it is configured for use in the application of the object-oriented matrix such as Table 1 below.
| Matrix Properties | N-DWA memory parameter |
| The number of dimension | N |
| The element number of every dimension often vector | Din (i) or Dout (i) bit width |
| Treat the matrix number simultaneously stored | Addr (i) bit width=log2(total institute's storage element/bit width (Din (i))) |
Table 1-Matrix Properties and N-DWA memory parameter
For example, if objective matrix is 2 × 4, and exist altogether 4 treat the matrix simultaneously stored, then 2-DWA memorizer can be used as described by Table 2 below.
Table 2-2 ties up word addressable (DWA) memorizer
Fig. 4 A and Fig. 4 B explanation is according to the addressing scheme for 2 dimension word addressable (DWA) memorizeies of at least one embodiment of the present invention.In Figure 4 A, address (1) (Addr (1)) is used to address 16 2 words.Each in described 2 words (such as, 0 to 15) represents 2 element row of target matrix data.In figure 4b, address (2) (Addr (2)) is used to address eight 4 words (such as, 0 to 7).Each in described 4 words represents 4 element row of target matrix data.Each in these examples hereafter be will be discussed in more detail.
Referring to Fig. 4 A, the configuration of 2 dimension word addressable (DWA) memorizeies is described for Addr (1).Memorizer can be by including that the Addr (1) of 16 2 words addresses, and each in described 16 2 words represents 2 element row of target matrix data as described.When being accessed by Addr (1), memory matrix 1 comprises word 0 to 3；Matrix 2 comprises word 4 to 7；Matrix 3 comprises word 8 to 11；And matrix 4 comprises word 12 to 15.Therefore, if will two positions in the second row of read/write matrix 4, then Addr (1) can be set to be worth 13, and single read/write operations can be performed, and exportable/2 words of storage.
Referring to Fig. 4 B, the configuration of 2 dimension word addressable (DWA) memorizeies is described for Addr (2).Described memorizer can be by including that the Addr (2) of eight 4 words (0 to 7) addresses, and each in described eight 4 words (0 to 7) represents 4 element row of target matrix data.When being accessed by Addr (2), memory matrix 1 comprises word 0 to 1；Matrix 2 comprises word 2 to 3；Matrix 3 comprises word 4 to 5；And matrix 4 comprises word 7 to 8.Therefore, if will four positions in the secondary series of read/write matrix 1, then Addr (2) can be set to be worth 1, and single read/write operations can be performed.For example, for read operation, 4 outputs of column data in matrix 1, row 1 can then be obtained in single operation.Similarly, for write operation, in single operation, 4 bit data can be stored matrix 1, row 1.
As discussed about Figure 1A and Figure 1B, if applying the position 2 (as indicated in Figure 1B) needing to use conventional single ported memory to read word 0,1,2 and 3 by with reference to 120, then four store access cycles of needs are read all four word by it.Then, it would be desirable to operation bidirectional individually extracts position 2 information.By contrast, the one exemplary embodiment of the present invention allows to access data in the single memory cycle.
For example, can create as indicated in Table 3 and Fig. 5 is illustrated and the 2 dimension word addressable memories that configure, to provide while target 4 × 4 matrix data and 4 row and column words accesses of monocycle.Described matrix class is similar to the matrix illustrated by Figure 1A and Figure 1B.
| 2-DWA memory parameter |
| N=2 |
| The position, bit width=4 Din (2) of Din (1) and Dout (1) and the position, bit width=4 of Dout (2) |
| Bit width=the log of Addr (1)2Bit width=the log of (4 × 4 × 1/4)=2 position Addr (2)2Position, (4 × 4 × 1/4)=2 |
Table 3-4 × 42 dimension word addressable (DWA) memorizer
By using 4 × 42 dimension word addressable (DWA) memorizeies as shown in Figure 5, string word read/write 520 (such as, Addr (2)=1) can be performed.Therefore, can arrange by reading/writing data in only one store access cycle.It addition, can it can be appreciated from the foregoing that, embodiments of the invention also addressable data 510, and data described in read/write, it is corresponding to conventional read/write operations (such as, 110 in Figure 1A).
The content of the foregoing description has been provided for some examples and the advantage of embodiments of the invention.Those skilled in the art will appreciate from the foregoing description that, embodiments of the invention are very suitable for matrix intensive applications.One example use of at least one embodiment of the present invention is digital communication.For example, N-DWA memorizer can be used for block alternation sum release of an interleave, and it is typical mission performed in the digital communication system of such as CDMA (CDMA), CDMA2000 and WCDMA system.For example, block interleaver can take advantage of the row of N row (M × N) array to accept symbol decoded in block by filling M row.Then, manipulator will can be fed to through staggered symbol the most by line.On the other hand, block deinterlacer performs reverse operating.Block alternation sum release of an interleave is well known in the art, therefore, further detail below (" Digital Communications-Fundamentals and application " (DigitalCommunications Fundamentals and Applications) see (such as) Bernardus carat (Bernard Sklar) be will not be provided herein, the second edition, page 464).
The process of block alternation sum release of an interleave may need to use many memorizeies and the logical operation of conventional system.But, embodiments of the invention permit direct matrix operation, and without additional logic operations.For example, referring to table 4, M × N2 can be created and tie up word addressable memory, while matrix data to be provided and monocycle M row and N row word access.
| 2-DWAM × N memory parameter | 2-DWA M × N × 2 memory parameter |
| N=2 | N=2 |
| Din (1) and the bit width=log of Dout (1)2(M) individual position Din (2) and the bit width=log of Dout (2)2(N) individual position | Din (1) and the bit width=log of Dout (1)2(M) individual position Din (2) and the bit width=log of Dout (2)2(N) individual position |
| Bit width=the log of Addr (1)2Bit width=the log of (N × 1) individual position Addr (2)2(M × 1) individual position | Bit width=the log of Addr (1)2Bit width=the log of (N × 2) individual position Addr (2)2(M × 2) individual position |
Word addressable (DWA) memorizer is tieed up in table 4-M × N × 22
Staggered and/or the de-interleaving example referring back to block, can use a 2-DWA memorizer being configured for use in M × N (such as, 4 × 6) matrix manipulation to carry out enforcement block in the case of without added logic and interlock or de-interleaving hardware design.Or, use a 2-DWA memorizer with the storage for 2 M × N matrix (as shown in the right row of table 4 and as depicted in fig.6) to may be used to form table tennis (ping-pong) buffer 600.2-DWA M × N × 2 memorizer may act as or the M × N matrix ping-pong buffers configuration 600 of release of an interleave staggered for block, to realize the throughput of one symbol high performance per memory cycle.Fig. 6 illustrates this example configured.For example, interleaver input sequence can directly fill table tennis buffer 610 with mode list entries by column (such as, (0,1,2,3) (4,5,6,7) ...).Interleaved output sequence (such as, (0,4,8,12,16,20) (1,5,9,13,17,21) ...) can be directly retrieved from pang buffer 620 on the basis of line by line.Therefore, interleaved output sequence can be produced in the case of without any added logic.The configuration being also based on memory array (such as, M × N) determines staggered.
De-interleaving operation can be realized by the similar configuration reciprocal with functional interleaving.For example, can line by line interleaved output sequence (such as, (0,4,8,12,16,20) (1,5,9,13,17,21) ...) be filled in reception memorizer.Data can be read by (such as, (0,1,2,3) (4,5,6,7) ...) by column and carry out direct release of an interleave interleaved output sequence to recover original input sequence.Therefore, also in the case of without any added logic, directly release of an interleave function can be realized from memorizer.
Although previous case emphasizes that embodiments of the invention perform the ability of matrix functions in digital communication systems, but embodiments of the invention are not limited to those application.For example, in encoding and decoding of video, can be the array in memorizer by object definition, and skimulated motion can be carried out by making described object column or row of mobile a certain number in described array.Embodiments of the invention allow the flexible addressing of memory array so that can improve object and move and process.Therefore, embodiments of the invention are not limited to examples and illustrations contained herein.
It addition, from foregoing teachings it is to be understood that the embodiments of the invention method that can comprise the sequence for performing action, algorithm, function and/or step discussed herein.For example, embodiment can comprise the method for access memorizer, and described method includes setting up the first set of addressable words from N-dimensional bit cell array, and sets up the second set of addressable words from N-dimensional bit cell array.As discussed above, N is at least two, and the first set of addressable words is orthogonal with the second set of addressable words.Described method can further include the element number (such as, being respectively 2 and 4 for Fig. 4 A and Fig. 4 B) that the bit width (i) being used for each set of addressable words is defined as every dimension often vector.Address bitwidth (i) can be defined as: Addr (i) bit width=log2(total institute's storage element/bit width (i)).For example, for Fig. 4 A and Fig. 4 B, respectively corresponding address bitwidth is defined as log2(32/2)=4 and log2(32/4)=3.In this example, the first set of addressable words has the bit width different from the bit width of the second set of addressable words.But, the first set of addressable words also can have the bit width (see (such as) Fig. 5) identical with the bit width of the second set of addressable words, is still orthogonal simultaneously.Embodiment can further include and list entries is written to the first set of addressable words, and reads output sequence from the second set of addressable words, and this can produce through staggered output.Further, list entries can be written to the first buffer (such as, ping buffer), and output sequence can be read from the second buffer (such as, pang buffer).
It is understood by those skilled in the art that, any one in multiple different technologies and skill and technique can be used to represent information and signal.For example, may the data of whole descriptions above reference in addition, instruct, order, information, signal, position, symbol and chip can be represented by voltage, electric current, electromagnetic wave, magnetic field or magnetic particle, light field or optical particle or its any combination.
Although the illustrative embodiment of the foregoing disclosure shows present invention, it should be noted that can make various changes and modifications in this article in the case of the scope of the present invention defined without departing from such as appended claims.Need not the function of claim to a method item, step and/or the action performed in any particular order according to embodiments of the invention described herein.Although additionally, the element of the present invention may be described or claimed in the singular, but being limited to singulative unless explicitly stated, otherwise expect plural form.
Claims (17)
1. a N-dimensional addressable memory, comprising:
N-dimensional bit cell array；
Being configured to the logic using N-dimensional to address each unit, wherein N is at least two, and wherein said
Bit cell array can be addressed by N number of orthogonal address space；And
The access path while of N number of, each of which access path comprises:
Data word input port；
Data word address port；
Data word output port；And
Controlling port, each of which access path is configured to access can from described each of N-dimensional bit cell array
Addressing word set, and each set of addressable words of wherein said set of addressable words is with other set of addressable words just
Hand over,
The orthogonal address space of each of which has bit width based on described data word input port or described data word is defeated
Go out the bit width of the bit width of port.
Memorizer the most according to claim 1, the wherein said logic being configured to address each unit is wrapped further
Include:
N number of address decoder；And
N number of word selects multiplexer.
Memorizer the most according to claim 2, each of which address decoder is configured to receive a data word address,
And an access control signal.
Memorizer the most according to claim 1, it farther includes:
It is configured to input the logic of the data for each N-dimensional degree；And
It is configured to export the logic of the data for each N-dimensional degree.
Memorizer the most according to claim 4, wherein said being configured to inputs patrolling of the data for each N-dimensional degree
Collect and comprise data word input port.
Memorizer the most according to claim 4, wherein said being configured to exports patrolling of the data for each N-dimensional degree
Collect and comprise sense amplifier.
Memorizer the most according to claim 1, the orthogonal address space of each of which has not bit widths.
Memorizer the most according to claim 1, each of which bit location includes:
One position memory element；
N number of wordline；And
N number of bit line, wherein N is at least two.
Memorizer the most according to claim 8, wherein said bit location be static RAM (SRAM) or
A part for dynamic random access memory (DRAM).
Memorizer the most according to claim 8, each in wherein said N number of bit line includes:
First Line, it is coupled to described memory element；And
Second line, it is coupled to described memory element, and its median is by the difference between described First Line and described second line
Value determines.
11. memorizeies according to claim 10, each in wherein said N number of wordline includes:
First Line, it is coupled to first device, and described first device is configured to the described First Line coupling of described bit line
Close described memory element；And
Second line, it is coupled to the second device, and described second device is configured to the described second line coupling of described bit line
Close described memory element.
12. memorizeies according to claim 8, each in wherein said N number of wordline is coupled to a device, described
Device is configured to when described wordline is activated to be coupled to described storage from the corresponding bit line of described N number of bit line
Element.
13. 1 kinds of methods accessing memorizer according to claim 1, comprising:
The bit width (i) being used for each set of addressable words (i) is defined as the element number of every dimension often vector；And
The address bitwidth being used for addressing each set of addressable words is defined as:
Addr (i) bit width=log2(total institute's storage element/bit width (i)).
14. methods according to claim 13, wherein the first set of addressable words has and the position of the second set of addressable words
The bit width that width is different.
15. methods according to claim 13, wherein the first set of addressable words has and the position of the second set of addressable words
The bit width that width is identical.
16. methods according to claim 13, it farther includes:
List entries is written to the first set of addressable words；And
Output sequence is read from the second set of addressable words.
17. methods according to claim 16, are wherein written to the first buffer by described list entries, and wherein from
Two buffers read output sequence.
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| US11/767,639 US8120989B2 (en) | 2007-06-25 | 2007-06-25 | Concurrent multiple-dimension word-addressable memory architecture |
| PCT/US2008/068388 WO2009003115A1 (en) | 2007-06-25 | 2008-06-26 | Concurrent multiple-dimension word-addressable memory architecture |
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| US8120989B2 (en) * | 2007-06-25 | 2012-02-21 | Qualcomm Incorporated | Concurrent multiple-dimension word-addressable memory architecture |
| US20110157194A1 (en) * | 2009-12-31 | 2011-06-30 | Omri Eisenbach | System, data structure, and method for processing multi-dimensional video data |
| WO2012059121A1 (en) | 2010-11-01 | 2012-05-10 | Telefonaktiebolaget L M Ericsson (Publ) | Memory arrangement for accessing matrices |
| US9361973B2 (en) | 2013-10-28 | 2016-06-07 | Cypress Semiconductor Corporation | Multi-channel, multi-bank memory with wide data input/output |
| US9083340B1 (en) * | 2014-05-15 | 2015-07-14 | Xilinx, Inc. | Memory matrix |
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| EP2165334A1 (en) | 2010-03-24 |
| EP2523352A1 (en) | 2012-11-14 |
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| US8120989B2 (en) | 2012-02-21 |
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| JP2010537351A (en) | 2010-12-02 |
| CN106294196B (en) | 2019-09-27 |
| WO2009003115A1 (en) | 2008-12-31 |
| TW200910375A (en) | 2009-03-01 |
| EP2165334B1 (en) | 2014-04-23 |
| US20080316835A1 (en) | 2008-12-25 |
| KR20100101558A (en) | 2010-09-17 |
| US8773944B2 (en) | 2014-07-08 |
| CN101689396A (en) | 2010-03-31 |
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