CN101685389B - Processor structure - Google Patents
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- CN101685389B CN101685389B CN200810216362A CN200810216362A CN101685389B CN 101685389 B CN101685389 B CN 101685389B CN 200810216362 A CN200810216362 A CN 200810216362A CN 200810216362 A CN200810216362 A CN 200810216362A CN 101685389 B CN101685389 B CN 101685389B
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- 238000003860 storage Methods 0.000 description 1
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Abstract
The invention discloses a processor structure which comprises an algorithm data control unit, a data channel and an operational unit, wherein the operational unit is used for executing operation on input data; and the algorithm data control unit executes a configuration instruction to configure the input or output data path of the data channel and/or the operation function of the operational unit. The invention is favorable to the expansion of the function and quantity of the operational unit, and is favorable to the cascade connection of a plurality of processors. Simultaneously, the invention has good algorithmic security.
Description
[technical field]
The present invention relates to the IC design field, be specifically related to the processor of a kind of configurable arithmetic unit and data path.
[background technology]
Along with integrated circuit fabrication process gets into the 90nm-45nm stage; ASIC (the Application Specific Integrated Circuit of complicated algorithm (like digital medium and radio communication algorithm etc.); Be special IC) realize; Face the design cycle long, design cost is high, very flexible, extendability are poor, is difficult to satisfy the demand that product goes on the market fast, function constantly promotes.Therefore, based on the storage instruction control mode, promptly processor is realized complicated algorithm, and it is more and more important just to seem.
Yet the method for designing of general processor and order set will be supported the realization of complicated algorithm; Order set and the order format and the implementation that must need relative complex; And be difficult for expansion, such as, when processor need be supported a kind of new calculation function or increase new arithmetic unit; Often need remodify the design of entire process device even revise whole order set, to support the realization of new function.Simultaneously, based on the algorithm design of general processor instruction system, the definite semantic of program code is plagiarized than being easier to, and is difficult to the intellecture property that guarantees that algorithm is realized.
[summary of the invention]
Fundamental purpose of the present invention solves the problems of the prior art exactly, and a kind of processor is provided, and helps expansion, has good algorithmic security.
For realizing above-mentioned purpose; The present invention provides a kind of processor; Comprise the algorithm data control assembly, be used to the data path of selecting data to import source and outgoing route, the arithmetic unit that is used for the input data are carried out arithmetic operation; Said algorithm data control assembly is carried out configuration-direct, and the calculation function that inputs or outputs data routing exclusive disjunction parts of data path is configured.
In one embodiment; Said data path comprises data input channel and output select unit; Said data input channel comprises data input alteration switch and configuration register, and said output select unit comprises data output change-over switch and output port conf register, and said arithmetic unit comprises ALU and configuration register; Said algorithm data control assembly writes configuration information the configuration register of appointment in the instruction according to configuration-direct.
Said algorithm data control assembly comprises load-on module and general-purpose register; Said load-on module is used for from outside port load instructions or data and deposits general-purpose register in, said configuration information be in the general-purpose register content, immediately the number or data-carrier store in content.
In another kind of embodiment; Said algorithm data control assembly also is used for when processor flows to row operation to data, carrying out pause instruction; Processor controls is in halted state, and said data path exclusive disjunction configuration of components information is remained unchanged, up to receiving recovering information.
Said recovering information is from carrying out information or the look-at-me that pause instruction picks up counting or counts completion.
The present invention also provides a kind of processor; Comprise the algorithm data control assembly, be used to the data path of selecting data to import source and outgoing route, the arithmetic unit that is used for the input data are carried out arithmetic operation; Said algorithm data control assembly is carried out configuration-direct; The calculation function that inputs or outputs data routing exclusive disjunction parts to the data path is configured, and said configuration-direct comprises operational code, configuration information and three operations of configuration purpose element.
In another embodiment; Said algorithm data control assembly also is used for when processor flows to row operation to data, carrying out pause instruction; Processor controls is in halted state; And said data path exclusive disjunction configuration of components information is remained unchanged, up to receiving recovering information, said pause instruction comprises operational code and two operations of time out count information element.
The invention has the beneficial effects as follows: the present invention adopts the configuration-direct of single kind to come the calculation function of selected data path of configuration data path and arithmetic unit, make arithmetic unit accomplish whole arithmetic operations, and instruction set is very simple; Do not need complicated decoding logic; Can simplify hardware configuration, can support the complex calculations function, when arithmetic unit increases the additional calculation function; Need not make amendment and increase configuration-direct; The semanteme that only need define newly-increased configuration information gets final product, thus help the expansion of arithmetic unit function and quantity, and help the cascade of a plurality of processors.Simultaneously; With of the prior art to have a semantic instruction of determinacy different; Comprise operational code, configuration information and three operations of configuration purpose element in the configuration-direct of the present invention, different configuration information source and different configuration purposes can produce different semantics; Different configurations is accomplished in instruction that maybe be same, so the present invention has good algorithmic security.
[description of drawings]
Fig. 1 is the hardware module block diagram of ADU in the processor in an embodiment of the present invention;
Fig. 2 is the configure hardware block diagram of an embodiment of the present invention.
[embodiment]
The application's characteristic and advantage will combine accompanying drawing to be elaborated through embodiment.
Embodiment one:
Comprise algorithm data control assembly (being called for short ADU, algorithm and data control unit) in the processor, be used to select the data path of data input source and outgoing route and be used for arithmetic unit (being called for short ALU) input data execution arithmetic operation.ADU is responsible for the data routing of configuration data path and the calculation function of ALU, and promptly to relevant algorithm application, ADU carries out the path configurations of data path and the calculation function configuration of ALU through carrying out configuration-direct.
Said data path comprises data input channel (being called for short Switch) and output select unit; Said data input channel comprises data input alteration switch and configuration register, and said output select unit comprises data output change-over switch and output port conf register.Said arithmetic unit ALU comprises ALU and configuration register; Said algorithm data control assembly ADU comprises load-on module and general-purpose register; Said load-on module is used for from outside port load instructions or data and deposits general-purpose register in; Algorithm data control assembly ADU writes configuration information the configuration register of appointment in the instruction according to configuration-direct.
Configuration-direct comprises operational code, configuration information and three operations of configuration purpose element, and form and bit wide are not limit, and said configuration information is the content of register of the interior perhaps input port of the interior several perhaps immediately or data-carrier store in the general-purpose register.For example:
Movesc?reg，configreg：
This instruction writes the configuration register of appointment with the data among the general-purpose register reg, and this configuration register is directly accomplished the path configurations of corresponding operation functions of components or data path.
As the mutation of such instruction, under the situation that the instruction bit wide allows, also can the general-purpose register reg in the above-mentioned instruction be changed into and count imm immediately, be i.e. Movesc imm, configreg.With the write direct configuration register of appointment of imm.
Count imm immediately and also can represent the address of data-carrier store, as configuration information, number can also be concrete operation or numerical value immediately with the data of the data-carrier store of corresponding address.
The configuration implication of data representative in the above-mentioned configuration register, i.e. the arithmetic operation of appointment or data routing can customize as required, thereby make illegal program code obtain the algorithm that taker can't be decoded actual execution.
Movesd?reg，datareg：
This instruction writes the data designated register with the data among the general-purpose register reg.
As the mutation of this instruction, the reg in this instruction can be the data-in port register of processor, and the value that is about to the data-in port register of processor writes the data designated register, and configuration-direct is: Input port, datareg.Equally, the data-out port register that the datareg in this instruction can finger processor, the value that is about to the general-purpose register of processor writes data designated output port register, and configuration-direct is: Output reg, port.
Be illustrated in figure 1 as a kind of concrete structure of algorithm data control assembly ADU; Said ADU is appreciated that to being a processor that has only several instructions that does not comprise arithmetic unit to have command memory, data-carrier store, general-purpose register, timing or modules such as counter, code translator naturally.Module 1 is programmable counter PC among the figure, is used for indicating the address of current working procedure; Module 2 and 3 is representative data storer DMEM and command memory IMEM respectively, is used for storing data and instruction respectively, can certainly adopt a memory stores data and instruction; Module 4 is decoding units, is used as the analysis instruction implication, the interpretive order behavior; Module 6 is a general purpose register set, is used to store data or instruction; Module 7 expression load-on modules.Load-on module 7 deposits data-carrier store DMEM or command memory IMEM in from the outside port loading data.When load-on module 7 load be data the time; Load-on module is loaded on data-carrier store dmem with data from input port; When load-on module 7 load be instruction the time; Carry module and will instruct and be loaded on command memory imem from input port, the address that provides through the pc module will be selected correspondence to instruct from command memory to operate.
Like a kind of concrete structure of processor that Fig. 2 thinks,, 2 ALU have only been drawn for ALU bunch among this figure for convenient explanation.ADU unit among the figure in the module 11 expression processors, a series of instructions among the present invention are responsible for carrying out in this unit; Module 12,13,17 is represented Switch, ALU bunch and output select unit respectively, and this three part is responsible for accomplishing operation of data and is handled; Module 14 and 15 is represented the input port and the output port of processor respectively, is responsible for the input and output of data.
In the present embodiment, said Switch comprises alteration switch and configuration register.Said arithmetic unit ALU family can comprise one or more ALU, and each ALU comprises ALU and configuration register, and wherein ALU includes but not limited to basic computing modules such as totalizer, multiplier, shift unit.Special, ALU can also comprise the arithmetic element of various special uses, like butterfly processing element, cordic unit etc.Output select unit comprises data output change-over switch and configuration register (being the output port register).18a, 18b, 18c represent the configuration register of Switch, ALU bunch and output select unit respectively among the figure, and the data register of module 19 representative data input channel Switch is ALU bunch and preserves service data.
Input end at data input channel Switch; The input Data Source has three: temporary data in the general-purpose register among the algorithm data control assembly ADU, from the data of input port input and the data of output select unit 17 outputs, data input channel Switch can select in three data sources according to configuration information.
Output select unit can pass through four path output datas; That is: data are outputed to output port, output to the input port of data input channel Switch and deposit the general-purpose register of ADU in; Data-carrier store, output select unit can be selected in four data outgoing routes according to configuration information.
Algorithm data control assembly ADU carries out configuration-direct, configuration information is write the configuration register of appointment in the instruction.Configuration information can be the content of general-purpose register/dmem or count immediately.The configuration register of appointment can be the configuration register of data input channel Switch in the instruction, also can be the configuration register of arithmetic unit ALU, can also be the configuration register of output select unit.
More than can know; Utilize this configuration-direct and hardware thereof to realize; Can change the annexation and the calculation function of its inner ALU easily; Realize the data path of processor and the configurability of function, be applicable to the situation that large-scale data stream is handled, particularly be directed against the array of digital signal processing.
When the present invention increases computing function at needs, need not make amendment and increase instruction, the semanteme that only need define newly-increased configuration information gets final product, and helps the expansion of functional processor and does not increase the complicacy of hardware designs.
The present invention only need can accomplish various complex calculations operations and algorithm mapping through the simple configuration instruction, and the instruction that each functional unit is carried out from the instruction design is basic identical, and can accomplish different operation through the difference of configuration information.For example same movesc instruction realizes according to the different functions that dispose different step of the configuration register of being write; Because ALU can design ALU voluntarily according to hardware designer, even it is just the same therefore to carry out the configuration information of configuration ALU instruction, the execution function of computing unit also can be according to the difference of ALU and difference.Therefore, the instruction among the present invention has encryption, and each system design manufacturer can be according to the semanteme of the configuration information of ALU among the self-defined array ALU of actual conditions bunch, thereby obtains self-defining order set, and can effectively protect independent intellectual property right.
Embodiment two,
Present embodiment is the further improvement on the foregoing description basis.
When carrying out Data Stream Processing, usually can run into an ALU and only need accomplish under the situation of a specific function computing, so often need to carry out circularly repeatedly one section specific program.Present embodiment repeats for fear of program, has defined the pause instruction that processor controls is suspended, and said pause instruction comprises operational code and two operations of time out count information element, and its a kind of form is:
Rouser?#imm；
ADU carries out pause instruction when processor flows to row operation to data; Processor controls is in halted state; Start timer timing or rolling counters forward; Make processor be in halted state simultaneously, said data path exclusive disjunction configuration of components information is remained unchanged, up to receiving recovering information.When timing or counting completion, processor recovers normal operating condition.
This instruction also can be written as the form of rouser reg, and at this moment the value among the reg replaces imm.
Pause instruction can also be following form:
HLT；
This instruction is as the special shape of rouser instruction, promptly carries out should instruction the time as ADU, with the work of time-out processor, up to being waken up by other signals (like look-at-me etc.).
For example, when data streams, suppose that computing last time of arithmetic unit is additive operation; After carrying out pause instruction, arithmetic unit will keep the additive operation function, and the data of input are done additive operation; Recover normal operating condition up to processor, arithmetic unit is configured to new calculation function.
Instruction of the present invention and hardware configuration help the Data Stream Processing among the array ALU.Thereby each processing unit in the array ALU structure all can be accomplished corresponding configuration through this configuration-direct and realize different computing functions; When carrying out the large scale digital signal Processing; Data flow to from the input port of array ALU; Accomplish the corresponding operation operation by way of each processing unit, can accomplish the algorithm mapping of complicated digital signal processing, and not need each processing unit to execute instruction continually; Only need when initialization, to accomplish each computing unit function and data routing configuration, or in the minority processing unit course of work, carry out the modification of corresponding operation function and data routing.
Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (8)
1. processor; Comprise the algorithm data control assembly, be used to the data path of selecting data to import source and outgoing route, the arithmetic unit that is used for the input data are carried out arithmetic operation; It is characterized in that: said algorithm data control assembly is carried out configuration-direct, and the calculation function that inputs or outputs data routing exclusive disjunction parts of data path is configured;
Said data path comprises data input channel and output select unit; Said data input channel comprises data input alteration switch and configuration register; Said output select unit comprises data output change-over switch and output port conf register; Said arithmetic unit comprises ALU and configuration register, and said algorithm data control assembly writes configuration information the configuration register of appointment in the instruction according to configuration-direct.
2. processor as claimed in claim 1; It is characterized in that: said algorithm data control assembly comprises load-on module and general-purpose register; Said load-on module is used for from outside port load instructions or data and deposits general-purpose register in, said configuration information be in the general-purpose register content, immediately the number or data-carrier store in content.
3. processor as claimed in claim 1 is characterized in that: said processor also comprises the input port register, and said configuration information is the content in the input port register.
4. processor as claimed in claim 1; It is characterized in that: said algorithm data control assembly also is used for when processor flows to row operation to data, carrying out pause instruction; Processor controls is in halted state; And said data path exclusive disjunction configuration of components information is remained unchanged, up to receiving recovering information.
5. processor as claimed in claim 4 is characterized in that: said recovering information is from carrying out information or the look-at-me that pause instruction picks up counting or counts completion.
6. processor; Comprise the algorithm data control assembly, be used to the data path of selecting data to import source and outgoing route, the arithmetic unit that is used for the input data are carried out arithmetic operation; It is characterized in that: said algorithm data control assembly is carried out configuration-direct; The calculation function that inputs or outputs data routing exclusive disjunction parts to the data path is configured, and said configuration-direct comprises operational code, configuration information and three operations of configuration purpose element;
Said data path comprises data input channel and output select unit; Said data input channel comprises data input alteration switch and configuration register; Said output select unit comprises data output change-over switch and output port conf register; Said arithmetic unit comprises ALU and configuration register; Said algorithm data control assembly comprises load-on module and general-purpose register; Said load-on module is used for from outside port load instructions or data and deposits general-purpose register in, and said configuration information comprises content in the general-purpose register, the content of the register of the interior perhaps input port of number or data-carrier store immediately, and said configuration purpose is the configuration register of data input channel, the output port conf register exclusive disjunction configuration of components register of output select unit.
7. processor as claimed in claim 6; It is characterized in that: said algorithm data control assembly also is used for when processor flows to row operation to data, carrying out pause instruction; Processor controls is in halted state; And said data path exclusive disjunction configuration of components information is remained unchanged, up to receiving recovering information.
8. processor as claimed in claim 7 is characterized in that: said pause instruction comprises operational code and two operations of time out count information element.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810216362A CN101685389B (en) | 2008-09-28 | 2008-09-28 | Processor structure |
| US13/121,406 US20110271078A1 (en) | 2008-09-28 | 2008-12-15 | Processor structure of integrated circuit |
| PCT/CN2008/073514 WO2010034167A1 (en) | 2008-09-28 | 2008-12-15 | Processor structure of integrated circuit |
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| CN200810216362A CN101685389B (en) | 2008-09-28 | 2008-09-28 | Processor structure |
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| CN101685389B true CN101685389B (en) | 2012-10-24 |
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| CN102681970B (en) * | 2012-04-25 | 2015-01-07 | 华为技术有限公司 | Signal processor and configuration method thereof |
| CN107193755A (en) * | 2017-06-29 | 2017-09-22 | 合肥工业大学 | A kind of MMU memory management unit and its working method suitable for general floating point processor |
| CN112559442A (en) * | 2020-12-11 | 2021-03-26 | 清华大学无锡应用技术研究院 | Array digital signal processing system based on software defined hardware |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1321276A (en) * | 1998-09-23 | 2001-11-07 | 因芬尼昂技术股份公司 | Configurable hardware block |
| CN101133409A (en) * | 2005-03-03 | 2008-02-27 | Clear-Speed科技公司 | Reconfigurable logic in processors |
| CN101136070A (en) * | 2007-10-18 | 2008-03-05 | 复旦大学 | Multiple protocol radio frequency label read-write machine baseband processor based on reconstruction structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1321276A (en) * | 1998-09-23 | 2001-11-07 | 因芬尼昂技术股份公司 | Configurable hardware block |
| CN101133409A (en) * | 2005-03-03 | 2008-02-27 | Clear-Speed科技公司 | Reconfigurable logic in processors |
| CN101136070A (en) * | 2007-10-18 | 2008-03-05 | 复旦大学 | Multiple protocol radio frequency label read-write machine baseband processor based on reconstruction structure |
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