CN101674092B - Deinterleaver supporting seamless change of data frame length and method thereof - Google Patents

Abstract

The invention relates to the field of digital communication, in particular to a deinterleaver supporting the seamless change of data frame length and a method thereof. The deinterleaver is realized by the following steps: converting deinterleave with variable width to deinterleave with fixed width J but variable depth Krg(i), causing all pairs of circuit branches with the same modulo value J and the same delay to be equivalent to a circuit branch with the delay K times that of the circuit branches, and writing and reading address in a memory. On the basis of supporting the seamless change of data frame length, the deinterleave method greatly saves hardware resources. The deinterleaver can be widely applied to European digital audio broadcasting standard DAB, Korean terrestrial digital multimedia broadcasting standard T-DMB and other time deinterleave systems.

Description

A kind of deinterleaver and method thereof of supporting the seamless variation of data frame length

Technical field

The present invention relates to digital communication system, relate in particular to deinterleaver and de-interweaving method.

Background technology

In digital communication system, in order to make continuous wrong discretization, strengthen the chnnel coding error correcting capability, can use data interleaver usually.In european digital audio broadcast standards DAB, the transmission data of all subchannels all need be carried out time-interleaved in the regulation MSC (MSC).Yet in case multiplexingly reshuffle generation, data frame length just changes possibly in the subchannel.

Suppose that r frame data frame length is M _r, the input r frame data that interweave do $B_r=(b_{r,0},b_{r,1},\·\·\·,b_{r,M_r-1}),$ Output r frame data then interweave $C_r=(c_{r,0},c_{r,1},\·\·\·,c_{r,N_r-1})$ For

$c_{r,i}=\left\{\begin{array}{cc}{b}_{r-f\left(i\right),i}& 0\≤i\≤M_{r-f\left(i\right)}-1\\ 0,& M_{r-f\left(i\right)}\≤i\≤N_r-1\end{array}\right.$

Wherein, the relation between f (i) and the i is as shown in Figure 5, and Fig. 5 multiplexingly concerns sketch map, N between f (i) and the i during to reshuffle that a situation arises time-interleaved _rBe the output r frame data C that interweaves _rLength.

Under the constant situation of multiplexing configuration, N _rInput r frame data B equals to interweave _rLength M _r, i.e. N _r=M _rYet after multiplexing reconfiguration events took place, in 15 frame data of input continuously, the dateout that interweaves frame length was long greater than the input data frame that interweaves probably, i.e. N _r＞M _r

Concrete N _rWith M _rBetween relation can be expressed as:

(1) if M _rConstant in 16 frames, i.e. M _r=M _R-1=...=M _R-15, N then _r=M _r

(2) if M _rIn 16 frames, increase, i.e. M _r＞M _R-15, N then _r=M _r

(3) if M _rIn 16 frames, reduce, i.e. M _r＜M _R-15, N then _r=M _R-15

More than (1), (2), (3) can be reduced to formula N _r=max (M _r, M _R-15).

Fig. 1 is the elongated time-interleaved sketch map of DAB sub-channels Frame.Fig. 2 is the time-interleaved sketch map that DAB sub-channels Frame shortens.Fig. 1 and Fig. 2 have provided the time-interleaved example that DAB sub-channels Frame is elongated and shorten respectively.Interleaver has inserted padding data 0 in multiplexing 15 frame data of reshuffling generation, when deinterleaving, then need carry out special processing to realize the seamless connection of valid data to these 15 frame data.The tradition de-interweaving method can be through therefrom selecting suitable data as output behind 15 Frames of buffer memory again; If each data-measuring is 4 bits; Needing memory size when then supporting eldest son's channel in the conventional method is 55296 * 15 * 4=3317760 bit, and so large-scale memory will certainly increase chip cost greatly.

Denomination of invention is a time de-interweaving method, and publication number is the Chinese patent of CN101242190A, has proposed the time de-interweaving method of a kind of T-DMB of being applicable to, and this method can be saved half for conventional method with memory size.But this patented method only is suitable for the constant time de-interweaving of data frame length, but can't solve the problem that data frame length changes.Therefore in present de-interweaving method, how to realize supporting on the littler cost basis that the seamless variation of data frame length is a major issue that needs solution.

Summary of the invention

The invention provides a kind of deinterleaver and method thereof of supporting the seamless variation of data frame length that can overcome the above problems.

In first aspect, the invention provides a kind of deinterleaver, this deinterleaver is used for the input data b _{R, i}Deinterleaving becomes dateout c _{R, i}, and satisfy c _{R, i}=b _{Ri-g (i), i}(0≤i≤M _r-1), wherein deinterleaving postpones g (i) and satisfies g (i)=g (mod (i, J)), (i J) asks modular arithmetic for i to J to mod, and b _{R, i}And c _{R, i}Frame length is respectively M _rAnd N _r, and M _r=min (N _r, N _R-D), $D=\underset{0\≤i\≤J-1}{\mathrm{Max}}f\left(i\right),$ N _r=K _rJ, wherein N _r, K _rBe variable, J is a constant.

This deinterleaver comprises delayer, comparator, frame counter and reads address-generation unit.This delayer is used for variable K _rThereby postpone the D frame and obtain K _R-DThis comparator is used to receive variable K _rAnd K _R-D, and compare K _rWith K _R-DSize.This frame counter is used to receive K _rWith K _R-The comparative result of D, and according to this comparative result the deinterleaving input data frame is grown variation back D frame data and count.This is read address-generation unit and is used to receive write address, K _rValue, K _R-DValue, K _rWith K _R-DComparative result and frame count value information, and read address A according to the information generating that this receives _{N+1, r}, this reads address A _{N+1, r}Be A _{N+1, r}=(A _{N+1, w}-(K _Max-K _R-D) g (n)+(K _r-K _R-D) min (t, g (n))) modN _AWherein, A _{N+1, r}Be that the n+1 branch road is read the address, A _{N+1, w}Be n+1 branch road write address, K _MaxBe the maximum frame length that interleaver is supported, N _ABe the required memory address number of memory, t is a frame count value.

In second aspect, the invention provides a kind of de-interweaving method, this de-interweaving method is used for the input data b _{R, i}Deinterleaving becomes dateout c _{R, i}, and satisfy c _{R, i}=b _{R-g (i), i}(0≤i≤M _r-1), wherein deinterleaving postpones g (i) and satisfies g (i)=g (mod (i, J)), (i J) asks modular arithmetic for i to J to mod, and b _{R, i}, c _{R, i}Frame length is respectively M _rAnd N _r, and M _r=min (N _r, N _r-D), $D=\underset{0\≤i\≤J-1}{\mathrm{Max}}f\left(i\right),$ N _r=K _rJ, wherein N _r, K _rBe variable, J is a constant.

This de-interweaving method comprises said width N _rIt is J and degree of depth K that variable deinterleaving is converted into fixed width _rThe variable deinterleaving of g (i), and ask the mould value identical and postpone identical branch road equivalence and be one and have K to J all _rThe branch road that doubly should postpone, and through write address in memory and read the address and realize.This reads address A _{N+1, r}Be A _{N+1, r}=(A _{N+1, w}-(K _Max-K _R-D) g (n)+(K _r-K _R-D) min (t, g (n))) modN _AWherein, A _{N+1, w}Be n+1 branch road write address, K _MaxBe the maximum frame length that interleaver is supported, N _ABe the required memory address number of memory, t is a frame count value.

In one embodiment of the invention, deinterleaver comprises that data counter and read-write enable generation unit.This data counter be one with N _rBe the counter in cycle, it is used for enabling generation unit to said read-write and sends count value s, and this count value s from 0 to N _r-1.This read-write enables generation unit and reads to enable useful signal or write to enable useful signal to the memory transmission according to the count value s from this data counter.

In another embodiment of the present invention, this deinterleaver comprises branch road counter and write address generation unit.The cycle counter that this branch road counter is a mould J and its count value be from 0 to J-1, and it is used for each branch road sequence number is counted judging branch road under the input data, and should be sent to the write address generation unit by affiliated branch road.This write address generation unit produces write address based on this count value, and this write address is sent to reads address-generation unit.

The present invention produces the deinterleaving read/write address through the branch road counter, and in 15 frames that data frame length changes, the said address of reading is revised, and the valid data that deinterleaving is exported can seamless connection.De-interweaving method of the present invention has been practiced thrift hardware resource greatly on the basis of supporting the seamless variation of data frame length.

Description of drawings

Below with reference to accompanying drawings specific embodiments of the present invention is explained in more detail, in the accompanying drawings:

Fig. 1 is the elongated time-interleaved sketch map of DAB sub-channels Frame;

Fig. 2 is the time-interleaved sketch map that DAB sub-channels Frame shortens;

Fig. 3 is that the convolution de-interleaving equivalence transforms sketch map;

Fig. 4 is the deinterleaver hardware systems block diagram of present embodiment;

Fig. 5 multiplexingly concerns sketch map between f (i) and the i during to reshuffle that a situation arises time-interleaved.

Embodiment

Suppose that deinterleaving imports the r frame data $C_r=(c_{r,0},c_{r,1},\·\·\·,c_{r,N_r-1})$ Frame length be N _r, the r frame data are exported in deinterleaving $B_r=(b_{r,0},b_{r,1},\·\·\·,b_{r,M_r-1})$ Frame length be M _r=min (N _r, N _R-D), and

b _r，i＝c _r-g(i)，i，0≤i≤M _r-1

Wherein, function g (i) satisfy g (i)=g (mod (i, J))=D-f (i), and $D=\underset{0\≤i\≤J-1}{\mathrm{Max}}f\left(i\right);$ (mod (i, J)) shows that many branch roads have same delay to g (i)=g, and (i J) asks modular arithmetic for i to J to mod; G (i) postpones for deinterleaving, the interweave delay of f (i) for postponing with respect to this deinterleaving; And satisfy N _r=K _rJ, N _r, K _rBe variable, J is a constant.

The above deinterleaving is that variable-width (is N _rVariable) convolution de-interleaving.De-interweaving method of the present invention is with this width N _rIt is J and degree of depth K that variable deinterleaving is converted into fixed width _rThe deinterleaving form that g (i) is variable.

Fig. 3 is that the deinterleaving equivalence transforms sketch map.Be N with width among Fig. 3 _rPostponing for the deinterleaving of g (i) is converted into width is that J postpones to be K _rThe deinterleaving of g (i), and ask the mould value identical and postpone identical branch road equivalence and be one and have K to J all _rThe branch road that doubly should postpone.What Fig. 3 described is that r frame data deinterleaving equivalence transforms sketch map, for a certain frame data, N _rBe worth the identical K that then transforms every the branch road in back _rBe worth also identical, only when certain frame data width changes with respect to the former frame data width, K _rValue just can change.

Therefore at deinterleaving width N _rK when not changing as yet _rConstant, however in case N _rChange, in the D frame that change to take place, the present invention adopts padding data 0 is removed and only exports the valid data method, thereby and realizes this and only export the de-interweaving method of valid data through the deinterleaving memory read/write is controlled.

Fig. 4 is the deinterleaver hardware systems block diagram of present embodiment.This deinterleaver comprises that data counter 410, read-write enable generation unit 420, branch road counter 430, write address generation unit 440, read address-generation unit 450, delayer 460, comparator 470, frame counter 480 and memory 490.

Data counter 410 be one with the long N of deinterleaving input data frame _rBe the counter in cycle, and output count value s from 0 to N _r-1.

Read-write enables generation unit 420 produces memory 490 according to the count value s of data counter 410 enable signal.As s＜N _rThe time, read-write enables generation unit 420 and produces one to memory 490 and write and enable useful signal; As s＜M _r=min (N _r, N _R-D) time, read-write enables generation unit 420 and reads to enable useful signal to memory 490 one of generation.It is thus clear that, for a certain frame data, read enable signal and possibly be less than and write enable signal, because in the deinterleaving process, need to remove the invalid data 0 that interleaving process is filled, sense data possibly is less than write data to realize the seamless link of valid data.

Memory 490 is used for the buffer memory deinterleaved data.It is that the memory address space of each branch road input data in memory 490 is unfixing that present embodiment adopts the whole circular displacement method, but in the whole circular displacement, the data of every branch road are all read according to the read signal of next branch road.This method need increase the memory space of 1 data so that realize the whole circular displacement.Suppose that the deinterleaving input data frame covers with sufficient N _Max=K _MaxJ then needs storage address to count N altogether _AFor

$N_A=K_{\max }\underset{i=0}{\overset{J-1}{\mathrm{\Σ}}}g\left(i\right)+1---\left(1\right)$

With the time-interleaved of DAB standard is example, gets maximum data frame length 55296, and the quantizing bit number of tentation data is 4, because N _Max=K _MaxJ and J=16, then K _Max=N _Max/ J=55296/16, simultaneously because $\underset{i=0}{\overset{J-1}{\mathrm{\Σ}}}f\left(i\right)=\underset{i=0}{\overset{J-1}{\mathrm{\Σ}}}i,$ Then required memory size does $N_A=(\frac{55296}{16}\underset{i=0}{\overset{15}{\mathrm{\Σ}}}i+1)\×4=1658884$ Bit is about the half the of required 3317760 bits of conventional method, has therefore reduced the realization cost greatly.

Branch road counter 430 be its count value of mould J cycle counter from 0 to J-1; This branch road counter 430 is used for each branch road sequence number is counted with branch road under the judgement input data; And should be sent to write address generation unit 440 by affiliated branch road, branch road is a branch road under the convolution de-interleaving after transforming under this.

Write address generation unit 440 produces write address according to the count value of branch road counter 430, and this write address is sent to reads address-generation unit 450 and memory 490.

Particularly, suppose that n data of r frame belong to mod (n, J) (0≤n≤N _r-1) branch road, its write address are A _{N, w}, then n+1 data belong to mod (its write address do for n+1, J) branch road

A _n+1，w＝(A _n，w+K _maxg(n))modN _A

(2)

Delayer 460 is used for the long N of deinterleaving input data frame _r=K _rVariable K among the J _rPostpone the D frame and obtain K _R-D, and with this K _R-DBe sent to and read address-generation unit 450 and comparator 470.

Comparator 470 receives K _rValue reaches the K from delayer 460 _R-DValue, and compare K _rAnd K _R-DSize exports this comparative result to and reads address-generation unit 450 and frame counter 480, with control frame counter 480 and read address-generation unit 450.

Frame counter 480 receives from 470 couples of K of comparator _rAnd K _R-DComparative result, and the D frame data that the deinterleaving input data frame is long after changing are counted according to this comparative result.

Particularly, work as K _r=K _R-DThe time, promptly when deinterleaving input data frame length was constant, frame counter 480 was in reset mode, and frame count value t is 0; Work as K _r≠ K _R-DThe time, promptly when deinterleaving input data frame long hair was given birth to change, this moment, frame counter 480 was in count status, and frame count value t counts from 0 to D-1.

Read address-generation unit 450 and receive write address A _{N+1, w}, K _r, K _R-DValue, K _rAnd K _R-DComparative result and frame count value t information, and according to the corresponding address of reading of this information generating that receives.

K when deinterleaving input data frame length remains unchanged _r=K _R-DThe time, establish the long N of actual deinterleaving input data frame _r=K _rJ, the then basic address table of reading is shown

A _n+1，r＝(A _n+1，w-(K _max-K _r)g(n))modN _A (3)

Taking place after multiplexing the reshuffling is K _r≠ K _R-DThe time, then need revise the address of reading basically in the formula (3).According to K _r, K _R-DAnd t, obtain the revised address of reading and be difference:

(1) the deinterleaving input data frame is elongated, i.e. K _r＞K _R-DThe time

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)+|K _r-K _r-D|·min(t，g(n)))modN _A

(2) the deinterleaving input data frame shortens, i.e. K _r＜K _R-DThe time

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)-|K _r-K _r-D|·min(t，g(n)))modN _A

(3) the deinterleaving input data frame is long constant, i.e. K _r=K _R-DThe time

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n))modN _A

Comprehensively (1), (2), (3) three kinds of situation are read address-generation unit and are output as

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)+(K _r-K _r-D)·min(t，g(n)))modN _A (4)

Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited described claims.

Claims (6)

1. a deinterleaver is used for the input data b _{R, i}Deinterleaving becomes dateout c _{R, i}, and satisfy c _{R, i}=b _{R-g (i), i}(0≤i≤M _r-1), wherein deinterleaving postpones g (i) and satisfies g (i)=g (mod (i, J)), (i J) asks modular arithmetic for i to J to mod, and b _{R, i}And c _{R, i}Frame length is respectively M _rAnd N _r, and M _r=min (N _r, N _R-D),

N _r=K _rJ, wherein N _r, K _rBe variable, J is a constant, it is characterized in that, comprise,

Delayer is with said variable K _rThereby postpone the D frame and obtain K _R-D

Comparator receives said variable K _rAnd K _R-D, and compare K _rWith K _R-DSize;

Frame counter receives said K _rWith K _R-DComparative result, and the long back D frame data that change of deinterleaving input data frame are counted according to this comparative result;

Read address-generation unit, receive write address, said K _r, K _R-DValue, said K _rWith K _R-DComparative result and said frame count value information, and read address A according to the information generating that this receives _{N+1, r}

This write address does,

A _n+1，w＝(A _n，w+K _maxg(n))?mod?N _A；

At K _r＞K _R-DThe time,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)+|K _r-K _r-D|·min(t，g(n)))mod?N _A；

At K _r＜K _R-DThe time,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)-|K _r-K _r-D|·min(t，g(n)))mod?N _A；

At K _r=K _R-DThe time,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n))mod?N _A；

This reads address A _{N+1, r}For,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)+(K _r-K _r-D)·min(t，g(n)))mod?N _A

Wherein, A _{N+1, r}Be that the n+1 branch road is read the address, A _{N+1, w}Be n+1 branch road write address, K _MaxBe the maximum frame length that interleaver is supported, N _ABe the required memory address number of memory, t is a frame count value.

2. a kind of deinterleaver as claimed in claim 1 is characterized in that, comprises that data counter, read-write enable generation unit;

Said data counter be one with N _rBe the counter in cycle, this data counter is used for enabling generation unit to said read-write and sends count value s, and this count value s from 0 to N _r-1;

Said read-write enables generation unit and reads to enable useful signal or write to enable useful signal to the memory transmission according to the count value s from this data counter.

3. a kind of deinterleaver as claimed in claim 2 is characterized in that, at s＜N _rThe time, read-write enables generation unit and produces to write and enable useful signal; At s＜M _r=min (N _r, N _R-D) time, read-write enables the generation unit generation and reads to enable useful signal.

4. a kind of deinterleaver as claimed in claim 1 is characterized in that, comprises branch road counter, write address generation unit;

The cycle counter that said branch road counter is a mould J and its count value be from 0 to J-1, and this branch road counter is used for each branch road sequence number is counted judging branch road under the input data, and should be sent to the write address generation unit by affiliated branch road;

The write address generation unit produces write address according to this count value, and this write address is sent to reads address-generation unit.

5. a kind of deinterleaver as claimed in claim 1 is characterized in that, at K _r=K _R-DThe time, said frame counter is in reset mode, and frame count value t is 0; At K _r≠ K _R-DThe time, said frame counter is in count status, and frame count value t counts from 0 to D-1.

6. a de-interweaving method is used for the input data b _{R, i}Deinterleaving becomes dateout c _{R, i}, and satisfy c _{R, i}=b _{R-g (i), i}(0≤i≤M _r-1), wherein deinterleaving postpones g (i) and satisfies g (i)=g (mod (i, J)), (i J) asks modular arithmetic for i to J to mod, and b _{R, i}, c _{R, i}Frame length is respectively M _rAnd N _r, and M _r=min (N _r, N _R-D),

N _r=K _rJ, wherein N _r, K _rBe variable, N _rThe expression width, J is a constant, it is characterized in that, comprise,

With said width N _rIt is J and degree of depth K that variable deinterleaving is converted into fixed width _rThe variable deinterleaving of g (i), and ask the mould value identical and postpone identical branch road equivalence and be one and have K to J all _rThe branch road that doubly should postpone, and through write address in memory and read the address and realize;

This write address does,

A _n+1，w＝(A _n，w+K _maxg(n))mod?N _A；

At K _r＞K _R-DThe time,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)+|K _r-K _r-D|·min(t，g(n)))mod?N _A；

At K _r＜K _R-DThe time,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)-|K _r-K _r-D|·min(t，g(n)))mod?N _A；

At K _r=K _R-DThe time,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n))mod?N _A；

The said address A that reads _{N+1, r}For,

A _n+1，r＝(A _n+1，w-(K _max-K _r-D)g(n)+(K _r-K _r-D)·min(t，g(n)))mod?N _A

Wherein, A _{N+1, w}Be n+1 branch road write address, K _MaxBe the maximum frame length that interleaver is supported, N _ABe the required memory address number of memory, t is a frame count value.

Images