CN101669196A - multifinger carbon nanotube field-effect transistor - Google Patents

multifinger carbon nanotube field-effect transistor Download PDF

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CN101669196A
CN101669196A CN200880003634.5A CN200880003634A CN101669196A CN 101669196 A CN101669196 A CN 101669196A CN 200880003634 A CN200880003634 A CN 200880003634A CN 101669196 A CN101669196 A CN 101669196A
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effect transistor
field effect
electrode
nanotube
grid
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CN101669196B (en
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Z·于
P·J·伯尔克
S·麦基南
D·王
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RF Nano Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/202—Integrated devices comprising a common active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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Abstract

A kind of grid (multifinger) carbon nanotube field-effect transistors (CNT FET) that refer to are provided more, and wherein a plurality of nanometers top grid FET is incorporated on the finger-like solid along the length of the random alignment of the array of the nanotube of single carbon nanotube, alignment or nanotube.Each independent FET is provided so that between gate finger electrodes on the single carbon nanotube and drain electrode finger electrode does not have overlapping structure how much, thereby minimizes the miller capacitance (Cgd) between gate finger electrodes and the drain electrode finger electrode.Low-K dielectric can be used for separating source electrode and the gate electrode that refers among the grid CNT FET more, further to minimize the miller capacitance between source electrode and the gate electrode.

Description

Multifinger carbon nanotube field-effect transistor
Technical field
[0001] the present invention relates generally to the nanotube device field, more specifically, relate to referring to grid (multifinger) carbon nanotube field-effect transistors (CNT FET) more.
Background technology
[0002] in theory, the predicted intrinsic cut-off frequency that has near Terahertz (THz) scope of many Single Walled Carbon Nanotube field-effect transistors (SWNT FET), wherein intrinsic refers to, and the gate-to-source electric capacity required with adjusting conductivity is compared, and the parasitic capacitance that fringing field produces can be ignored.Yet in actual applications, this parasitic capacitance is usually occupied the geometry of most of CNT FET.
[0003] when making an independent CNT FET, useful is to measure its whole S parameters (or Z, h or abcd matrix of equivalence), propose equivalent-circuit model then, it can be compared with theoretical model, and makes up the not only more complicated circuit of a CNT FET as the basis.Yet in fact, the high impedance of single CNT FET and low operating current have hindered the previous trial that obtains these measured values.
Summary of the invention
[0004], is provided at the nanotube device that has a plurality of finger electrodes on the single nanotube according to feature of the present invention.One or more than an embodiment in, this nanotube device comprises multifinger carbon nanotube field-effect transistor (CNT FET), and a plurality of carbon nano-tube top grid field effect transistor (FET) thereon uses a segment length of Single Walled Carbon Nanotube to be merged into the finger-like solid.One or more than an embodiment in, low-K dielectric can be used for separating source electrode and the gate electrode that refers among the grid CNTFED more, so that the electric capacity between source electrode and the gate electrode (being miller capacitance) minimum.
[0005] according to another feature of the present invention, the nanotube device that provides comprises multifinger carbon nanotube field-effect transistor (CNT FET), form a plurality of nanotubes between source finger electrodes thereon and the drain electrode finger electrode, wherein a plurality of nanotubes can be aligned or form at random.
[0006] one or more than an embodiment in, use a Single Walled Carbon Nanotube that 100 independent μ m are long, it is the one-transistor (after going to embed the parasitic capacitance of finger) of 7.65GHz to produce cut-off frequency that 100 independent nanotube top grid field effect transistors are merged into a finger-like solid; Before going embedding, cut-off frequency is 0.2GHz.After going embedding, the maximum stable gain value drops to the integer (extrapolation obtains) above 15GHz, and before going embedding, the maximum stable gain value drops to integer 2GHz (recording).Use this structure, keep by the device of combination greater than the direct current power of 1mW with above the mutual conductance (dc) of 1.5mS.According to the great progress of multifinger carbon nanotube field-effect transistor (CNT FET) expression that various embodiment described herein form, it allows nanotube technology to use in RF and microwave frequency applications.
[0007] according to another feature of the present invention, the nanotube device with a plurality of finger electrodes is used in the circuit with amplification RF signal and drives 50 ohm load, thereby the nanotube amplifier that drives 50 ohm load is provided.
Description of drawings
[0008] with reference to the following describes book also in conjunction with the accompanying drawings, above-mentioned feature of the present invention and target will become more obvious, and wherein identical reference number is represented components identical, and wherein:
[0009] Fig. 1 is the schematic diagram of multifinger carbon nanotube field-effect transistor (CNT FET) according to an embodiment of the invention.
[0010] Fig. 2 is ESEM (SEM) image of an embodiment of multifinger carbon nanotube field-effect transistor (CNT FET) according to an embodiment of the invention.
[0011] Fig. 3 A and Fig. 3 B are the part diagrammatic layout figure of multifinger carbon nanotube field-effect transistor (CNT FET) according to an embodiment of the invention.
[0012] Fig. 4 A shows the I-V characteristic curve that records from exemplary multifinger carbon nanotube field-effect transistor formed according to the present invention (CNT FET) under the room temperature condition.
[0013] Fig. 4 B illustrates the exemplary multifinger carbon nanotube field-effect transistor (CNT FET) of Fig. 4 A at V DsLow bias depletion curve during=0.5V.
[0014] Fig. 4 C illustrates DC and the 1GHz dl of exemplary multifinger carbon nanotube field-effect transistor (CNT FET) under various bias conditions of Fig. 4 A Ds/ dV DsValue.
[0015] Fig. 5 is the image of the electrode capacitance that records from exemplary multifinger carbon nanotube field-effect transistor formed according to the present invention (CNT FET) of expression.
[0016] Fig. 6 is the image of the current gain of expression exemplary multifinger carbon nanotube field-effect transistor (CNT FET) formed according to the present invention to frequency.
[0017] Fig. 7 is that expression exemplary multifinger carbon nanotube field-effect transistor (CNT FET) formed according to the present invention goes before the intercalation electrode electric capacity and the image of MSG afterwards.
[0018] Fig. 8 is the circuit diagram that shows the multifinger carbon nanotube field-effect transistor (CNT FET) in the exemplary circuit that is used for amplification RF signal according to one embodiment of present invention and drives load.
[0019] Fig. 9 illustrates the I-V characteristic curve of Fig. 8 circuit.
Embodiment
[0020] the present invention relates to multifinger carbon nanotube field-effect transistor (CNT FET) and manufacture method thereof.One or more than an embodiment in, a plurality of finger electrodes that the multifinger carbon nanotube field-effect transistor that provides (CNT FET) 100 has on single nanotube 102 are shown in the schematic diagram of Fig. 1.Refer to that grid CNT FET 100 comprises source electrode 104, drain electrode 106 and grid 108, it has respectively from nanotube 102 outward extending finger electrode 104a, 106a and 108a more.
[0021] one or more than an embodiment in, nanotube 102 is carbon nano-tube (CNT) of certain-length, it is synthetic by chemical vapor deposition according to any CNT method known to those skilled in the art.CNT 102 is deposited on oxidized high resistivity silicon (Si) wafer, and this silicon wafer has dielectric layer formed thereon (as the silicon dioxide (SiO of 300-400nm 2) layer).Use el and metal vaporization technology on CNT 102, to form metal electrode (source electrode 104, drain electrode 106, grid 108 and separately finger electrode 104a, 106a and 108a).At one or more than an embodiment, metal electrode comprises the bilayer of 30nm palladium (Pd)/100nm gold (Au).The silicon dioxide (as have 10nm thickness) of vaporization is used as insulator, and Au top grid are vaporized.The width of gate finger electrodes 108a is littler than the gap between source finger electrodes 104a and the drain electrode finger electrode 106a, so that the length of nanotube 102 part is not by gridization.
[0022] for example, can form the source electrode-drain gaps 110 that is approximately 0.8 μ m, and the width of gate finger electrodes 108a is approximately 0.2 μ m.Fig. 2 demonstrates the SEM image of the part of an embodiment who refers to grid CNT FET 100 this kind with this kind size more.In the SEM image, before the deposit dielectric (not shown), nanotube 102 is visible in the top-right illustration.After dielectric and top grid were deposited formation, in the SEM image, nanotube 102 was sightless.
[0023] one or more than an embodiment in, 2x gate finger electrodes 108a, x source finger electrodes 104a (providing electric current at both direction) and x drain electrode finger electrode 106a (in the both direction absorption current) (wherein x＞1) is connected electrically in together as described here on the chip and is obtained 2x CNT FET altogether, and these CNT FET are in parallel to be electrically connected how to form finger grid CNT FET 100.In one embodiment, select x=50 so that 100 gate finger electrodes 108a, 50 source finger electrodes 104a and 50 drain electrode finger electrode 106a, 100 independent CNT FET in parallel altogether that these electrodes are electrically connected and obtain making up to be provided.Because each the independent CNT FET that makes on identical nanotube 102 has identical geometry usually, so wish that the electrical property of the CNT FET that each is independent is identical.Electrical property by the independent CNT FET (as 100) that will make on a long nanotube 102 merges to " on the chip ", can realize that maximum stable gain surpasses the performance of the nanotube transistor of 1GHz (even comprising parasitic capacitance), also solve resistance matching problem simultaneously by electric current being increased to big numerical value (mA).Then, the source/drain/gate electrodes 104a/106a/108a coplanar waveguide structure (not shown) that can be electrically connected to industrial standard with the RF probe station compatibility of commerce.
[0024] one or more than an embodiment in, use the nanotube device 120 of the identical a plurality of nanotubes 122 of electrode geometry can be used for replacing single nanotube 102.For example, the SWNT 122 of a plurality of random orientations can be formed on source electrode 104 and drain between 106, meaning property demonstration as shown in Fig. 3 A, or the array of a plurality of SWNT 122 of alignment can be formed on source electrode 104 and drain between 106 meaning property demonstration as shown in Fig. 3 B.The nanotube device 120 that is formed with a plurality of nanotubes 122 will be formed and with Fig. 1 in the functional similarity of many fingers grid CNT FET100 of describing.
[0025] one or more than an embodiment in, be formed with the Miller effect minimum that many fingers grid CNT FET 100 of referring to the gate electrode geometry this kind will make in the device more.The Miller effect at grid 108 and the effective capacitance (Cgd) that causes between 106 of draining be the input electric capacity (1+ gain) doubly.Therefore, miller capacitance (Cgd) need be held minimum so that make the corresponding maximum of frequency.Refer to that how much overlapping structures of nothing can stop the Miller effect that can not stop to grid CNT FET 100 between gate finger electrodes 108a and the drain electrode finger electrode 106a in traditional CNT FET device by being provided at more.One or more than an embodiment in, by using low-K dielectric to separate source electrode 104/ gate electrode 106 so that the electric capacity minimum between two electrodes 104/106 can further reduce the Miller effect.By using low-K dielectric to separate grid-source electrode 104/106, the electric capacity (Cgs) between grid 104 and the source electrode 106 is minimized so that the high frequency characteristics maximization of installing.
[0026] at one or more than an embodiment, the finger electrode 104a/106a/108a that forms can lack the wider width (as wideer than several microns) that (as less than about several microns) and the lead electrode 104/106/108 that is in contact with it form relatively, so that the resistance minimum of lead electrode 104/106/108, wherein the inductance of the resistance of grid 108 and lead electrode is minimized especially.
[0027], illustrates from according to one or the room temperature I-V characteristic curve that records more than the exemplary multifinger carbon nanotube field-effect transistor that forms the embodiment (CNT FET) with reference now to Fig. 4 A.Fig. 4 B further illustrates low bias depletion curve, and simultaneously, Fig. 4 C illustrates DC and the 1GHz dl under various bias conditions Ds/ dV DsValue.In addition, Fig. 4 C illustrates the contrast of differential resistor (according to the I-V curve that records) with the differential resistor (will further describe below) of the microwave S parameter that records of dc.The result of explanation is gratifying illustrated among Fig. 4 A-4C: under various bias conditions, the dynamic source electrode-drain impedance when 1GHz is identical with dynamic source electrode-drain impedance when the dc.The previous measurement of carrying out equal number in independent nanotube part on these results and the FET that forms is consistent.
[0028] one or more than an embodiment in, RF characteristic for many fingers grid CNT FET 100, the microwave probe that use can be bought (being suitable for calibrating with the calibration criterion of the short/open/load that can buy/penetrate (SOLT)) can be carried out the microwave measurement that refers to grid CNT FET 100 more, and microwave measurement can be allowed to co-planar waveguide (CPW) electrode on (lithographically) makes from the coaxial transition to the lithographic printing the chip.Microwave network analyzer can be used for measuring the S parameter (S of absolute calibration (complexity) 11, S 12, S 21, S 22).The SOLT calibration procedure can be used on the commercial calibration chip.
[0029] one or more than an embodiment in, the calibration criterion wafer should not have the many fingers grid geometry that refers to grid CNT FET 100 more, so, by measuring S parameter, because the parasitic capacitance that finger electrode 104a/106a/108a produces (mainly being because the fringe field between these finger electrodes 104a/106a/108a produces) can be determined exactly without any the control device of nanotube.According to the S parameter that records on the control finger device, Y matrix and electric capacity (using suitable fundamental relation Y=i ω C) can be determined.According to these values, three parasitic capacitance Cgs, Cgd, Cds can be determined, and it is marked in the schematic diagram of Fig. 5.According to the point in Fig. 5, it is irrelevant to clearly show frequency and electric capacity, and it has verified the calibration and the model of ghost effect, and wherein absolute value coincide better with the electric capacity that calculates according to electrode geometry.
[0030] parameter commonly used of expression high frequency (HF) transistor quality is a cut-off frequency, and it is defined as the frequency that current gain (H21) drops to 0dB.Refer to one of grid CNT FET 100 or, because the required gate-to-source electric capacity of parasitic capacitance and adjustment conductivity compares greatly, so cut-off frequency is limited more than among the embodiment more.By measuring the whole S parameters that refer to grid CNT FET 100 more, a kind of technology is provided, it is complete many fingers grid CNT FET 100 device extraction cut-off frequencies of 0.2GHz, as shown in Fig. 6 key diagram.
[0031] known because of parasitic capacitance (Cgs, Cgd, Cds), thus these can " by deducting " to determine " intrinsic " performance of many finger grid CNT FET 100.Equally, " intrinsic " refers to the gate-to-source electric capacity required with adjusting conductivity and compares, and the parasitic capacitance that fringing field produces can be ignored.In practice, the Y matrix that records by use deducts control (open circuit) the Y matrix (only being determined) of finger electrode 104a/106a/108a in separating matrix, obtain " intrinsic " Y matrix: Y Intrinsic=Y Measured-Y Control, can carry out this and go the embedding program.Then, Y IntrinsicCan be used to find intrinsic (being gone to embed) S, h, Z and abcd matrix.After this program of execution, the intrinsic cut-off frequency of 7.65GHz (removes to embed current gain H 21Drop to the frequency of 0dB) found in one embodiment, as shown in Figure 6.This is illustrated on the nanotube FET in the maximum cut-off of once measuring one.
[0032] second parameter commonly used of expression high frequency (HF) transistor quality is that maximum stable gain (is defined as S 21/ S 12) drop to the frequency of 0dB.Limit and f MAXDepend on whole 4 S parameters, so this is not always the f of direct measurement MAX, maximum oscillation frequency.Yet it can flat-footedly be measured, as measuring S 21And S 12The same, so it is generally as " basic (poor man ' s) " quality factor.With reference now to Fig. 7,, provides to embed before the parasitic capacitance and the key diagram of maximum stable gain (MSG) afterwards.Curve extrapolation is to 15GHz, and it is among the highest MSG of the nanotube device once reported one.
[0033] author of the present invention has determined that clearly removing to embed cut-off frequency can be used for measuring the ultimate performance that refers to grid CNT FET 100 more.In side circuit,, electrode refers to that electrode just must also be calculated in any application, especially in the nanometer circuit on the grid CNT FET 100 when being connected to more.In other words, although refer to that the embedded performance that goes of grid CNT FET 100 may highly significant, how finger grid CNT FET 100 can be by before in side circuit more, quantizes and represents that any contact electrode is important.More importantly, the measurement of foregoing description determines clearly to refer to that the transistance among the grid CNT FET 100 lasts till 10GHz always more.In optional embodiment, minimum ghost effect can be used for determining meticulousr RF circuit model into nanotube intrinsic performance.
[0034] one or more than an embodiment in, refer to that grid CNT FET 100 can be used in the circuit with amplification RF signal and drives load, as shown in the circuit diagram of Fig. 8 more.One or more than an embodiment in, load is 50 ohm load, so that provide the nanotube amplifier in order to drive 50 ohm load.The nanotube device of prior art can not realize the high power of the about 1mW of any ratio, and nanotube device wherein of the present invention can expand to a plurality of watts (W) device of using in the power amplifier.This circuit gain is by following The Representation Equation:
Gain＝2g mZ load||g d
[0035] according to following input can implementation value less than 1 gain: g m=1mS, Z Load=50 Ω, and g d=300 Ω.Believe that use is such as g m=1mS, Z Load=1k Ω, and g dThe input of=10k Ω, and it is saturated to use impedance matching circuit and high quality dielectric that circuit bias is arrived, and can realize that gain is greater than 1.Some interpretation in the I-V characteristic curve shown in Figure 9 is in order to improve the expection bias point of gain.
[0036] although described system and method according to the specific embodiment of present consideration, the present invention need not be confined among the disclosed embodiment.The objective of the invention is to cover the various modifications and similar layout that comprise in claim scope and the thought, scope of the present invention should be understood that to explain widely, so that surround all this type of modification and analog structures.The present invention includes any and whole embodiment of claim.

Claims (18)

1. refer to the grid nanotube field effect transistor one kind, it comprises more:
Have the single nanotube of length, it is formed in the substrate;
A plurality of field effect transistor devices, it is formed on the described single nanotube and in parallel the electrical connection.
2. the grid nanotube field effect transistor that refers to according to claim 1 more, each in wherein said a plurality of field effect transistor devices comprises:
A plurality of parallel finger electrodes, it is formed on the described single nanotube.
3. the grid nanotube field effect transistor that refers to according to claim 2 more, wherein said a plurality of parallel finger electrode comprises source finger electrodes, drain electrode finger electrode and gate finger electrodes, and wherein each finger electrode has the width that extends beyond described single nanotube counterpart.
4. the grid nanotube field effect transistor that refers to according to claim 3 more, its further be included in do not have between described gate finger electrodes on the described single nanotube and the described drain electrode finger electrode how much overlapping.
5. the grid nanotube field effect transistor that refers to according to claim 3, wherein said source finger electrodes, drain electrode finger electrode and gate finger electrodes are configured to minimize the miller capacitance (Cgd) between described gate finger electrodes and the described drain electrode finger electrode more.
6. the grid nanotube field effect transistor that refers to according to claim 2, the many fingers grid nanotube field effect transistor that is combined as combination that wherein has described a plurality of parallel field effect transistor devices of a plurality of parallel finger electrodes provides lower output impedance more.
7. the grid nanotube field effect transistor that refers to according to claim 3 further comprises low-K dielectric more, and it separates described source finger electrodes and described gate finger electrodes.
8. the grid nanotube field effect transistor that refers to according to claim 7, wherein said low-K dielectric minimizes the electric capacity between described source finger electrodes and the described gate finger electrodes more.
9. the grid nanotube field effect transistor that refers to according to claim 2, wherein said transistor can expand to a plurality of watts of devices more.
10. the grid nanotube field effect transistor that refers to according to claim 3 more, it further comprises: the source electrode lead electrode, drain conductors electrode and the grid lead electrode that are connected respectively to described source finger electrodes, described drain electrode finger electrode and described gate finger electrodes, the length of each in wherein said source finger electrodes, described drain electrode finger electrode and the described gate finger electrodes is less than its width of source lead electrode, drain lead electrode and grid lead electrode separately, so that the resistance of described lead-in wire electrode and inductance minimum.
11. refer to the grid nanotube field effect transistor one kind, it comprises more:
A plurality of field effect transistor devices, it is formed in the substrate and in parallel the electrical connection, and each in the wherein said field effect transistor devices comprises parallel source finger electrodes, drain electrode finger electrode and gate finger electrodes; And
A plurality of nanotubes, it is formed in described a plurality of field effect transistor devices between the described source finger electrodes and described drain electrode finger electrode on each.
12. the grid nanotube field effect transistor that refers to according to claim 11, wherein said a plurality of nanotubes comprise the single-walled nanotube of random orientation more.
13. the grid nanotube field effect transistor that refers to according to claim 11, wherein said a plurality of nanotubes comprise the array of the single-walled nanotube of a plurality of alignment more.
14. the grid nanotube field effect transistor that refers to according to claim 11 more, its further be included in do not have between described suprabasil described gate finger electrodes and the described drain electrode finger electrode how much overlapping.
15. the grid nanotube field effect transistor that refers to according to claim 11, wherein said source finger electrodes, described drain electrode finger electrode and described gate finger electrodes are configured to minimize the miller capacitance (Cgd) between described gate finger electrodes and the described drain electrode finger electrode more.
16. the grid nanotube field effect transistor that refers to according to claim 11, the many fingers grid nanotube field effect transistor that is combined as combination that wherein has described a plurality of parallel field effect transistor devices of a plurality of parallel finger electrodes provides lower output impedance more.
17. a superelevation radio frequency (RF) carbon nanotube device, it comprises:
Have the single nanotube of length, it is formed in the substrate;
A plurality of field effect transistor devices, it is formed on the described single nanotube and in parallel the electrical connection, and each in the wherein said field effect transistor devices comprises parallel source finger electrodes, drain electrode finger electrode and gate finger electrodes;
The input of RF signal; And
Be connected to the load of described a plurality of field effect transistor devices, the combination of the field effect transistor devices of wherein said parallel connection is amplified described RF signal input and is driven the load that is connected.
18. superelevation radio frequency according to claim 17 (RF) carbon nanotube device, wherein said device are incorporated in power amplifier, low noise amplifier (LNA), non-linear device, non-linear frequency mixing device or the nonlinear detector at least one employed circuit.
CN200880003634.5A 2007-01-30 2008-01-29 Multifinger carbon nanotube field-effect transistor Expired - Fee Related CN101669196B (en)

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US12/021,042 US8039870B2 (en) 2008-01-28 2008-01-28 Multifinger carbon nanotube field-effect transistor
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