CN101667167A - Universal serial bus device and correcting method thereof - Google Patents
Universal serial bus device and correcting method thereof Download PDFInfo
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- CN101667167A CN101667167A CN200910207014A CN200910207014A CN101667167A CN 101667167 A CN101667167 A CN 101667167A CN 200910207014 A CN200910207014 A CN 200910207014A CN 200910207014 A CN200910207014 A CN 200910207014A CN 101667167 A CN101667167 A CN 101667167A
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Abstract
A universal serial bus device is used for receiving data from linked partner. An electronic entity unit receives the data from the linked partner and generates a code element string. A correcting unitjudges whether each code element in the received code element string is a code element of the first type and counts the amount of the received code elements of the first type, wherein when the counted amount is odd number and the next received code element is of a second type, the next received code element is replaced by the code element of the first type. A decoder decodes the code element fromthe correcting unit as the decoded data. A descrambler descrambles the decoded data according to a seed. When the decoded data corresponds to the code element of the second type, the linear feedbackshift register of the descrambler updates the seed according to a specified query table.
Description
Technical field
The invention relates to a kind of universal serial bus device, particularly cross over the universal serial bus device of code element relevant for a kind of recoverable.
Background technology
(Universal Serial Bus, USB) for connecting a kind of serial bus standard of external unit, it can support hot plug (Hot plug) and plug and play functions such as (Plug and Play) to USB (universal serial bus).
Now, USB 2.0 specifications can provide low speed, full speed and high-speed transfer, and it can support the data volume of maximum 1.5Mbps, 12Mbps and 480Mbps respectively.Yet along with the increase of sophisticated functions, electronic product needs USB transfer rate more at a high speed, so that can be more quickly from external unit access data and the relevant running program of execution.
Therefore, USB implements the specification that forum (USB Implementers Forum) has worked out USB 3.0, it can provide the message exchange of hypervelocity (SuperSpeed) and non-hypervelocity (being USB 2.0) simultaneously, and wherein the hypervelocity transmission can be supported the data volume of maximum 5G bps.
Summary of the invention
The invention provides a kind of universal serial bus device, have first work clock, in order to receive data from link partner.Above-mentioned universal serial bus device comprises: electronic entity unit, be coupled to above-mentioned link partner via cable, come from the serial bit data of above-mentioned link partner in order to reception, and produce the code-element string corresponding to above-mentioned serial bit data, wherein above-mentioned code-element string comprises a plurality of code elements; Correcting unit, be coupled to above-mentioned electronic entity unit, in order to receive above-mentioned code-element string, to judge whether each the above-mentioned code element in the above-mentioned code-element string that is received is the quantity of the above-mentioned first kind code element of first kind code element and counting reception, wherein when the quantity of counting be that odd number and the next above-mentioned code element that is received are when being the second type code element, the above-mentioned code element that the above-mentioned next one received is replaced with above-mentioned first kind code element, and wherein above-mentioned first kind code element is for crossing over code element.
Moreover, the invention provides a kind of bearing calibration, be applicable to universal serial bus device with first work clock, wherein above-mentioned bearing calibration comprises the serial bit data of reception from link partner, and producing code-element string corresponding to above-mentioned serial bit data, wherein above-mentioned code-element string comprises a plurality of code elements.Receive above-mentioned code-element string and judge whether each the above-mentioned code element in the above-mentioned code-element string is the quantity of the above-mentioned first kind code element of first kind code element and counting reception, and wherein above-mentioned first kind code element is for crossing over code element.When the quantity of counting is odd number and the next above-mentioned code element that is received when being the second type code element, the above-mentioned code element that the above-mentioned next one received is replaced with above-mentioned first kind code element.
Description of drawings
Fig. 1 is the synoptic diagram that shows hypervelocity data transfer between two universal serial bus devices;
Fig. 2 shows a kind of data packet that meets USB 3.0 specifications;
Fig. 3 A shows a tables of data, the data that will transmit in the link partner 10 in its presentation graphs 1;
Fig. 3 B shows a tables of data, the data that received in the link partner 20 in its presentation graphs 1;
Fig. 4 A shows a tables of data respectively, and first crosses over the wrong situation of code element among its presentation graphs 3B;
Fig. 4 B shows a tables of data respectively, and second crosses over the wrong situation of code element among its presentation graphs 3B;
Fig. 5 shows according to the described universal serial bus device of one embodiment of the invention;
Fig. 6 A shows according to the described tables of data of one embodiment of the invention the data that received in the link partner 40 in its presentation graphs 5;
Fig. 6 B-8B shows according to the described tables of data of another embodiment of the present invention the data that received in the link partner 40 in its presentation graphs 5; And
Fig. 9 shows according to the described a kind of bearing calibration of one embodiment of the invention.
[main element label declaration]
10,20,40～link partner; 11,21～processing unit;
12～scrambler; 13～scrambler;
14,24～electronic entity unit; 15,25～linear feedback shift register;
22～descrambler; 23～demoder;
26～time the clock correction compensating unit; 30～cable;
41～correcting unit; 200～data packet;
210～data packet header; The load of 220～data packet;
230～header is packaged into frame; 232,234,236,238～code element;
610,660～leap code element;
710,720,760,770,810,860～leap is organized in order; And
S
COMP, S
CORR, S
DEC, S
ENC, S
IN, S
SCR, TXData, RXData～data.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Embodiment:
Fig. 1 is the synoptic diagram that shows hypervelocity (SuperSpeed) data transfer between two universal serial bus devices 10,20.In Fig. 1, USB (universal serial bus) (USB) device 10 transmits data via cable 30 and gives USB (universal serial bus) 20, and wherein universal serial bus device 10 is link partner (link partner) with universal serial bus device 20.Link partner 10 comprises processing unit 11, scrambler 12, scrambler 13 and electronic entity unit 14, and wherein scrambler 12 comprises linear feedback shift register (linearfeedback shifter register) 15.At first, processing unit 11 provides the raw data TXData that will be transmitted to scrambler 12, and wherein data TXData has 8 bit lengths.Then, scrambler 12 can carry out scrambling to produce scrambled data S to data TXData according to the seed (seed) that linear feedback shift register 15 is provided
SCRThen, scrambler 13 can be with scrambled data S
SCRBe encoded into data S
ENCAnd be sent to electronic entity unit 14.Scrambler 13 uses 8/10 (8b/10b) coding techniquess to data S
SCREncode, so data S
ENCBe code element (symbol) with 10 bit lengths.Then, electronic entity unit 14 is with data S
ENCBy being converted to serial (parallel to serial) side by side, and be sent to link partner 20 via cable 30.Electronic entity unit 14 is a kind of I (Input/OutputInterface) unit, in order to receive and to transmit the differential-pair signal that meets the USB specification.
With reference to figure 1, link partner 20 comprise processing unit 21, descrambler 22, demoder 23, the time clock correction compensating unit 26 and electronic entity unit 24, wherein descrambler 22 comprises linear feedback shift register 25.When link partner 20 received serial bit data (or bit data stream) from link partner 10, the bit data that electronic entity unit 24 can will receive continuously for side by side, had a plurality of data Ss with formation by serial conversion
INCode-element string, each data S wherein
INFor having the code element of 10 bit lengths.Then, the time clock correction compensating unit 26 can determine whether needing to carry out a compensation program according to the difference on the frequency between second work clock of first work clock of link partner 20 and link partner 10, make that the information rate of the data transfer rate of link partner 10 and link partner 20 can be synchronous.When the difference on the frequency between two work clocks is very little, the time clock correction compensating unit 26 can be directly with data S
INOffer demoder 23 and do not carry out compensation program, i.e. data S
COMPCan be same as data S
INTherefore, when in the data transfer during undistorted generation, the data S that link partner 20 is received
COMPCan be same as the data S in the link partner 10
ENCThen, demoder 23 can use 8/10 decoding techniques with data S
COMPBe decoded as data S
DECSimilarly, when data transfer is correct, the data S that link partner 20 is received
DECCan be same as the data S in the link partner 10
SCRThen, separate and confuse seed that device 22 can be provided according to linear feedback shift register 25 data S
DECCarry out descrambling to produce data RXData, carry out follow-up application for processing unit 21 to processing unit 21.
In Fig. 1, in order correctly to restore the data TXData that link partner 10 will transmit, the scrambler 12 of link partner 10 and the descrambler of link partner 20 22 employed seeds must be synchronously.Linear feedback shift register 15 and linear feedback shift register 25 can provide seed in a set mode (for example according to specific tabling look-up (lookup table)) simultaneously.Therefore, after simultaneously to linear feedback shift register 15 and linear feedback shift register 25 setting initial values, then the seed of linear feedback shift register 15 and linear feedback shift register 25 can change synchronously, and promptly linear feedback shift register 15 and linear feedback shift register 25 have identical seed.In addition, in the specification of USB3.0, can use calibration symbols (COM) to come the linear feedback shift register of scrambler/de-scrambler is set initial value, with the seed of each link partner internal linear feedback shift register of initialization.Therefore, before transmitting data, can use calibration symbols to come synchronization links partner 10 the linear feedback shift register 15 and the linear feedback shift register 25 of link partner 20.Moreover the specification of USB 3.0 also discloses can use leap code element (SKP) to make linear feedback shift register stop more new seed, makes seed to remain unchanged.The form of crossing over code element is " 0011111001 " and " 1100000110 ".Generally speaking, except calibration symbols and leap code element, the code element of other type all can make the linear feedback shift register of scrambler/de-scrambler that seed is upgraded.
Fig. 2 shows a kind of data packet 200 that meets USB 3.0 specifications.Data packet 200 comprises data packet header 210 and data packet load (payload) 220, and wherein data packet header 210 and data packet load 220 are made up of a plurality of code element.In data packet header 210, header is packaged into frame (framing) 230 and comprises code element 232,234,236 and 238, and wherein code element 232 is the code element that transmits at first in the data packet 200.In addition, header is packaged into the serious forgiveness (error tolerance) that frame 230 allows a code element.Therefore, in data transmission procedure, when header is packaged into that a code element in the frame 230 makes a mistake and other three code element when being correct, the link partner of receiving end must be considered as active data with data packet 200.In addition, the link partner of the transmission end situation of can looking transmit to be crossed over group (SKP Ordered Set) in order with clock (clock) difference on the frequency between the link partner of the link partner of compensation receiving end and transmission end between two data packets.In the specification of USB 3.0, one crosses in order, and group comprises that two cross over code element.For example, first crosses over code element " 0011111001 " crosses over code element " 1100000110 " with second, or the first leap code element " 1100000110 " is crossed over code element " 0011111001 " with second.In addition, according to the USB3.0 specification, average per 354 code elements of the link partner of transmission end need transmit one and cross over the link partner of organizing in order to receiving end.Yet the link partner of transmission end can not inserted in arbitrary data packet and cross over group in order, so the link partner of transmission end can be accumulated the quantity of crossing over orderly group sends receiving end again to after data packet has transmitted link partner.Moreover when receiving the orderly group of leap, the link partner of receiving end can increase or reduce crosses over the orderly quantity of organizing to solve the nonsynchronous problem of clock between two link partner.
Fig. 3 A shows a tables of data 300, the data that will transmit in the link partner 10 in its presentation graphs 1.With reference to figure 1 and Fig. 3 A, link partner 10 can transmit data packet P1 in regular turn, cross over and organize PS and data packet P2 in order to link partner 20 simultaneously.In tables of data 300, the 1st row are data TXData that expression processing unit 11 is provided.The 2nd row are seed lfsr_1 that expression linear feedback shift register 15 is provided.The 3rd row are scrambled data S that expression scrambler 12 is provided
SCR, it is to produce according to seed lfsr_1 and data TXData.The 4th row are coded data S that presentation code device 13 is provided
ENCData EncA, EncB are last two code elements of data packet P1, and data EncC, EncD, EncE, EncF are preceding four code elements of data packet P2, and promptly header is packaged into frame.With data DataA is example, and scrambler 12 provides scrambled data ScrA according to data DataA and seed lfsrA.Then, scrambler 13 can be encoded to data EncA with scrambled data ScrA.It should be noted that scrambler 12 can not carry out scrambling to crossing over data SKP.In addition, if the data desiring to confuse are non-leap data, then scrambler 12 finish confuse after, linear feedback shift register 15 can be earlier more the new seed lfsr_1 data desiring to confuse for the next one use.For instance, after finishing scrambled data DataB, linear feedback shift register 15 can be updated to lfsrC with seed earlier.Therefore, when scrambler 12 received the first leap data SKP, scrambler 12 can directly provide crossed over data SKP (not confusing), and can not use seed lfsrC to carry out scrambling to crossing over data SKP.In addition, cross over data SKP owing to receive first, so linear feedback shift register 15 can not upgrade to seed, then seed can be maintained lfsrC.Then, scrambler 13 can be encoded to the first leap code element EncSKP with the first leap data SKP of not scrambling.Then, when scrambler 12 received the second leap data SKP, scrambler 12 can directly provide crossed over data SKP to scrambler 13, and seed also is maintained lfsrC.Then, scrambler 13 can be encoded to the second leap code element EncSKP with the second leap data SKP of not scrambling.
Fig. 3 B shows a tables of data 350, the data that received in the link partner 20 in its presentation graphs 1.Tables of data 350 is the data that transmitted corresponding to according to tables of data 300 among Fig. 3 A.With reference to figure 1, Fig. 3 A and Fig. 3 B, PS and data packet P2 are organized in data packet P1, leap that link partner 20 can receive in regular turn from link partner 10 in order simultaneously.In tables of data 350, the 1st row are the received input data S of expression electronic entity unit 24
INIn addition, in this embodiment, owing to do not need to carry out compensation program, input data S
INCan be directly by the time clock correction compensating unit 26 be passed to demoder 23, i.e. data S
COMPBe same as input data S
INThe 2nd row are decoded data S that expression demoder 23 is provided
DECThe 3rd row are seed lfsr_2 that expression linear feedback shift register 25 is provided.The 4th row are that expression descrambler 22 is according to seed lfsr_2 and decoded data S
DECThe descrambling data RXData that is provided.When data transfer is correct, the input data S that the electronic entity unit of link partner 20 24 is received
INCan be same as the coded data S that the scrambler 13 of link partner 10 is provided
ENCTherefore, the 1st row of tables of data 350 can be same as the 4th row of tables of data 300 among Fig. 3 A among Fig. 3 B.EncA is an example with the input data, and demoder 23 can be decoded as decoded data ScrA with data EncA.As described previously, when data transfer was correct, the 2nd row of tables of data 350 can be same as the 3rd row of tables of data 300 among Fig. 3 A among Fig. 3 B.Then, descrambler 22 can obtain descrambling data DataA according to decoded data ScrA and seed lfsrA.Therefore, the processing unit 21 of link partner 20 can correctly receive the data TXData that link partner 10 will transmit.It should be noted that the seed lfsr_2 of tables of data 350 among Fig. 3 B need be synchronized with the seed lfsr_1 of tables of data 300 among Fig. 3 A, could correctly restore the data TXData that link partner 10 will transmit.
Fig. 4 A and Fig. 4 B are difference video data table 400 and tables of data 450, and wherein tables of data 400 is wrong situations of the first leap code element among the presentation graphs 3B, and tables of data 450 is wrong situations of the second leap code element among the presentation graphs 3B.With reference to figure 1 and Fig. 4 A, when the electronic entity unit 24 first received leap code element EncSKP of link partner 20 lose the generation of true feelings condition (EncERR represents with data), demoder 23 can't identify data EncERR for crossing over code element simultaneously.Therefore, demoder 23 can be decoded as data ERR with data EncERR.Then, descrambler 22 can carry out descrambling to decoded data ERR according to seed lfsrC, to obtain descrambling DataK.After finishing descrambling data ERR, linear feedback shift register 25 can be updated to lfsrD with seed.Then, when link partner 20 receives the second leap code element EncSKP, then demoder 23 can be decoded as data EncSKP and cross over data SKP, and descrambler 22 can directly provide leap data SKP to processing unit 21, and linear feedback shift register 25 can not upgrade seed, and then seed can be maintained lfsrD.Significantly, when processing is crossed over code element from second of link partner 10, among Fig. 4 A the seed lfsr_2 of tables of data 400 asynchronous in Fig. 3 A the seed lfsr_1 of tables of data 300, so link partner 20 correctly descrambling restore the follow-up data that link partner 10 will transmit.For example, according to seed lfsrD, lfsrE, lfsrF and lfsrG, descrambler 22 obtains data DataL, DataM, DataN and DataO respectively, so link partner 20 can't restore data DataC, DataD, DataE and DataF.When link partner 20 can't receive correct data always, link partner 10 and link partner 20 needed the extra time to rebulid online and seed are carried out synchronization settings.Similarly, with reference to figure 4B, when link partner 20 receives (EncERR represents with data) when crossing over code element EncSKP and lose the true feelings condition and take place from second of link partner 10, seeds in link partner 10 and the link partner 20 will be no longer synchronous, thus link partner 20 also correctly descrambling restore the follow-up data that link partner 10 will transmit.
Fig. 5 shows according to the described universal serial bus device 40 of one embodiment of the invention.In Fig. 5, link partner 10 transmits data via cable 30 and gives USB (universal serial bus) 40, and link partner 10 provides data to link partner 40 according to second work clock, and link partner 40 is handled data from link partner 10 according to first work clock.Link partner 20 in Fig. 1, link partner 40 also comprise be coupled to electronic entity unit 24 and the time correcting unit 41 between the clock correction compensating unit 26.Correcting unit 41 receives the input data S from electronic entity unit 24 in regular turn
IN, and according to the input data S that is received
INCorrection data S is provided
CORRTo the time clock correction compensating unit 26.In Fig. 5, correcting unit 41 comprises counter 42.Correcting unit 41 is judged the input data S that is received
INWhether be to cross over code element, and usage counter 42 is counted the quantity of the leap code element that receives.For instance, when electronic entity unit 24 correctly receives when crossing in order group from one of link partner 10, counter 42 can count down to two and cross over code elements.Yet when cable 30 had interference to exist, crossing over orderly group may be disturbed in transmission course, made counter 42 only can count down to one and crossed over code element, shown in the data EncERR among Fig. 4 A and Fig. 4 B.Therefore, when counting down to odd number, counter 42 crosses over code element and the next input data S that is received
INDuring for non-leap code element, correcting unit 41 can be carried out a correction program, should non-leap code element replaces to the leap code element and clock correction compensating unit 26 when exporting to.Therefore, clock correction compensating unit 26 can receive even number and cross over code element the time.
Fig. 6 A shows according to the described tables of data 600 of one embodiment of the invention the data that received in the link partner 40 in its presentation graphs 5.Tables of data 600 is the data that transmitted corresponding to according to tables of data 300 among Fig. 3 A.With reference to figure 5 and Fig. 6 A, PS and data packet P2 are organized in data packet P1, leap that link partner 40 can receive in regular turn from link partner 10 in order simultaneously.In tables of data 600, the 1st row are the received input data S of expression electronic entity unit 24
INThe 2nd row are that expression correcting unit 41 is according to the data S from electronic entity unit 24
INThe correction data S that is provided
CORRIn this embodiment, the difference on the frequency between second work clock of link partner 10 and first work clock of link partner 40 is very little, thus the time clock correction compensating unit 26 do not need to carry out compensation program.Therefore, clock correction compensating unit 26 can directly provide correction data S the time
CORRTo demoder 23, i.e. data S
COMPBe same as correction data S
CORRThe 3rd row are that expression demoder 23 is according to data S
COMPThe decoded data S that is provided
DECThe 4th row are seed lfsr_2 that expression linear feedback shift register 25 is provided.The 5th row are that expression descrambler 22 is according to seed lfsr_2 and decoded data S
DECThe descrambling data RXData that is provided.Data EncA is an example with input, when correcting unit 41 judges that input data EncA are non-leap code element, and clock correction compensating unit 26 when correcting unit 41 can directly be passed to data EncA, and do not carry out correction program.Then, demoder 23 and descrambler 22 can correctly be reduced to data DataA with data EncA.In tables of data 600, first leap code element distortion (EncERR represents with data) among the PS is organized in electronic entity unit 24 received leaps in order, so correcting unit 41 can't be judged data EncERR for crossing over code element.So clock correction compensating unit 26 was to carry out subsequent treatment when correcting unit 41 can directly be passed to data EncERR.Then, descrambler 22 can be data DataK with data EncERR descrambling.Then, the leap that receives when electronic entity unit 24 is organized among the PS second when crossing over code element EncSKP in order, and correcting unit 41 can be judged data EncSKP for crossing over code element, and enabling counting device 42 is counted the quantity of the leap code element of follow-up continuous reception.Then, when electronic entity unit 24 received data EncC, next data EncC that correcting unit 41 can be judged after the data EncSKP was non-leap code element, and the value of being counted according to counter 42 judges whether to carry out correction program.In this embodiment, the value counted of counter 42 is 1 (odd number).Therefore, correcting unit 41 data EncC can be replaced to cross over code element EncSKP 610 and provide to the time clock correction compensating unit 26 to carry out subsequent treatment, wherein linear feedback shift register 25 can not upgrade seed, then seed can be maintained lfsrD.In addition, correcting unit 41 data EncC is replaced to cross over code element EncSKP after, also counter 42 can be reset, with the quantity of the leap code element of counting follow-up reception again.Then, when electronic entity unit 24 received data EncD, it was non-leap code element that correcting unit 41 can be judged data EncD, and clock correction compensating unit 26 was to carry out subsequent treatment when then correcting unit 41 can directly be passed to data EncD.So demoder 23 can be decoded as data ScrD with data EncD, and descrambler 22 can correctly be reduced to data DataD with data ScrD according to seed lfsrD.Therefore, carry out correction programs, synchronously the seed that provided of linear feedback shift register 15 and linear feedback shift register 25 by correcting unit 41.In addition, because header is packaged into the serious forgiveness that frame can allow a code element, processing unit 21 can be packaged into frame according to the header that data DataD, DataE, DataF detect data packet P2, and data packet P2 is considered as active data.Therefore, after correcting unit 41 was carried out correction program, processing unit 21 can correctly receive data packet P2.
Fig. 6 B shows according to the described tables of data 650 of another embodiment of the present invention the data that received in the link partner 40 in its presentation graphs 5.Tables of data 650 is the data that transmitted corresponding to according to tables of data 300 among Fig. 3 A.Tables of data 600 in Fig. 6 A, tables of data 650 are described when electronic entity unit 24 received leaps and are organized among the PS second in order when crossing over code element generation distortion, the result of correcting unit 41 execution correction programs.Correcting unit 41 data EncERR can be replaced to cross over code element EncSKP 660 and provide to the time clock correction compensating unit 26 to carry out subsequent treatment.Then, follow-up data DataC, DataD, DataE, DataF can correctly be reduced.Therefore, carry out the leap code element that correction program comes correcting distortion by correcting unit 41, the seed that provided of linear feedback shift register 15 and linear feedback shift register 25 makes processing unit 21 can correctly receive the data that link partner 10 will transmit synchronously.
When link partner 10 transmits a plurality of leaps when organizing PS in order between data packet P1 and data packet P2, but correcting unit 41 usage counters 42 are counted the quantity of the leap code element of continuous reception.For instance, next record data after correcting unit 41 is judged the leap data EncSKP of present reception are quantity that non-leap code element and counter 42 continuous counters are crossed over code element when being odd number (for example 3,5,7 etc.), correcting unit 41 these next record data can be replaced to cross over code element EncSKP with provide to the time clock correction compensating unit 26 and counter reset 42.Therefore, organizing in order when a plurality of leaps has among the PS when crossing over code element generation distortion, correcting unit 41 also can by carry out correction program export even number cross over code element to the time clock correction compensating unit 26.
Fig. 7 A shows according to the described tables of data 700 of another embodiment of the present invention the data that received in the link partner 40 in its presentation graphs 5.Tables of data 700 is the data that transmitted corresponding to according to tables of data 300 among Fig. 3 A, and tables of data 700 describes when electronic entity unit 24 received leaps organize in order that first work clock of crossing over code element generation distortion and two link partner 10 and 40 has big difference on the frequency to exist among the PS, correcting unit 41 execution correction programs and the time clock correction compensating unit 26 execution compensation program the result.In this embodiment, the frequency of first work clock of link partner 40 is greater than the frequency of second work clock of link partner 10, so cause data transfer rate and information rate between two link partner 10 and 40 asynchronous.Therefore, the time clock correction compensating unit 26 can cross in order the quantity of group and carry out compensation program by between first data packet and second data packet, increasing, to compensate the difference on the frequency between two work clocks.Simultaneously with reference to figure 5 and 7A figure, in tables of data 700, the 1st row are the input data S that represent that electronic entity unit 24 is received
INThe 2nd row are that expression correcting unit 41 is according to the input data S from electronic entity unit 24
INThe correction data S that is provided
CORRThe offset data S that clock correction compensating unit 26 was provided when the 3rd row were expression
COMPThe 4th row are decoded data S that expression demoder 23 is provided
DECThe 5th row are seed lfsr_2 that expression linear feedback shift register 25 is provided.The 6th row are that expression descrambler 22 is according to seed lfsr_2 and decoded data S
DECThe descrambling data RXData that is provided.As described previously, judging next record data after crossing over data EncSKP when correcting unit 41 is value that non-leap code element and counter 42 are counted when being odd number, correcting unit 41 the next record data can be replaced to cross over code element EncSKP 610 and provide to the time clock correction compensating unit 26.Then, receiving the orderly group of the leap that is provided by correcting unit 41 at 710 o'clock, the time clock correction compensating unit 26 can after crossing in order group 710, provide one to cross over and organize 720 in order to demoder 23, and then data EncD, data EncE and data EncF are sent to demoder 23 to carry out subsequent treatment.In this embodiment, processing unit 21 can be packaged into frame according to the header that data DataD, DataE, DataF detect data packet P2, and data packet P2 is considered as active data.Therefore, correcting unit 41 carry out correction programs and the time after clock correction compensating unit 26 carries out compensation program, processing unit 21 can correctly receive data packet P2.
Fig. 7 B shows according to the described tables of data 750 of another embodiment of the present invention the data that received in the link partner 40 in its presentation graphs 5.Tables of data 750 is the data that transmitted corresponding to according to tables of data 300 among Fig. 3 A, and tables of data 750 describes when electronic entity unit 24 received leaps organize in order that second work clock of crossing over code element generation distortion and two link partner 10 and 40 has big difference on the frequency to exist among the PS, correcting unit 41 execution correction programs and the time clock correction compensating unit 26 execution compensation program the result.In this embodiment, the frequency of first work clock of link partner 40 is greater than the frequency of second work clock of link partner 10.Similarly, clock correction compensating unit 26 leap that is provided by correcting unit 41 was provided organized at 760 o'clock in order at that time, the time clock correction compensating unit 26 can after crossing in order group 760, provide one to cross over and organize 770 in order to demoder 23, and then data EncC, data EncD, data EncE and data EncF are sent to demoder 23 to carry out subsequent treatment.In this embodiment, processing unit 21 header that can receive complete data packet P2 is packaged into frame (data DataC, DataD, DataE, DataF).Therefore, correcting unit 41 carry out correction programs and the time after clock correction compensating unit 26 carries out compensation program, processing unit 21 can correctly receive data packet P2.
Fig. 8 A shows according to the described tables of data 800 of another embodiment of the present invention the data that received in the link partner 40 in its presentation graphs 5.Tables of data 800 is the data that transmitted corresponding to according to tables of data 300 among Fig. 3 A, and tables of data 800 describes when electronic entity unit 24 received leaps organize in order that first work clock of crossing over code element generation distortion and two link partner 10 and 40 has big difference on the frequency to exist among the PS, correcting unit 41 execution correction programs and the time clock correction compensating unit 26 execution compensation program the result.In this embodiment, the frequency of first work clock of link partner 40 is less than the frequency of second work clock of link partner 10.Therefore, clock correction compensating unit 26 can be by reduce the quantity of crossing over orderly group between first data packet and second data packet, to compensate the difference on the frequency between two work clocks time.As described previously, judging next record data after crossing over data EncSKP when correcting unit 41 is value that non-leap code element and counter 42 are counted when being odd number, correcting unit 41 the next record data can be replaced to cross over code element EncSKP and provide to the time clock correction compensating unit 26.Then, receiving the leap that provided by correcting unit 41 group 810 o'clock in order, the time clock correction compensating unit 26 can not provide and cross in order group 810 to demoder 23.Then, when clock correction compensating unit 26 receives data EncD at that time, just can begin output data EncD to demoder 23 to carry out subsequent treatment.In this embodiment, processing unit 21 can be packaged into frame according to the header that data DataD, DataE, DataF detect data packet P2, and data packet P2 is considered as active data.Therefore, correcting unit 41 carry out correction programs and the time after clock correction compensating unit 26 carries out compensation program, processing unit 21 can correctly receive data packet P2.
Fig. 8 B shows according to the described tables of data 850 of another embodiment of the present invention the data that received in the link partner 40 in its presentation graphs 5.Tables of data 850 is the data that transmitted corresponding to according to tables of data 300 among Fig. 3 A, and tables of data 850 describes when electronic entity unit 24 received leaps organize in order that second work clock of crossing over code element generation distortion and two link partner 10 and 40 has big difference on the frequency to exist among the PS, correcting unit 41 execution correction programs and the time clock correction compensating unit 26 execution compensation program the result.In this embodiment, the frequency of first work clock of link partner 40 is less than the frequency of second work clock of link partner 10.Similarly, the leap that provided by correcting unit 41 group 860 o'clock in order was provided clock correction compensating unit 26 at that time, the time clock correction compensating unit 26 can not provide and cross in order group 860 to demoder 23.Then, when clock correction compensating unit 26 receives data EncC at that time, just can begin output data EncC to demoder 23 to carry out subsequent treatment.In this embodiment, processing unit 21 header that can receive complete data packet P2 is packaged into frame (data DataC, DataD, DataE, DataF).Therefore, correcting unit 41 carry out correction programs and the time after clock correction compensating unit 26 carries out compensation program, processing unit 21 can correctly receive data packet P2.
Fig. 9 shows that it is applicable to the universal serial bus device 40 that has first work clock among Fig. 5 according to the described a kind of bearing calibration of one embodiment of the invention.Simultaneously with reference to figure 5 and Fig. 9, at first, the serial bit data that electronic entity unit 24 receives from link partner 10, and generation is corresponding to a code-element string (step S902) of serial bit data, wherein link partner 10 has second work clock, and code-element string comprises a plurality of code elements arranged side by side.Then, correcting unit 41 receives the code element from electronic entity unit 24 in regular turn, and judges whether the code element that is received is the quantity (step S904) of crossing over the leap code element of code element and counting reception.Then, judging next code element after crossing over code element when correcting unit 41 is that value that non-leap code element and counter 42 are counted is when being odd number (for example 1,3,5,7 etc.), correcting unit 41 can next non-leap code element replaces to the leap code element with this, and counter 42 reset to 0, with the quantity (step S906) of the leap code element of counting follow-up reception again.Then, when the difference on the frequency between first work clock and second work clock is excessive, the time clock correction compensating unit 26 can by adjust cross over code element quantity so that the code element from correcting unit 41 is carried out compensation program (step S908).Then, the code element that clock correction compensating unit 26 is provided during 23 pairs of demoders decode (step S910).Then, descrambler 22 can carry out descrambling to decoded data according to the seed that linear feedback shift register 25 is provided and provide descrambling data to processing unit 21 to carry out subsequent treatment, wherein whether more linear feedback shift register 25 can determine new seed (step S912) according to decoded data.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (12)
1. a universal serial bus device has first work clock, in order to receive the data from link partner, comprising:
Electronic entity unit is coupled to above-mentioned link partner via cable, comes from the serial bit data of above-mentioned link partner in order to reception, and produces the code-element string corresponding to above-mentioned serial bit data, and wherein above-mentioned code-element string comprises a plurality of code elements; And
Correcting unit, be coupled to above-mentioned electronic entity unit, in order to receive above-mentioned code-element string, to judge whether each the above-mentioned code element in the above-mentioned code-element string that is received is the quantity of the above-mentioned first kind code element of first kind code element and counting reception, wherein when the quantity of counting be that odd number and the next above-mentioned code element that is received are when being the second type code element, the above-mentioned code element that the above-mentioned next one received is replaced with above-mentioned first kind code element, and wherein above-mentioned first kind code element is for crossing over code element.
2. universal serial bus device according to claim 1 also comprises:
Demoder will be in order to becoming decoded data from the above-mentioned symbol decoding of above-mentioned correcting unit; And
Descrambler, in order to according to a seed above-mentioned decoded data is carried out descrambling, above-mentioned descrambler comprises:
Linear feedback shift register, in order to above-mentioned seed to be provided, wherein when above-mentioned decoded data be during corresponding to the above-mentioned second type code element, above-mentioned linear feedback shift register upgrades above-mentioned seed according to specific tabling look-up.
3. universal serial bus device according to claim 2, wherein when above-mentioned decoded data be during corresponding to above-mentioned first kind code element, above-mentioned linear feedback shift register stops to upgrade above-mentioned seed.
4. universal serial bus device according to claim 2, wherein when above-mentioned decoded data be when being calibration symbols corresponding to the above-mentioned second type code element and the above-mentioned second type code element, the above-mentioned seed of above-mentioned linear feedback shift register initialization, wherein above-mentioned link partner comprises scrambler, and above-mentioned link partner transmits above-mentioned calibration symbols with the linear feedback shift register of synchronous above-mentioned scrambler and the above-mentioned linear feedback shift register of above-mentioned descrambler.
5. universal serial bus device according to claim 2 also comprises:
The time clock correction compensating unit, be coupled between above-mentioned correcting unit and the above-mentioned demoder, in order to adjust the quantity of above-mentioned first kind code element, with the difference on the frequency between second work clock that compensates above-mentioned first work clock and above-mentioned link partner, wherein when the frequency of above-mentioned first work clock during greater than the frequency of above-mentioned second work clock, to compensate said frequencies by the quantity that increases above-mentioned first kind code element poor for the clock correction compensating unit when above-mentioned, and when the frequency of above-mentioned first work clock during less than the frequency of above-mentioned second work clock, to compensate said frequencies by the quantity that reduces above-mentioned first kind code element poor for the clock correction compensating unit when above-mentioned.
6. universal serial bus device according to claim 1, wherein above-mentioned correcting unit comprises counter, quantity in order to the above-mentioned first kind code element of counting continuous reception, wherein when above-mentioned code element that the above-mentioned next one received was replaced by above-mentioned first kind code element, above-mentioned correcting unit was reset above-mentioned counter.
7. a bearing calibration is applicable to the universal serial bus device with first work clock, and above-mentioned bearing calibration comprises:
Reception is from the serial bit data of link partner, and produces the code-element string corresponding to above-mentioned serial bit data, and wherein above-mentioned code-element string comprises a plurality of code elements; And
Receive above-mentioned code-element string and judge whether each the above-mentioned code element in the above-mentioned code-element string is the quantity of the above-mentioned first kind code element of first kind code element and counting reception, and wherein above-mentioned first kind code element is for crossing over code element;
When the quantity of counting is odd number and the next above-mentioned code element that is received when being the second type code element, the above-mentioned code element that the above-mentioned next one received is replaced with above-mentioned first kind code element.
8. bearing calibration according to claim 7 also comprises:
Above-mentioned symbol decoding is become decoded data; And
According to a seed above-mentioned decoded data is carried out descrambling.
9. bearing calibration according to claim 8 is wherein above-mentionedly carried out the step of descrambling according to above-mentioned seed to above-mentioned decoded data, also comprises:
When above-mentioned decoded data is during corresponding to the above-mentioned second type code element, upgrade above-mentioned seed according to specific tabling look-up; And
When above-mentioned decoded data is during corresponding to above-mentioned first kind code element, stop to upgrade above-mentioned seed.
10. bearing calibration according to claim 9 is wherein above-mentionedly carried out the step of descrambling according to above-mentioned seed to above-mentioned decoded data, also comprises:
When above-mentioned decoded data is when being calibration symbols corresponding to the above-mentioned second type code element and the above-mentioned second type code element, the above-mentioned seed of initialization.
11. bearing calibration according to claim 8 also comprises:
The quantity of adjusting above-mentioned first kind code element is with the difference on the frequency between second work clock that compensates above-mentioned first work clock and above-mentioned link partner;
When the frequency of above-mentioned first work clock during greater than the frequency of above-mentioned second work clock, it is poor that the quantity that increases above-mentioned first kind code element compensates said frequencies; And
When the frequency of above-mentioned first work clock during less than the frequency of above-mentioned second work clock, it is poor that the quantity that reduces above-mentioned first kind code element compensates said frequencies.
12. bearing calibration according to claim 7, the step of the above-mentioned first kind code element that wherein above-mentioned counting receives also comprises the quantity of the above-mentioned first kind code element that counting receives continuously, wherein when above-mentioned code element that the above-mentioned next one received is replaced by above-mentioned first kind code element, the quantity of the above-mentioned first kind code element that receives of counting again.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104052587A (en) * | 2013-03-12 | 2014-09-17 | Nxp股份有限公司 | Clock synchronization in an RFID equipped device |
| CN104537319A (en) * | 2014-12-22 | 2015-04-22 | 昆腾微电子股份有限公司 | Device and method for scrambling and descrambling buses and integrated circuit chip |
| CN107209743A (en) * | 2015-02-06 | 2017-09-26 | 高通股份有限公司 | The reception clock alignment of universal serial bus |
| US11349626B1 (en) * | 2019-07-08 | 2022-05-31 | Astera Labs, Inc. | Retimer with path-coordinated flow-rate compensation |
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| TWI548212B (en) * | 2014-12-16 | 2016-09-01 | 原相科技股份有限公司 | Circuit calibrating method and circuit calibrating system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104052587A (en) * | 2013-03-12 | 2014-09-17 | Nxp股份有限公司 | Clock synchronization in an RFID equipped device |
| US9727767B2 (en) | 2013-03-12 | 2017-08-08 | Nxp B.V. | Clock synchronization in an RFID equipped device |
| CN104052587B (en) * | 2013-03-12 | 2017-09-12 | Nxp股份有限公司 | Clock in RFID device is equipped with is synchronous |
| CN104537319A (en) * | 2014-12-22 | 2015-04-22 | 昆腾微电子股份有限公司 | Device and method for scrambling and descrambling buses and integrated circuit chip |
| CN107209743A (en) * | 2015-02-06 | 2017-09-26 | 高通股份有限公司 | The reception clock alignment of universal serial bus |
| US11349626B1 (en) * | 2019-07-08 | 2022-05-31 | Astera Labs, Inc. | Retimer with path-coordinated flow-rate compensation |
| US11949629B1 (en) | 2019-07-08 | 2024-04-02 | Astera Labs, Inc. | Retimer with path-coordinated flow-rate compensation |
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| CN101667167B (en) | 2011-05-11 |
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Effective date of registration: 20200622 Address after: Chinese Taiwan New Taipei City Patentee after: VIA LABS Inc. Address before: Taiwan County, Taipei, China Patentee before: Via Technologies, Inc. |