CN101661906A

CN101661906A - Manufacturing method of nonvolatile storage cell

Info

Publication number: CN101661906A
Application number: CN200810212502A
Authority: CN
Inventors: 陈宜秀; 李永忠; 吴怡德
Original assignee: Eon Silicon Solutions Inc
Current assignee: Eon Silicon Solutions Inc
Priority date: 2008-08-29
Filing date: 2008-08-29
Publication date: 2010-03-03

Abstract

The invention relates to a manufacturing method of a nonvolatile storage cell, in particular to a method for manufacturing a gate electrode by utilizing self-aligned metal silicide. The self-aligned metal silicide is used as a connecting layer of a polycrystalline silicon gate electrode to replace a known tungsten metal layer so as to reduce the application of a mask manufacturing technology in the step and achieve the purposes of simplifying manufacturing processes simplification and reducing the cost, and meanwhile, the resistance deflection caused by the oxidation of the tungsten metal layer can be avoided.

Description

The manufacture method of non-volatile memory cells

Technical field

The invention relates to a kind of manufacture method of non-volatile memory cells, be meant a kind of manufacture method of in the manufacturing of gate electrode, using self-aligned metal silicate especially.

Background technology

In semiconductor applications, non-volatile memories still can be retained after outage owing to having the data that deposit in, the little power consumption of volume is low, reusable advantage, therefore be used in the digital camera storage widely, in a large amount of appliance and electronic such as mobile phone and personal computer, in typical non-volatile memories, be to use the control grid electrode of making by polysilicon (control gate) and have silicon-silica-silicon-nitride and silicon oxide-silicon (silicon-oxide-nitride-oxide-silicon simultaneously, SONOS) Gou Zao assembly is used as channel hot electron and injects and to write data and hot hole injects the control assembly that removes data, it is to be stacked in regular turn on the silicon substrate, and with the source of the silicon nitride layer in the middle of the silica interlayer as the electric charge acquisition, the silica of levels is then respectively as the usefulness of isolation layer and tunneling layer, because this structure can be by silica-silicon-nitride and silicon oxide layer (oxide-nitride-oxide, ONO) replace floating gate (floating gate), therefore can effectively reduce the use and the minification of mask in the manufacturing process.

In the gate electrode structure of the memory cell of this kind non-volatile memories; for the sheet resistance (sheet resistance) that reduces polygate electrodes; and the resistance value between each contact point of electrode; usually can on the grid of polysilicon, further form the layer of metal layer; to improve its higher resistance value; in the known practice; mainly above polygate electrodes, further cover a tungsten metal level; reach aforesaid purpose; in TaiWan, China patent announcement I287834 number; promptly disclose a kind of prior art that on polygate electrodes, further forms a tungsten metal level; yet; use this tungsten metal level as the cover layer on the polygate electrodes; has shortcoming apt to deteriorate and that fabrication schedule is complicated; because of this tungsten metal in the deposition after; must cover silicon nitride layer rapidly; go bad to avoid producing; simultaneously; during the silicon nitride layer that covers removing; also must use mask that polygate electrodes and other pattern etching are come out in addition; therefore on simplified manufacturing process and cost consideration, all cause disadvantageous burden.

For the shortcoming in the gate electrode structure manufacturing that improves this non-volatile memories memory cell, purpose of the present invention, mainly being that proposition is a kind of can replace the manufacture method that further covers the tungsten metal level in the prior art on polygate electrodes, and it can solve effectively and use the tungsten metal level to improve and the manufacturing process complicated problems as the cost that cover layer caused on the polygate electrodes.

Summary of the invention

In order to solve aforesaid technical problem, promptly improve the shortcoming of the textural fabrication schedule of gate electrode of this non-volatile memory cells, purpose of the present invention mainly is to propose a kind of can the replacement in the prior art using the tungsten metal level as the tectal manufacture method on the polygate electrodes on the polygate electrodes, it is to utilize the self-aligned metal silicate layer to replace known tungsten metal level, can avoid the spoilage problems of using the tungsten metal level to be produced effectively because of follow-up high annealing manufacturing process, reduced the use of mask when this polygate electrodes upper caldding layer of etching, simultaneously can further simplify the manufacture process of this step, and reduce production costs.

The present invention is the cover layer that utilizes a kind of self aligned metal silicide to make, and it is the manufacturing step that comprises as following:

Clean with the silica of acid solution earlier, to remove its surperficial formed original oxide layer (native oxide) the silicon composition surface of institute's pre-reaction;

Utilizing sputter or chemical vaporization mode is that the metal level of 30 to 200 dusts is formed on above-mentioned polygate electrodes, source electrode and drain region and other zone with thickness;

Further forming a thickness again on the aforementioned metal layer is the barrier layer of 50 to 250 dusts, does not contact with extraneous air when metal silicide reacts to protect aforesaid metal level and silicon substrate to form;

Heat treatment is for the first time handled with the high temperature between 250 to 700 ℃ in the metal level and the barrier layer of aforementioned formation, make the reaction of metal level and silicon substrate and the formation metal silicide;

Utilize wet etching to remove metal level and barrier layer that unreacted becomes metal silicide, and form the self-aligned metal silicate layer that is covered in polygate electrodes and source electrode and drain region; And

Temperature with 500 to 900 ℃ is carried out the heat treatment second time, makes the metal suicide structure of the inside formation inversion of phases of metal silicide, can effectively reduce the resistance of metal silicide.

Self aligned metal silicide described in the present invention, be meant and the special metal layer be covered on silicon substrate and other material (as silicon nitride), owing to only can partly reacting with silicon substrate, this metal level generates metal silicide after heat treated, and the metal level that is covered on other material (as silicon nitride) will can not produce any variation, therefore can reach and have the function that selectivity covers, simultaneously when carrying out reacted wet etching, only remove the unreacted metal layer by etching liquid and keep the part that the reaction back generates metal silicide, reach covering effect with regioselectivity, promptly, must be again not define the zone that institute's desire covers with mask in addition, its be the present invention alleged can self aligned effect.

Being used for described in the present invention carried out the formed metal level of autoregistration, its material does not limit especially, being meant can be by reacting the metal material of reaching the selective reaction effect with different substrate materials, and the composition of its metal level is preferably cobalt, titanium, platinum, tantalum, is more preferred from cobalt.

Being used for described in the present invention removed the acid solution of original oxide layer, and its composition does not limit especially, is preferably inorganic acid, is more preferred from hydrofluoric acid.

The method of metal level on deposit spathic silicon gate electrode, source electrode and the drain region described in the present invention, the electricity that can be physical property is starched sputter or chemical vaporization, and the thickness of metal film that it deposited is preferably 30 to 200 dusts, is more preferred from 50 to 180 dusts.

The method of deposited barrier layer on the metal level described in the present invention is the electricity slurry sputter or the chemical vaporization of physical property, and the barrier film thickness that it deposited is preferably 50 to 250 dusts, is more preferred from 80 to 220 dusts, and the composition on its barrier layer can be titanium nitride (TiN).

The heat-treating methods first time described in the present invention, be meant that the metal level that will be deposited on polygate electrodes, source electrode and the drain region is with rapid thermal treatment method (rapid thermal process, RTP) carry out thermal response, make the reaction of metal level and silicon substrate and form metal silicide, unreacted portion is then remained stationary, its reaction temperature is preferable between 250 to 700 ℃, be more preferred between 300 ℃ to 600 ℃, its formed metal silicide can be cobalt silicide, titanium silicide, platinum silicide or tantalum silicide.

Remove described in the present invention unreacted become metal silicide wet etching, its etching liquid can be strong acid or highly basic, is preferably hydrofluoric acid or potassium hydroxide.

The heat-treating methods second time described in the present invention, be meant that the metal level that will be deposited on polygate electrodes, source electrode and the drain region is with rapid thermal treatment method (rapid thermal process, RTP) carry out thermal response, make the metal suicide structure of the inside formation inversion of phases of metal silicide, to reduce the resistance of metal silicide, its reaction temperature is preferable between 500 to 900 ℃, be more preferred between 550 ℃ to 850 ℃, its formed metal silicide can be cobalt silicide, titanium silicide, platinum silicide or tantalum silicide.

Description of drawings

Fig. 1 (a) and Fig. 1 (b) are respectively the top view and the X-axis profile of the silicon substrate that forms metal wire and groove.

Fig. 2 (a) and Fig. 2 (b) are respectively top view and the X-axis profile that forms ONO structure and polygate electrodes layer on metal wire and the groove.

Fig. 3 (a), Fig. 3 (b) and Fig. 3 (c) are respectively the top view that is covered in tungsten metal level on the polygate electrodes, Y-axis profile and the X-axis profile of known technology.

Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c) are respectively top view, Y-axis profile and the X-axis profile that is covered in self-aligned metal silicate layer on the polygate electrodes of the present invention.

Drawing reference numeral:

10 silicon substrates (silicon wafer)

11 metal wires

12 grooves

21 silica tunneling layers

22 silicon nitride electric charges acquisition layer

23 silica isolation layers

24 polysilicon electric grid layers

31 tungsten metal levels

41 silicon cobalt substrates

Embodiment

For making your auditor understand purpose of the present invention, feature and effect, now by following specific embodiment, and cooperate appended graphicly, the present invention is described in detail, illustrate as the back:

The gate electrode preparation method:

Shown in Fig. 1 (a) and Fig. 1 (b), on silicon substrate (silicon wafer) 10, utilize etching and deposition manufacturing process to depict metal wire 11 and groove 12, wherein this metal wire 11 is made by aluminium, groove 12 parts then are to fill silica as insulating barrier.

Shown in Fig. 2 (a) and Fig. 2 (b), on silicon substrate 10, form silica tunneling layer 21, silicon nitride electric charge acquisition layer 22 in regular turn in regular turn, silica isolation layer 23 and polysilicon electric grid layer 24.

In known technology; be to utilize tungsten metal level 31 to be deposited on polygate electrodes 24 and source electrode and the drain region (figure does not show); its result is as Fig. 3 (a); shown in Fig. 3 (b) and Fig. 3 (c); must on tungsten metal level 31, deposit the protective layer and the photoresist layer (figure does not show) of one deck silicon nitride separately; expose again; develop; and etch needed figure; yet in the present invention; then be as Fig. 4 (a); shown in Fig. 4 (b) and Fig. 4 (c); directly deposit thickness is the cobalt metal level of 50 to 180 dusts in polygate electrodes and source electrode and drain electrode; cover the barrier layer that a layer thickness is the titanium nitride of 80 to 220 dusts again; after finishing deposition; carry out the heat treatment first time; it is with rapid thermal treatment method (rapid thermal process; RTP) make the reaction of metal level and silicon substrate form the thermal response of metal silicide; its reaction temperature is between 300 ℃ to 600 ℃; after heat treatment for the first time, then make original cobalt metal level and polygate electrodes form silicon cobalt substrate 41 (COSi ₂), it is the autoregistration metal level, afterwards, re-use wet etching and do not remove cobalt metal level with silicon substrate reaction becoming metal silicide, its employed etching liquid is a hydrofluoric acid, after finishing be shown in Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c), become autoregistration and be covered in silicon cobalt substrate on the gate electrode, then carry out the heat treatment second time again, with high temperature between 550 ℃ to 850 ℃ the inside of metal silicide is formed the metal suicide structure of inversion of phases, to lower the resistance of metal silicide by this.

Utilize the non-volatile memories of above-mentioned manufacture process manufacturing, in the manufacturing of polygate electrodes, can have as following advantage:

One, by in the non-volatile memories manufacturing process, using the self-aligned metal silicate layer to replace known tungsten metal level, can avoid the spoilage problems of using the tungsten metal level to be produced effectively because of follow-up high annealing manufacturing process.

Two, can reduce the use of mask when this polygate electrodes upper caldding layer of etching, can simplify the manufacture process of this step, and reduce production costs.

Though the present invention discloses as above with a preferred embodiment, is not in order to limit scope of the invention process.Any related personnel who is familiar with this area; without departing from the spirit and scope of the present invention, when can doing a little change and retouching, promptly allly change and modify according to the equalization that the present invention did; should be protection scope of the present invention and contain, it defines and should be as the criterion with claims of the present invention.

Claims

1, a kind of manufacture method of non-volatile memory cells, it is characterized in that described method is to implement as following manufacturing step on it at a silicon substrate that comprises an above memory cell, polygate electrodes, silica-silicon-nitride and silicon oxide layer structure, source electrode, drain electrode:

Remove surperficial formed original oxide layer with cleaning procedure;

Utilize sputter or chemical vaporization mode that metal level is formed on above-mentioned polygate electrodes, source electrode, drain region and other zone;

On described metal level, further form a barrier layer, do not contact during with the reaction of protection metal level and silicon substrate formation metal silicide with extraneous air;

Described metal level and barrier layer are carried out high temperature heat treatment for the first time, make the reaction of described metal level and silicon substrate and the formation metal silicide;

Utilize wet etching to remove unreacted metal layer and barrier layer, to form the self-aligned metal silicate layer; And

The self-aligned metal silicate layer is carried out the heat treatment second time, make the metal suicide structure of the inside formation inversion of phases of metal silicide.

2, manufacture method as claimed in claim 1 is characterized in that, described cleaning procedure is to use hydrofluoric acid.

3, manufacture method as claimed in claim 1 is characterized in that, described metal layer thickness is 30 to 200 dusts.

4, manufacture method as claimed in claim 1 is characterized in that, described metal level can be cobalt, titanium, platinum, tantalum metal layer.

5, manufacture method as claimed in claim 1 is characterized in that, described barrier layer thickness is 50 to 250 dusts.

6, manufacture method as claimed in claim 1 is characterized in that, described barrier layer is for being titanium nitride layer.

7, manufacture method as claimed in claim 1 is characterized in that, the described first time, heat treated reaction temperature was to be between 250 to 700 ℃.

8, manufacture method as claimed in claim 1 is characterized in that, described wet etching is to use hydrofluoric acid as etching liquid.

9, manufacture method as claimed in claim 1 is characterized in that, the described second time, heat treated reaction temperature was to be between 500 to 900 ℃.