CN101661704A - Color sequence time control circuit and correlative color sequence displayer system and method thereof - Google Patents
Color sequence time control circuit and correlative color sequence displayer system and method thereof Download PDFInfo
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- CN101661704A CN101661704A CN200910308078A CN200910308078A CN101661704A CN 101661704 A CN101661704 A CN 101661704A CN 200910308078 A CN200910308078 A CN 200910308078A CN 200910308078 A CN200910308078 A CN 200910308078A CN 101661704 A CN101661704 A CN 101661704A
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Abstract
The invention relates to a color sequence time control circuit and a correlative color sequence displayer system and a method thereof. A row-column data sorting unit in the color sequence time controlcircuit temporarily stores, sorts and outputs inputted pixels or sub pixels. The pixels or the sub pixels are sorted by a color data sorting unit according to a color sequence method or the color ofthe different sub pixels, so that a drive control unit writes the sorted sub pixels with different colors into a display faceplate in extreme short time difference to complete a full color picture. The row-column data sorting unit temporarily stores the pixels or the sub pixels in a matrix way, and reads the pixels or the sub pixels in parallel row by row correspondingly to the way of the matrix,wherein the pixels or the sub pixels are sorted and read in parallel according to the size of the matrix row and column and the numbers of brake cables started by a scan drive unit in the same time. The invention can still remain the correctness of the pixels sorting and the outputting when starting more than two brake cables in the scan drive unit.
Description
Technical field
The present invention relates to a kind of color sequence time control circuit and relevant color sequence displayer and method, refer to a kind of color sequence time control circuit and relevant color sequence displayer and method that uses many brake cables to open cooperation data ordering reading of data especially.
Background technology
The general display of look preface method that uses all can be equipped with a color sequence time control circuit, each self-contained sub-picture element of a plurality of picture elements superposition in the time of extremely lacking that single full-color picture was comprised is shown in the display panel of this LCD, in order to the demonstration of carrying out all picture elements in this full-color picture with the persistence of vision phenomenon of human eye.
See also Fig. 1, it is a kind of synoptic diagram of general color sequence displayer 100.As shown in Figure 1, color sequence displayer 100 is to comprise a color sequence time control circuit 110, a data-driven unit 120, one scan driver element 130, a display panel 140, a light emitting diode driver element 150, a backlight module 160, and two memory buffer 108 and 112.Display panel 140 is picture elements that data line that the sweep trace that driven according to scan drive cell 130 and data-driven unit 120 are driven decides its transistor that comprises to show.In order to implement look preface method, color sequence time control circuit 110 is to be used for time sequential routine of control data driver element 120 and scan drive cell 130, in extremely short different time the picture element of different colours is read in display panel 140.Color sequence time control circuit 110 is also controlled the sequential of the time sequential routine of light emitting diode driver element 150 with decision startup backlight module 160.
Color sequence time control circuit 110 is to comprise an input buffer storage 102, image ordering processing unit 104, a Drive and Control Circuit 106.Input buffer storage 102 is used for the outside is inputed to a synchronous signal dei, a picture element frequency pclk, and a plurality of picture elements of color sequence time control circuit 110, and 110 employed system frequency sclk do synchronous processing with color sequence time control circuit.Image ordering processing unit 104 is and memory buffer 108 and 112 operate together, the picture element output quantity that picture element in the single picture is cooperated the single brake cable that scan drive cell 130 only opens at one time, and rearrange according to the sub-picture element of different colours, with the red sub-picture element (in Fig. 1, representing) that this picture is comprised with block R, green sub-picture element (in Fig. 1, representing) with block G, and blue sub-picture element (in the 1st figure, representing) assisting by memory buffer 108 and 112 with block B, in different time and extremely short mistiming, read in driving control unit 106, and the full-color picture that driving control unit 106 is controlled on the display panel 140 according to this indirectly shows.
In order to improve the data transmission efficiency of color sequence displayer shown in Figure 1 100, can make scan drive cell 130 open the speed that many brake cables come speeding up data transmission simultaneously; Yet such way also very easily causes the confusion on data transfer sequence between many brake cables, and makes that the picture element data can't correct being reduced after being transmitted, thereby causes display panel 140 can't show correct picture element data.
Summary of the invention
The present invention discloses several color sequence time control circuits and relevant color sequence displayer system and image data ordering and read method, high data rate when opening many brake cables simultaneously with effective utilization, and reach the purpose that under the situation of opening many brake cables, still can keep the correctness of handling picture element arrangement and output.
The present invention discloses a kind of color sequence time control circuit that uses many brake cables to open cooperation data ordering reading of data, is applied to a color sequence displayer.This color sequence time control circuit comprises a raw column data sequencing unit and a color data sorting unit.This raw column data sequencing unit is to be used for keeping in and reading a plurality of picture elements.This raw column data sequencing unit is to comprise a ranks memory buffer and to insert ranking circuit.This ranks memory buffer is to be used for temporary these a plurality of picture elements of matrix-style.This insertion ranking circuit is to be used for being divided into a plurality of first five equilibriums according to these a plurality of picture elements that one first cutting number is kept in this ranks memory buffer, to read in parallel each self-contained picture element of arranging with matrix-style of these a plurality of first five equilibriums.This insertion ranking circuit and a plurality of picture elements that comprise according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read picture element in proper order to read according to a picture element in each second five equilibrium in regular turn.This color data sequencing unit is to be used for the color of this a plurality of each self-contained sub-picture elements of picture element of keeping in and reading according to this raw column data sequencing unit, should each self-contained sub-picture element of a plurality of picture elements is classified and sorts.This color sequence time control circuit is a sub-picture element of exporting a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture.This picture element that is used for reading in each second five equilibrium at this in regular turn picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a picture element read picture element.The quantity that these a plurality of C grades are divided is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
The present invention discloses a kind of color sequence displayer system that uses many brake cables to open cooperation data ordering reading of data.This color sequence displayer system comprises a raw column data sequencing unit and a color data sorting unit.This raw column data sequencing unit is to be contained in the host side that this color sequence displayer system is comprised, and is used for keeping in and reading a plurality of picture elements.This raw column data sequencing unit comprises a ranks memory buffer and and inserts ranking circuit.This ranks memory buffer is to be used for temporary these a plurality of picture elements.This insertion ranking circuit is to be used for being divided into a plurality of first five equilibriums according to these a plurality of picture elements that one first cutting number is kept in this ranks memory buffer, to read in parallel each self-contained picture element of arranging with matrix-style of these a plurality of first five equilibriums.This insertion ranking circuit and a plurality of picture elements that comprise according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read picture element in proper order to read according to a picture element in each second five equilibrium in regular turn.This color data sequencing unit is to be contained in the color sequence displayer that this color sequence displayer system is comprised, be used for the color of this a plurality of each self-contained sub-picture elements of picture element of keeping in and reading according to this raw column data sequencing unit, should each self-contained sub-picture element of a plurality of picture elements classified and sort.This color sequence displayer system exports the sub-picture element of a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture.This picture element that is used for reading in each second five equilibrium at this in regular turn picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a picture element read picture element.The quantity that these a plurality of C grades are divided is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
The present invention discloses a kind of color sequence time control circuit that uses many brake cables to open cooperation data ordering reading of data, is applied to a color sequence displayer.This color sequence time control circuit comprises a color data sorting unit and a raw column data sequencing unit.This color data sequencing unit is to be used for color according to a plurality of each self-contained sub-picture element of picture element, should each the self-contained sub-picture element classification of a plurality of picture elements and ordering the sub-picture element group that pluralizes, and each sub-picture element group is corresponding to different colors.This raw column data sequencing unit is temporary and read the sub-picture element of this plural number group with this color data sequencing unit of cause.This raw column data sequencing unit is to comprise a ranks memory buffer and to insert ranking circuit.This ranks memory buffer is to be used for a sub-picture element group of the sub-picture element of temporary this plural number group.This insertion ranking circuit is that the plural number picture element that the sub-picture element of this that be used for this ranks memory buffer keep in according to one first cutting number group is comprised is divided into a plurality of first five equilibriums, to read in parallel each self-contained sub-picture element with the matrix-style arrangement of these a plurality of first five equilibriums.A this insertion ranking circuit and a plural number picture element that comprises according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read sub-picture element in proper order to read according to a sub-picture element in each second five equilibrium in regular turn.This color sequence displayer is the sub-picture element group that exports a plurality of different colours that this raw column data sequencing unit read according to a mistiming, to produce a full-color picture.This sub-picture element that is used for reading in each second five equilibrium at this in regular turn sub-picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a sub-picture element read picture element.The quantity that these a plurality of C grades are divided is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
The present invention discloses a kind of color sequence time control circuit that uses many brake cables to open cooperation data ordering reading of data, is applied to a color sequence displayer.This color sequence time control circuit comprises a raw column data sequencing unit.This raw column data sequencing unit is to be used for temporary and to read the sub-picture element of the plural number group that is inputed to this color sequence time control circuit by the outside.This raw column data sequencing unit is to comprise a ranks memory buffer and to insert ranking circuit.This ranks memory buffer is a sub-picture element group that is used for that temporary these a plurality of sub-picture element groups corresponding to different colours are comprised.This insertion ranking circuit is that the plural number picture element that the sub-picture element of this that be used for this ranks memory buffer keep in according to one first cutting number group is comprised is divided into a plurality of first five equilibriums, to read in parallel each self-contained sub-picture element with the matrix-style arrangement of these a plurality of first five equilibriums.A this insertion ranking circuit and a plural number picture element that comprises according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read sub-picture element in proper order to read according to a sub-picture element in each second five equilibrium in regular turn.This color sequence time control circuit is to share the memory buffer that display card and this display card comprised with a host side.The sub-picture element of this plural number group be by this display card and this memory buffer with each the self-contained sub-picture element classification of a plurality of picture elements and sort produced.This color sequence displayer is the sub-picture element group that exports a plurality of different colours that this raw column data sequencing unit read according to a mistiming, to produce a full-color picture.This sub-picture element that is used for reading in each second five equilibrium at this in regular turn sub-picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a sub-picture element read picture element.The quantity that these a plurality of C grades are divided is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
The present invention discloses a kind of color sequence time control circuit that uses many brake cables to open cooperation data ordering reading of data, is applied to a color sequence displayer.This color sequence time control circuit comprises one and blendes together the raw column data sequencing unit.This blendes together the raw column data sequencing unit is to be used for temporary a plurality of picture elements, and is used for reading this a plurality of picture elements with the form of sub-picture element.This blendes together the raw column data sequencing unit is to comprise a color data sorting unit, a ranks memory buffer, and one insert ranking circuit.This color data sequencing unit is to be used for color according to this a plurality of each self-contained sub-picture element of picture element, and should each self-contained sub-picture element of a plurality of picture elements being classified and sort be plural individual sub-picture element group.The sub-picture element of each of the sub-picture element of this plural number group group is corresponding to different colors.This ranks memory buffer is to be used for the sub-picture element of temporary this plural number of matrix-style group.This insertion ranking circuit is to be used for the plural number picture element that a sub-picture element group of the sub-picture element of this plural number of this ranks memory buffer keep in according to one first cutting number group comprised to be divided into a plurality of first five equilibriums, to read in parallel each self-contained sub-picture element with the matrix-style arrangement of these a plurality of first five equilibriums.A this insertion ranking circuit and a plural number picture element that comprises according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read sub-picture element in proper order to read according to a sub-picture element in each second five equilibrium in regular turn.This color sequence time control circuit is the sub-picture element group that exports a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture.This sub-picture element that is used for reading in each second five equilibrium at this in regular turn sub-picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a sub-picture element read picture element.The quantity that these a plurality of C grades are divided is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
The present invention discloses a kind of image data ordering and read method that uses many brake cables to open cooperation data ordering reading of data on color sequence displayer.This method comprises a plurality of picture element elements that will be temporary in the ranks memory buffer that a color sequence displayer comprised according to one first cutting number and is divided into a plurality of first five equilibriums, reading in parallel each self-contained picture element element of these a plurality of first five equilibriums, and a plurality of picture element elements that each branch such as first of these a plurality of first five equilibriums comprises are to be arranged in this ranks memory buffer with matrix-style; And a plurality of picture element elements that comprise according to each first branch such as grade that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, to read a picture element element in each C grade branch that a plurality of C grades that this branch such as second grade comprises divide in regular turn simultaneously.The quantity that these a plurality of C grades that this branch such as second grade comprises are divided is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
The present invention discloses a kind of color sequence displayer system that uses many brake cables to open cooperation data ordering reading of data.This color sequence displayer system comprises a host side and a color sequence displayer.This host side is to comprise a display card.This display card is to comprise a color data sorting unit, a raw column data sequencing unit, an and memory buffer.This color data sequencing unit is to be used for color according to a plurality of each self-contained sub-picture element of picture element, should each self-contained sub-picture element of a plurality of picture elements is classified and sorts.This raw column data sequencing unit is to be used for keeping in and reading these a plurality of picture elements that this color data sequencing unit is classified and sorted.This ranks buffering sequencing unit is to comprise a ranks memory buffer and to insert ranking circuit.This ranks memory buffer is to be used for temporary these a plurality of picture elements.This insertion ranking circuit is to be used for being divided into a plurality of first five equilibriums according to these a plurality of picture elements that one first cutting number is kept in this ranks memory buffer, to read in parallel each self-contained picture element of arranging with matrix-style of these a plurality of first five equilibriums.This insertion ranking circuit and a plurality of picture elements that comprise according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read picture element in proper order to read according to a picture element in each second five equilibrium in regular turn.This memory buffer is the buffer cell when being used for being used as this color data sequencing unit and this raw column data sequencing unit and classifying with ordering to these a plurality of picture elements.This color sequence displayer is to comprise an input buffer storage and a driving control unit.This input buffer storage is to receive these a plurality of picture elements that it is kept in and reads with this raw column data sequencing unit of cause, the outside is inputed to a synchronous signal of this color sequence displayer, one picture element frequency, and these a plurality of picture elements, one of using with this color sequence displayer is that the system frequency is done synchronous processing, this driving control unit is to be used for producing the control data-driven unit that this color sequence displayer comprised according to this sync signal and this system frequency, the one scan driver element, and the sequential of a LED driving circuit, and control this data-driven unit and this scan drive cell shows this full-color picture that is produced on the display panel that this color sequence displayer comprised according to the sub-picture element of this different colours that this color sequence time control circuit is exported.This color sequence displayer is a sub-picture element of exporting a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture.This picture element that is used for reading in each second five equilibrium at this in regular turn picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a picture element read picture element, and the quantity of should a plurality of C grades dividing is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.This color sequence displayer is to share this display card and this memory buffer with this host side.
Description of drawings
Fig. 1 is a kind of synoptic diagram of general color sequence displayer.
Fig. 2 is according to one first embodiment of the present invention, the synoptic diagram of a disclosed color sequence displayer.
Fig. 3 is the synoptic diagram of raw column data sequencing unit shown in Figure 2.
Fig. 4 is ranks memory buffer and the insertion picture element arrangement mode that ranking circuit carried out among diagram the 3rd figure.
Fig. 5 is the synoptic diagram according to the one second disclosed sequence displayer system of the same colour of embodiment of the present invention, and wherein the raw column data processing unit is a host side that is contained in the color sequence displayer system.
Fig. 6 is the synoptic diagram for the disclosed color sequence displayer of one the 3rd embodiment according to the present invention.
Fig. 7 and Fig. 8 are simple synoptic diagram temporary for the employed sub-picture element of raw column data sequencing unit shown in Figure 6, that sort, reach the way of output.
Fig. 9 is the synoptic diagram according to the disclosed color sequence displayer of one the 4th embodiment of the present invention, and wherein this color sequence displayer is to share the memory buffer that display card and this display card comprised with a host side in the external world.
Figure 10 is the synoptic diagram according to the disclosed color sequence displayer of one the 5th embodiment of the present invention, and wherein one to blend together the raw column data sequencing unit be to be used for replacing color data sorting unit and raw column data sequencing unit.
Figure 11 is the synoptic diagram that blendes together the raw column data sequencing unit shown in Figure 10.
Figure 12 is temporary for picture element/sub-picture element of being carried out on the ranks memory buffer according to the present invention, ordering, and the way of output, the synoptic diagram of the disclosed image data ordering of using many brake cables to open on color sequence displayer to cooperate the data ordering reading of data and read method.
[primary clustering symbol description]
| 100、200、320、400、500、600 | |
| 102 | |
| 104 | Image |
| 106 | Driving control unit |
| 108、112、530 | |
| 110、250、350、450、550、650 | Color sequence |
| 120 | The data-driven |
| 130 | Scan |
| 140 | |
| 150 | The light emitting |
| 160 | |
| 201、202、203、204、205、206 | The capable data of |
| 210 | The raw column |
| 220 | The color |
| 230 | The |
| 240 | |
| 300 | The color |
| 301、302、303、304、305、306、601、602 、603、604、605、606 | The capable data of |
| 310 | |
| 320 | |
| 330 | |
| 340 | |
| 510 | |
| 610 | Blend together the raw column |
| 702、704、706、708、710、712 | Step |
| P1，1、P1，2、P1，3、P1，4、P1，5、P1，6、 P2，1、P2，2、P2，3、P2，4、P2，5、P2，6、… 、P640，1、P640，2、P640，3、P640，4、 P640，5、P640，6、P641，1、P641，2、P641，3 、P641，4、P641，5、P641，6、…、P1280，1 、P1280，2、P1280，3、P1280，4、P1280，5、 P1280，6 | Picture element |
| R1，1、R1，2、R1，3、R1，4、R1，5、R1，6、 R2，1、R2，2、R2，3、R2，4、R2，5、R2，6、… 、R640，1、R640，2、R640，3、R640，4、 R640，5、R640，6、R641，1、R641，2、R641，3 、R641，4、R641，5、R641，6、…、R1280，1 、R1280，2、R1280，3、R1280，4、R1280，5、 R1280，6 | Sub-picture element |
Embodiment
In the middle of instructions and follow-up claim, used some vocabulary to censure specific assembly.The person with usual knowledge in their respective areas should understand, and same assembly may be called with different nouns by manufacturer.This instructions and follow-up claim are not used as distinguishing the mode of assembly with the difference of title, but the benchmark that is used as distinguishing with the difference of assembly on function.Be to be an open term mentioned " comprising " in the middle of instructions and the follow-up request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " electric connection " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be electrically connected at one second device, then represent this first device can be directly connected in this second device, or be connected to this second device indirectly through other device or connection means if describe one first device in the literary composition.
In order further to improve the usefulness of above-mentioned general color sequence displayer, the present invention discloses a kind ofly to use many brake cables to open to cooperate the data ordering reading of data and be used for the color sequence time control circuit of color sequence displayer and relevant color sequence displayer sorts and read method with image data.In the disclosed color sequence time control circuit of the present invention, mainly be that the processing of when opening many brake cables at the same time at general color sequence time control circuit the picture element data being carried out proposes a kind of improved picture element ordering and reads mode, even make the interior at one time brake cable of opening more than two of scan drive cell, picture element still can be by correct reading, and unlikely causing makes the full-color picture that superposition produced on display panel afterwards wrong problem occur when opening many brake cables simultaneously in the prior art.
See also Fig. 2, it is according to one first embodiment of the present invention, the synoptic diagram of a disclosed color sequence displayer 200.As shown in Figure 2, color sequence displayer 200 has comprised color sequence displayer 100 most assemblies among the 1st figure, but the image that comprised in the original color sequence time control circuit 110 ordering processing unit 104 is substituted with a raw column data sequencing unit (Line Data SortingUnit) 210 and one color data sorting unit 220, and make that color sequence time control circuit 110 substitutes with color sequence time control circuit 250 at this among Fig. 1.Raw column data sequencing unit 210 mainly is to be used for a plurality of picture elements that input buffer storage 102 is received are kept in and read.Color data sequencing unit 220 is used for the color of this a plurality of each self-contained sub-picture elements of picture element of keeping in and reading according to raw column data sequencing unit 210, should each self-contained sub-picture element of a plurality of picture elements be classified and sorted, and assisting by memory buffer 108 and 112, make the sub-picture element of a plurality of different colours that color sequence time control circuit 250 can be classified according to an extremely short mistiming output color data sequencing unit 220 and correct according to this generation one full-color picture.
The detailed structure of raw column data sequencing unit 210 and picture element arrangement mode are to be exposed in Fig. 3 and Fig. 4.See also Fig. 3, it is the synoptic diagram of raw column data sequencing unit 210 shown in Figure 2.As shown in Figure 3, raw column data sequencing unit 210 is to comprise a ranks memory buffer (Line Buffer) 230 and to insert ranking circuit (Insertion Sorting Circuit) 240.Ranks memory buffer 230 is to be used for the temporary a plurality of picture elements that come by input buffer storage 102 transmission of matrix-style.Inserting ranking circuit 240 is used for the picture element that ranks memory buffer 230 is kept in matrix-style is carried out data ordering and reads the picture element that is arranged to color data sequencing unit 220.The picture element arrangement mode that ranks memory buffer 230 and insertion ranking circuit 240 are carried out is to be exposed in Fig. 4, and wherein the picture element arrangement mode of Fig. 4 is with its notion of expression matrix.
See also Fig. 3 and Fig. 4.The picture element data are that (Line by Line) is read to ranks memory buffer 230 by input buffer storage 102 line by line, that is the capable data 206 of capable data 201 to the 6th row picture elements of the first row picture element shown in Fig. 3, and arrangement picture element arrangement mode as shown in Figure 4; The number that note that the capable data of single row picture element that raw column data sequencing unit 210 is once read in is not defined to described six of Fig. 3, and visual its number of various change of circumstance; In addition, when raw column data sequencing unit 210 ranks memory buffer 230 shared spaces are write finish after (be meant at this write completely single row behind totally six picture element line data), the ordering of the picture element that all picture element line data that can begin to carry out ranks memory buffer 230 is kept in comprise.For indicate picture element between with the sortord of expression matrix notion, in Fig. 4, each is read into the picture element of ranks memory buffer 230 all can be by additional numbers; For instance, the 4th figure numbers P1,1, P2,1, P3,1 ..., P1280,1 picture element is the capable data 201 of the first row picture element in the representative graph 3, numbering P1,2, P2,2 ..., P1280,2 picture element is the capable data 202 of the secondary series picture element in the representative graph 3, numbering P1,6, P2,6 ..., P1280,6 picture element is the capable data 206 of the 6th row picture element in the representative graph 3, and the picture element numbering that the capable data 203 of the 3rd row picture element shown in Figure 3, the capable data 204 of the 4th row picture element, the capable data 205 of the 5th row picture element are comprised is to add as shown in Figure 4 and no longer to give unnecessary details.Please note, Fig. 3 and capable data 201 to the 6th row picture element line data 206 of the first row picture element shown in Figure 4 for explanation data sorting mode used in the present invention institute icon, are not to be used for limiting the present invention at the data number that carries out once reading on the data sorting raw column data sequencing unit 210 only.
As shown in Figure 4, all picture elements that capable data 201 to the 6th row picture element line data 206 of the first row picture element are comprised are to be divided into two first five equilibriums (Equal Partition) 270 and 275, and after the described picture element way of output of Fig. 4 be the picture element that each branch such as first of parallel output comprises.For instance, picture element P1, the 1 and P641, the 1st, for being output simultaneously, and picture element P640, the 4 and P1280, the 4th, for being output simultaneously.Note that when above-mentioned all picture elements to be divided into timesharing such as two first grades, 2 can be regarded as the value of one first cutting number, and this first cutting number need satisfy the condition of the quantity of aliquot all picture elements of being kept in ranks memory buffer 230; For instance, all picture element numbers that ranks memory buffer 230 is comprised among Fig. 4 are to be 1280*6=7680, and the value 2 of the first cutting number is to divide exactly in 7680.
Then observe first five equilibrium 270.In order to realize, need to be about to each first five equilibrium earlier and to be divided into a plurality of second five equilibriums, for example illustrated second five equilibrium 2701,2702 among Fig. 4, and 2703 according to one second cutting number to the reading in parallel of each first five equilibrium; Wherein second five equilibrium 2701 is to comprise picture element P1,1, P1,2, P1,3, P1,4, P1,5, P1,6, the second five equilibriums 2702 are to comprise picture element P2,1, P2,2, P2,3, P2,4, P2,5, P2,6, the second five equilibriums 2703 are to comprise picture element P640,1, P640,2, P640,3, P640,4, P640,5, P640,6.Observe Fig. 3 and Fig. 4 as can be known, first five equilibrium 270 be with 6 for this second the cutting number be cut into a plurality of second five equilibriums, and observe second five equilibrium 2701,2702,2703 as can be known, each second five equilibrium is to comprise the picture element that the capable data 206 of capable data 201 to the 6th row picture elements of the first row picture element shown in Figure 3 is comprised separately.Note that this second the cutting choosing of number only need consider that whether dividing exactly all picture element quantity that comprise in first five equilibrium that is cut gets final product; For instance, in the example of Fig. 4, the value 6 of the second cutting number is the quantity 640*6=3840 of dividing exactly all picture elements that comprised in first five equilibrium 270.
Then observe second five equilibrium 2701.The picture element way of output shown in Figure 4 is also successively reading with each second unit of being divided on the order except considering the reading in parallel of each first five equilibrium; For this reason, each branch such as second is regarded as cutting into a plurality of C grade branches again, and when carrying out this picture element and reading order, each C grade that can be comprised by this branch such as second grade in regular turn reads a picture element in dividing.Note that quantity that a plurality of C grades that comprised are divided is that the brake cable number of being opened at one time with scan drive cell 130 is consideration in single second five equilibrium.With situation shown in Figure 4 for instance, when scan drive cell 130 is set at one time when starting two sweep traces, the C grade branch that each second branch such as grade comprises is to be two, and second five equilibrium 2701 is to comprise two C grades to divide 27011 and 27012, wherein C grade divides 27011 to be to comprise picture element P1,1, P1,2, P1,3, and C grade divides 27012 to be to comprise picture element P1,4, P1,5, P1,6.
In Fig. 4, the picture element that the capable data of each row picture element is comprised is to be temporary in ranks memory buffer 230 in the two-dimensional matrix mode.If with picture element among Fig. 4 by P1,1 to P1,6 direction is considered as one first dimension of ranks memory buffer 230, and with picture element by P1,1 to P1280,1 direction is considered as one second dimension of ranks memory buffer 230, and then a plurality of picture elements of comprising of second five equilibrium of each shown in Fig. 4 are the one first dimension rows that are arranged in ranks memory buffer 230 along this first dimension, and each second five equilibrium is to arrange along this second dimension; Thus, first dimension row's size is the number of the picture element that comprises for this each second branch such as grade, and this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on the ranks memory buffer 230.First dimension and second dimension that note that said ranks memory buffer 230 are shown in the temporary concrete concept of unit for picture element among expression Fig. 4 with row or column in the matrix only.
When insertion ranking circuit 240 carries out picture element output according to this picture element way of output, can finish reading of particular column picture element line data by reading in each second five equilibrium in regular turn corresponding to the above-mentioned brake cable number of opening simultaneously (that is number that C grade is divided in this each second five equilibrium).Reading order for example with picture element shown in Figure 4, in first five equilibrium 270, is to read in second five equilibrium 2701 C grade earlier to divide the 27011 picture element P1 that comprise, 1, and read in second five equilibrium 2701 C grade again and divide the 27012 picture element P1 that comprise, 4; Then inserting ranking circuit 240 is with picture element P2,1, P2,4, P3,1, P3,4 ..., P640,1, P640,4 order reads the part picture element that first five equilibrium 270 is comprised; In the same time, the picture element that first five equilibrium 275 is comprised is also with P641,1, P641,4, P642,1, P642,4 ... P1280,1, P1280,4 order is read, the picture element of win five equilibrium 270 and 275 each capable data 201 of the self-contained first row picture element and the 4th row picture element line data 204 is read in parallel finish, that is as the picture element output order of 210 icons of raw column data sequencing unit among Fig. 3.Then first five equilibrium 270 and 275 picture elements that comprised can be separately with capable data 202 of secondary series picture element and the 5th row picture element line data 205 read in parallel and the 3rd row picture element line data 203 and the 6th reading in parallel of row picture element line data 206 are finished; That is insert ranking circuit 240 meetings earlier with (P1,2, P1,5, P2,2, P2,5, P640,2, P640,5) with (P641,2, P641,5, P642,2, P642,5, P1280,2, P1280,5) picture element reads the picture element that sequential parallel reads first five equilibrium 270 and 275 capable data 202 of each self-contained secondary series picture element and the capable data 205 of the 5th row picture element, then again with (P1,3, P1,6, P2,3, P2,6, P640,3, P640,6) with (P641,3, P641,6, P642,3, P642,6, P1280,3, P1280,6) picture element reads the picture element that sequential parallel reads first five equilibrium 270 and 275 each capable data 203 of self-contained the 3rd row picture element and the capable data 206 of the 6th row picture element.Please note, be limited to illustrated length, the picture element that only illustrates first five equilibrium 270 and 275 each capable data 201 of the self-contained first row picture element and the 4th row picture element line data 204 among Fig. 3 and Fig. 4 reads order, but above-mentioned first five equilibrium 270 and 275 other row picture element line data that comprised read the order can significantly know by inference according to the diagram of Fig. 4 and above-mentioned explanation, so no longer in Fig. 4 separately icon with simplified.
Please note, shown in Fig. 3 and Fig. 4 first cuts number, the second cutting number, the brake cable number of opening simultaneously with the scan drive cell that decides the C grade branch number that is comprised in one second five equilibrium, the picture element number that the ranks memory buffer is held (size that comprises first dimension and second dimension in the above-mentioned ranks memory buffer 230), the capable data number of single row picture element that the ranks memory buffer is once read in, employed picture element reads sequential scheduling and all only is the employed variable of a preferred embodiment of the present invention in each C grade is divided, and can adopt other numerical value to above-mentioned each variable in other embodiments of the invention, as long as meet the above-mentioned condition that is used for limiting the rule of each variable; In other words, other embodiment that above-mentioned each parameter employing and Fig. 3 or different numerical value shown in Figure 4 are derived must be considered as category of the present invention.
Even note that in Fig. 4, the brake cable number that scan drive cell is opened simultaneously is to be 1, reading order at the picture element of first five equilibrium 270 still can P1,1, P2,1, ..., P640,1, P1,2, P2,2 ..., P640,2 ..., P640,6 order is carried out reading line by line, and still can finish correctly reading of picture element; Even, still can not influence running shown in Figure 4, and must be considered as one embodiment of the invention so the brake cable number that scan drive cell is opened simultaneously is reduced to 1.
Please consult Fig. 2 once more.When raw column data sequencing unit 210 is sorted picture element and is exported to color data sequencing unit 220 with Fig. 3 and mode shown in Figure 4 after, color data sequencing unit 220 can be divided into each picture element that is received its plural number picture element that comprises, and according to the difference of sub-picture element kind be temporary in memory buffer 108 or 112 one of them, for example according to red sub-picture element with single picture element comprised, green sub-picture element, blue sub-picture element is that prerequisite is temporary in memory buffer 108 or 112 illustrated block R to keep the putting in order of picture element that raw column data sequencing unit 210 exported respectively, block G, and block B; And color data sequencing unit 220 can be once more will before be temporary in memory buffer 108 or 112 one of them sub-picture elements of each color are that prerequisite is read in driving control unit 106 with the putting in order of picture element of keeping raw column data sequencing unit 210 equally and being exported the opportunity of needs afterwards, show with the full-color picture that carries out with look preface method on display panel 140 after carrying out.Please note, when memory buffer 108 and 112 one of them to carry out writing of sub-picture element fashionable, another one is to be used for carrying out reading of sub-picture element, and in other embodiments of the invention, color data sequencing unit 220 also can cooperate with more than one memory buffer and carries out the temporary of sub-picture element and write, and is not limited to two memory buffer 108 shown in the 2nd figure and 112.
See also Fig. 5, it is the synoptic diagram according to the disclosed sequence displayer system 300 of the same colour of one second embodiment of the present invention.Color sequence displayer system 300 comprises a host side 310 and a color sequence displayer 320.Color sequence displayer 320 is to comprise a color sequence time control circuit 350, memory buffer 108 and 112, data-driven unit 120, scan drive cell 130, display panel 140, light emitting diode driver element 150, and backlight module 160.Host side 310 is to comprise a primary processor 320, a chipset 330, an image engine 340, and raw column data processing unit 210.Primary processor 320, chipset 330, and image engine 340 be to be used for producing the required picture element of a complete picture, and the picture element that is produced is inputed to raw column data processing unit 210.The main difference place that disclosed this second embodiment of Fig. 5 and Fig. 2 disclose this first embodiment is that the raw column data sequencing unit 210 that is originally to be contained among Fig. 2 color sequence time control circuit 250 changes and is arranged on the host side 310, make picture element finish entering just to be sorted before the color sequence time control circuit 350, and color sequence time control circuit 350 only need carry out at the classification of the sub-picture element of variety classes and the sequential of controlling each driver element with correct enforcement look preface method and show full-color picture.The formation of other assembly is described similar or identical with Fig. 2 among Fig. 5, so do not given unnecessary details at this.
See also Fig. 6, Fig. 7, reach Fig. 8.Fig. 6 is the synoptic diagram for the disclosed color sequence displayer 400 of one the 3rd embodiment according to the present invention.The difference place of the color sequence displayer 200 shown in color sequence displayer 400 and the 2nd figure is in color sequence time control circuit 450, picture element that input buffer storage 102 is exported can be classified according to the sub-picture element of the variety classes that each picture element comprised by color data sequencing unit 220 earlier, and produces a plural number picture element module (for example a red sub-picture element module, a green sub-picture element module, and a blue sub-picture element module) and be input into raw column data sequencing unit 210; Therefore, in Fig. 3 and the situation difference that receives the picture element line data shown in Figure 4, raw column data sequencing unit 210 is received is to be the sub-picture element of above-mentioned plural number group, and represents in the mode of sub-picture element line data in Fig. 7 and Fig. 8.
Fig. 7 and Fig. 8 are simple synoptic diagram temporary for raw column data sequencing unit shown in Figure 6 210 employed sub-picture elements, that sort, reach the way of output.Temporary at the sub-picture element shown in Fig. 7 and Fig. 8, ordering, it is temporary to reach the way of output and Fig. 3 and the disclosed picture element of Fig. 4, ordering, and the way of output is identical, and difference only is that the data unit of handling changes sub-picture element into by picture element, and therefore handled sub-picture element is with R1 in Fig. 7 and Fig. 8,1, R1,2, R1,6, R2,1, R2,2, R2,6, R3,1, R3,2, R3,6, R640,1, R640,2, R640,6, R641,1, R641,2, R641,6, R1280,1, R1280,2, R1280,6 represent the sub-picture element of single kind, that is the plural number picture element that comprised of single sub-picture element group; In addition, the sub-picture element line data that is input into raw column data sequencing unit 210 is with capable data 401,402,403,404,405,406 representatives of sub-picture element.
See also Fig. 9, it is the synoptic diagram according to the disclosed color sequence displayer 500 of one the 4th embodiment of the present invention.As shown in Figure 9, color sequence displayer 500 is to share display cards 520 (Video Board) and a memory buffer 530 that this display card comprised with a host side 510, therefore picture element is categorized into the color data sequencing unit 220 that the process of the sub-picture element of different colours can be comprised by display card 520, raw column data sequencing unit 210, and assisting directly of memory buffer 530 finished, and make and to have classified and sort, and carry out the synchronous processing of necessity by color sequence time control circuit 550 to the picture element data of the sub-picture element of plural number group can be directly be input in the color sequence time control circuit 550 that color sequence displayer 500 comprised by display card 520.In addition, the sub-picture element that the raw column data sequencing unit 210 antithetical phrase picture elements that comprised at display card 520 carry out is kept in, sorts, is reached the way of output and Fig. 7 and shown in Figure 8 identical, so do not give unnecessary details in detail at this.
See also Figure 10, it is the synoptic diagram according to the disclosed color sequence displayer 600 of one the 5th embodiment of the present invention.Color sequence displayer 600 is in in the color sequence time control circuit 650 that it comprised with the difference of each embodiment before, one is blended together the function that raw column data sequencing unit 610 substitutes disclosed raw column data sequencing units 210 of each embodiment and color data sequencing unit 220 with what color sequence time control circuit 650 comprised.Please consult Figure 11 again.Figure 11 is the synoptic diagram that blendes together raw column data sequencing unit 610 shown in the 10th figure.As shown in figure 11, blending together the color data sequencing unit 220 that raw column data sequencing unit 610 comprised is the picture element line data 201 that receive several column, 202,203,204,205,206, and the picture element line data of each row is temporary in ranks memory buffer 230 in the mode that is divided into a plural number picture element line data, the capable data 601 of the first red sub-picture element shown in Figure 11 for example, the capable data 602 of the first green sub-picture element, the capable data 603 of the first blue sub-picture element, the capable data 604 of quatre dice picture element, the capable data 605 of the 4th green sub-picture element, the capable data 606 of the 4th green sub-picture element etc.Figure 11 is also simple and easy to illustrate the process that the capable data 601 of the first red sub-picture element and a quatre dice picture element line data 604 are carried out sub-picture element ordering and output with the sortord identical with Fig. 4 and Fig. 8.Above-mentioned with sub-picture element keep in, sort, and the process of output in embodiment before, to describe, so locate no longer to add to give unnecessary details.
See also Figure 12, it is temporary for picture element/sub-picture element of being carried out on the ranks memory buffer according to the present invention, ordering, and the way of output, the synoptic diagram of the disclosed image data ordering of using many brake cables to open on color sequence displayer to cooperate the data ordering reading of data and read method.As shown in figure 12, image data ordering of the present invention is to comprise following steps with read method:
Step 702: a plurality of picture element elements (Pixel Element) that will be temporary in the ranks memory buffer that a color sequence displayer comprised according to one first cutting number are divided into a plurality of first five equilibriums, reading in parallel each self-contained picture element element of these a plurality of first five equilibriums, and a plurality of picture element elements that each branch such as first of these a plurality of first five equilibriums comprises are to be arranged in this ranks memory buffer with matrix-style;
Step 704: a plurality of picture element elements of comprising of each first branch such as grade that will these a plurality of first five equilibriums according to one second cutting number are divided into a plurality of second five equilibriums, with read simultaneously in regular turn each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in a picture element element, the quantity of should a plurality of C grades dividing that wherein this branch such as second grade comprises is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer; When this picture element element is during for a picture element, execution in step 706; When this picture element element is during for a sub-picture element, execution in step 710;
Step 706:, should each self-contained sub-picture element of a plurality of picture element elements classified and sort according to the color of institute's this a plurality of each self-contained sub-picture elements of picture element element of keeping in and reading;
Step 708: according to the sub-picture element of mistiming output a plurality of different colours of classifying and sorting, to produce a full-color picture;
Step 710: according to the color of institute's this a plurality of each self-contained sub-picture elements of picture element element of keep in and reading, each self-contained sub-picture element of these a plurality of picture element elements being classified and sort is a plurality of sub-picture element groups corresponding to different colours;
Step 712: according to the sub-picture element group of mistiming output institute's this a plurality of different colours of classifying and sorting, to produce a full-color picture.
Step shown in Figure 12 is the summary for the method for the various embodiments described above of the present invention when carrying out the picture element ordering, so carries out reasonable combination and arranges other embodiment that is derived at each step shown in Figure 12, must be considered as category of the present invention.
The present invention discloses a kind of color sequence time control circuit and relevant color sequence displayer system and image data ordering and read method, by opening disclosed image data ordering of a plurality of gate lines and the present invention and read method simultaneously, the high data rate when opening many brake cables simultaneously except can effectively utilizing, the problem of the mistake of display panel on video data can't be reduced and be caused to the picture element data of also having avoided transmitting separately when opening many brake cables simultaneously in the prior art smoothly.In other words, ordering of disclosed color sequence time control circuit and image data and read method according to the present invention still can be kept when opening the brake cable more than two in the scan drive cell at the same time and handle that picture element is arranged and the correctness of output.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (25)
1. color sequence time control circuit, be applied to a color sequence displayer, it is characterized in that, this color sequence time control circuit (Color Sequential Timing Controlling Circuit) comprises: a raw column data sequencing unit (Line Data Sorting Unit), be used for keeping in and reading a plurality of picture elements, comprise: a ranks memory buffer is used for temporary these a plurality of picture elements of matrix-style; Reach one and insert ranking circuit (Insertion Sorting Circuit), be used for being divided into a plurality of first five equilibriums (Equal Partition) according to these a plurality of picture elements that one first cutting number is kept in this ranks memory buffer, to read in parallel each self-contained picture element of arranging with matrix-style of these a plurality of first five equilibriums, this insertion ranking circuit and a plurality of picture elements that comprise according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read picture element in proper order to read according to a picture element in each second five equilibrium in regular turn; And a color data sorting unit, be used for the color of this a plurality of each self-contained sub-picture elements of picture element of keeping in and reading according to this raw column data sequencing unit, should each self-contained sub-picture element of a plurality of picture elements be classified and sorted;
Wherein this color sequence time control circuit is a sub-picture element of exporting a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture;
This picture element that wherein is used for reading in each second five equilibrium at this in regular turn picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a picture element read picture element, and the quantity of should a plurality of C grades dividing is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
2. color sequence time control circuit according to claim 1 is characterized in that:
Wherein this ranks memory buffer is with temporary these a plurality of picture elements of two-dimensional approach;
Wherein a plurality of picture elements of comprising of each second five equilibrium of these a plurality of second five equilibriums are that one first dimension along this ranks memory buffer is temporary in the one first dimension row (Dimensional Line) in this ranks memory buffer, the a plurality of picture elements that make this each second five equilibrium comprise are that the mode of a plurality of elements of being comprised with this first dimension row is temporary in this ranks memory buffer, and this a plurality of second five equilibriums that comprised on this ranks memory buffer are the one second dimension arrangements along this ranks memory buffer;
Wherein this first dimension row's size is the number of the picture element that comprises for this each second branch such as grade;
Wherein this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on this ranks memory buffer;
Wherein this first cutting number is the quantity that divides exactly these a plurality of picture elements of being kept in this ranks memory buffer;
Wherein this second cutting number is the quantity that divides exactly a plurality of picture elements that each first branch such as grade comprises in this;
Wherein the quantity of a plurality of C grades branches of this that is comprised in each second five equilibrium at this is to divide exactly the picture element number that each second branch such as grade comprises in this.
3. color sequence time control circuit according to claim 1, it is characterized in that: one first auxiliary memory and one second auxiliary memory that wherein this color sequence displayer comprised are the memory buffer that is used for being used as this color data sequencing unit, and when both one of be when being used for the reading of sub-picture element that this color data sequencing unit sorted, other one is to be used for writing of sub-picture element that this color data sequencing unit sorted.
4. color sequence time control circuit according to claim 1, it is characterized in that, other comprises: an input buffer storage, be used for the outside is inputed to a synchronous signal, a picture element frequency, and these a plurality of picture elements of this color sequence time control circuit, do synchronous processing with the employed system frequency of this color sequence time control circuit, and it is temporary a plurality of picture elements to input to this raw column data sequencing unit; An and driving control unit, be used for producing the control data-driven unit that this color sequence displayer comprised, one scan driver element, and the sequential of a LED driving circuit, and control this data-driven unit and this scan drive cell shows this full-color picture that is produced on the display panel that this color sequence displayer comprised according to the sub-picture element of this different colours that this color sequence time control circuit is exported according to this sync signal and this system frequency.
5. color sequence displayer system, it is characterized in that, comprise: a raw column data sequencing unit, be contained in the host side that this color sequence displayer system is comprised, be used for keeping in and reading a plurality of picture elements, this raw column data sequencing unit comprises: a ranks memory buffer is used for keeping in these a plurality of picture elements; Reach one and insert ranking circuit, be used for being divided into a plurality of first five equilibriums according to these a plurality of picture elements that one first cutting number is kept in this ranks memory buffer, to read in parallel each self-contained picture element of arranging with matrix-style of these a plurality of first five equilibriums, this insertion ranking circuit and a plurality of picture elements that comprise according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read picture element in proper order to read according to a picture element in each second five equilibrium in regular turn; An and color data sorting unit, be contained in the color sequence displayer that this color sequence displayer system is comprised, be used for the color of this a plurality of each self-contained sub-picture elements of picture element of keeping in and reading according to this raw column data sequencing unit, should each self-contained sub-picture element of a plurality of picture elements classified and sort;
Wherein this color sequence displayer is a sub-picture element of exporting a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture;
This picture element that wherein is used for reading in each second five equilibrium at this in regular turn picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a picture element read picture element, and the quantity of should a plurality of C grades dividing is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
6. color sequence displayer according to claim 5 system is characterized in that:
Wherein this ranks memory buffer is with temporary these a plurality of picture elements of two-dimensional approach;
Wherein a plurality of picture elements of comprising of each second five equilibrium of these a plurality of second five equilibriums are that one first dimension along this ranks memory buffer is temporary in the one first dimension row in this ranks memory buffer, the a plurality of picture elements that make this each second five equilibrium comprise are that the mode of a plurality of elements of being comprised with this first dimension row is temporary in this ranks memory buffer, and this a plurality of second five equilibriums that comprised on this ranks memory buffer are the one second dimension arrangements along this ranks memory buffer;
Wherein this first dimension row's size is the number of the picture element that comprises for this each second branch such as grade;
Wherein this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on this ranks memory buffer;
Wherein this first cutting number is the quantity that divides exactly these a plurality of picture elements of being kept in this ranks memory buffer;
Wherein this second cutting number is the quantity that divides exactly a plurality of picture elements that each first branch such as grade comprises in this;
Wherein the quantity of a plurality of C grades branches of this that is comprised in each second five equilibrium at this is to divide exactly the picture element number that each second branch such as grade comprises in this.
7. color sequence displayer according to claim 5 system is characterized in that other comprises: one first auxiliary memory; And one second auxiliary memory;
Wherein this first auxiliary memory and this second auxiliary memory are the memory buffer that is used for being used as this color data sequencing unit, and when both are when being used for the reading of sub-picture element that this color data sequencing unit sorted, other one is to be used for writing of sub-picture element that this color data sequencing unit sorted.
8. color sequence displayer according to claim 6 system, it is characterized in that, other comprises: an input buffer storage, receive its these a plurality of picture elements of keeping in and reading, the outside is inputed to a synchronous signal, a picture element frequency, and this a plurality of picture elements of this color sequence displayer with this raw column data sequencing unit of cause, do synchronous processing, and should a plurality of picture elements input to this color data sequencing unit and keep in the employed system frequency of this color sequence displayer; An and driving control unit, be used for producing the control data-driven unit that this color sequence displayer comprised, one scan driver element, and the sequential of a LED driving circuit, and control this data-driven unit and this scan drive cell shows this full-color picture that is produced on the display panel that this color sequence displayer comprised according to the sub-picture element of this different colours that this color sequence time control circuit is exported according to this sync signal and this system frequency.
9. color sequence time control circuit, be applied to a color sequence displayer, it is characterized in that, comprise: a color data sorting unit, be used for color according to a plurality of each self-contained sub-picture element of picture element, should a plurality of picture elements each self-contained sub-picture element classification and ordering the sub-picture element group that pluralizes, and each sub-picture element group is corresponding to different colors; And a raw column data sequencing unit, temporary and read the sub-picture element of this plural number group with this color data sequencing unit of cause, comprise: a ranks memory buffer is used for a sub-picture element group of the sub-picture element of temporary this plural number group; Reach one and insert ranking circuit, the individual sub-picture element of plural number that the sub-picture element of this that is used for this ranks memory buffer keep in according to one first cutting number group is comprised is divided into a plurality of first five equilibriums, to read in parallel each self-contained sub-picture element of arranging with matrix-style of these a plurality of first five equilibriums, a this insertion ranking circuit and a plural number picture element that comprises according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read sub-picture element in proper order to read according to a sub-picture element in each second five equilibrium in regular turn;
Wherein this color sequence displayer is the sub-picture element group that exports a plurality of different colours that this raw column data sequencing unit read according to a mistiming, to produce a full-color picture;
This sub-picture element that wherein is used for reading in each second five equilibrium at this in regular turn sub-picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a sub-picture element read picture element, and the quantity of should a plurality of C grades dividing is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
10. color sequence time control circuit according to claim 9 is characterized in that:
Wherein this ranks memory buffer is a plural number picture element that is comprised with temporary this sub-picture element group of two-dimensional approach;
Wherein plural number the sub-picture element that comprises of each second five equilibrium of these a plurality of second five equilibriums is that one first dimension along this ranks memory buffer is temporary in the one first dimension row in this ranks memory buffer, the mode that a plural number picture element that makes this each second five equilibrium comprise is arranged a plurality of elements that comprised with this first dimension is temporary in this ranks memory buffer, and these a plurality of second five equilibriums that comprised on this ranks memory buffer are to arrange along one second dimension of this ranks memory buffer;
Wherein this first dimension row's size is the number of the sub-picture element that comprises for this each second branch such as grade;
Wherein this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on this ranks memory buffer;
Wherein this first cutting number is the quantity that divides exactly the individual sub-picture element of this plural number of keep in this ranks memory buffer;
Wherein this second cutting number is the quantity that divides exactly the plural number picture element that each first branch such as grade comprises in this;
Wherein the quantity of a plurality of C grades branches of this that is comprised in each second five equilibrium at this is to divide exactly the sub-picture element number that each second branch such as grade comprises in this.
11. color sequence time control circuit according to claim 9, it is characterized in that: one first auxiliary memory and one second auxiliary memory that wherein this color sequence displayer comprised are the memory buffer that is used for being used as this color data sequencing unit, and when both one of be when being used for the reading of sub-picture element that this color data sequencing unit sorted, other one is to be used for writing of sub-picture element that this color data sequencing unit sorted.
12. color sequence time control circuit according to claim 9, it is characterized in that, other comprises: an input buffer storage, be used for the outside input to this color sequence time control circuit a synchronous signal, a picture element frequency, and this a plurality of picture elements and the employed system frequency of this color sequence time control circuit do synchronous processing, and should a plurality of picture elements input to this raw column data sequencing unit and keep in; And
One driving control unit, be used for producing the control data-driven unit that this color sequence displayer comprised, one scan driver element, and the sequential of a LED driving circuit, and control this data-driven unit and this scan drive cell shows this full-color picture that is produced on the display panel that this color sequence displayer comprised according to the sub-picture element of this different colours group that this raw column data sequencing unit is exported according to this sync signal and this system frequency.
13. color sequence time control circuit, be applied to a color sequence displayer, it is characterized in that comprising: a raw column data sequencing unit, be used for temporary and read the sub-picture element of the plural number group that inputs to this color sequence time control circuit by the outside, comprise: a ranks memory buffer, a sub-picture element group that is used for that temporary these a plurality of sub-picture element groups corresponding to different colours are comprised; Reach one and insert ranking circuit, the individual sub-picture element of plural number that the sub-picture element of this that is used for this ranks memory buffer keep in according to one first cutting number group is comprised is divided into a plurality of first five equilibriums, to read in parallel each self-contained sub-picture element of arranging with matrix-style of these a plurality of first five equilibriums, a this insertion ranking circuit and a plural number picture element that comprises according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read sub-picture element in proper order to read according to a sub-picture element in each second five equilibrium in regular turn;
Wherein this color sequence time control circuit is to share a display card (Video Board) and a memory buffer that this display card comprised with a host side, and should plural number sub-picture element group be by this display card and this memory buffer with each the self-contained sub-picture element classification of a plurality of picture elements and sort produced;
Wherein this color sequence displayer is the sub-picture element group that exports a plurality of different colours that this raw column data sequencing unit read according to a mistiming, to produce a full-color picture;
This sub-picture element that wherein is used for reading in each second five equilibrium at this in regular turn sub-picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a sub-picture element read picture element, and the quantity of should a plurality of C grades dividing is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
14. color sequence time control circuit according to claim 13 is characterized in that:
Wherein this ranks memory buffer is a plural number picture element that is comprised with temporary this sub-picture element group of two-dimensional approach;
Wherein plural number the sub-picture element that comprises of each second five equilibrium of these a plurality of second five equilibriums is that one first dimension along this ranks memory buffer is temporary in the one first dimension row in this ranks memory buffer, the mode that a plural number picture element that makes this each second five equilibrium comprise is arranged a plurality of elements that comprised with this first dimension is temporary in this ranks memory buffer, and these a plurality of second five equilibriums that comprised on this ranks memory buffer are to arrange along one second dimension of this ranks memory buffer;
Wherein this first dimension row's size is the number of the sub-picture element that comprises for this each second branch such as grade;
Wherein this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on this ranks memory buffer;
Wherein this first cutting number is the quantity that divides exactly the individual sub-picture element of this plural number of keep in this ranks memory buffer;
Wherein this second cutting number is the quantity that divides exactly the plural number picture element that each first branch such as grade comprises in this;
Wherein the quantity of a plurality of C grades branches of this that is comprised in each second five equilibrium at this is to divide exactly the sub-picture element number that each second branch such as grade comprises in this.
15. color sequence time control circuit according to claim 13, it is characterized in that comprising in addition: an input buffer storage, be used for the outside is inputed to a synchronous signal, a picture element frequency, and these a plurality of picture elements of this color sequence time control circuit, do synchronous processing with the employed system frequency of this color sequence time control circuit, and it is temporary a plurality of picture elements to input to this raw column data sequencing unit; And
One driving control unit, be used for producing the control data-driven unit that this color sequence displayer comprised, one scan driver element, and the sequential of a LED driving circuit, and control this data-driven unit and this scan drive cell shows this full-color picture that is produced on the display panel that this color sequence displayer comprised according to the sub-picture element of this different colours group that this raw column data sequencing unit is exported according to this sync signal and this system frequency.
16. color sequence time control circuit, be applied to a color sequence displayer, it is characterized in that comprising: one blendes together raw column data sequencing unit (Hybrid Line Data Sorting Unit), be used for keeping in a plurality of picture elements, and be used for reading this a plurality of picture elements with the form of sub-picture element, comprise: a color data sorting unit, be used for color according to these a plurality of each self-contained sub-picture elements of picture element, should each self-contained sub-picture element of a plurality of picture elements being classified and sort be the sub-picture element of plural number group, and the sub-picture element of each of should plural number sub-picture element group group is corresponding to different colors; One ranks memory buffer is used for the sub-picture element of temporary this plural number of matrix-style group; Reach one and insert ranking circuit, being used for the individual sub-picture element of plural number that a sub-picture element group of the sub-picture element of this plural number of this ranks memory buffer keep in according to one first cutting number group comprised is divided into a plurality of first five equilibriums, to read in parallel each self-contained sub-picture element of arranging with matrix-style of these a plurality of first five equilibriums, a this insertion ranking circuit and a plural number picture element that comprises according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read sub-picture element in proper order to read according to a sub-picture element in each second five equilibrium in regular turn;
Wherein this color sequence time control circuit is the sub-picture element group that exports a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture;
This sub-picture element that wherein is used for reading in each second five equilibrium at this in regular turn sub-picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a sub-picture element read picture element, and the quantity of should a plurality of C grades dividing is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer.
17. color sequence time control circuit according to claim 16 is characterized in that:
Wherein this ranks memory buffer is with the sub-picture element of temporary this plural number of two-dimensional approach group;
Wherein plural number the sub-picture element that comprises of each second five equilibrium of these a plurality of second five equilibriums is that one first dimension along this ranks memory buffer is temporary in the one first dimension row in this ranks memory buffer, make that a plural number picture element that this each second five equilibrium comprises is that the mode of a plurality of elements of being comprised with this first dimension row is temporary in this ranks memory buffer, and this a plurality of second five equilibriums that comprised on this ranks memory buffer are the one second dimension arrangements along this ranks memory buffer;
Wherein this first dimension row's size is the number of the sub-picture element that comprises for this each second branch such as grade;
Wherein this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on this ranks memory buffer;
Wherein this first cutting number is the quantity that divides exactly all sub-picture elements that the individual sub-picture element of this plural number of keep in this ranks memory buffer group comprised;
Wherein this second cutting number is the quantity that divides exactly the plural number picture element that each first branch such as grade comprises in this;
Wherein the quantity of a plurality of C grades branches of this that is comprised in each second five equilibrium at this is to divide exactly the sub-picture element number that each second branch such as grade comprises in this.
18. color sequence time control circuit according to claim 16, it is characterized in that: one first auxiliary memory that wherein this color sequence displayer comprised and one second auxiliary memory are to be used for being used as the memory buffer that this blendes together the raw column data sequencing unit, and when both one of be when being used for this and blending together reading of sub-picture element that the raw column data sequencing unit sorted, other one is to be used for this to blend together writing of sub-picture element that the raw column data sequencing unit sorted.
19. color sequence time control circuit according to claim 16, it is characterized in that comprising in addition: an input buffer storage, be used for the outside is inputed to a synchronous signal, a picture element frequency, and these a plurality of picture elements of this color sequence time control circuit, do synchronous processing with the employed system frequency of this color sequence time control circuit, and should a plurality of picture elements inputing to this, to blend together the raw column data sequencing unit temporary; An and driving control unit, be used for producing the control data-driven unit that this color sequence displayer comprised, one scan driver element, and the sequential of a LED driving circuit, and control this data-driven unit and this scan drive cell shows this full-color picture that is produced on the display panel that this color sequence displayer comprised according to the sub-picture element of this different colours group that this color sequence time control circuit is exported according to this sync signal and this system frequency.
20. one kind is used image data ordering and read method on color sequence displayer, its spy then is to comprise: a plurality of picture element elements (Pixel Flement) that will be temporary in the ranks memory buffer that a color sequence displayer comprised according to one first cutting number are divided into a plurality of first five equilibriums, reading in parallel each self-contained picture element element of these a plurality of first five equilibriums, and a plurality of picture element elements that each branch such as first of these a plurality of first five equilibriums comprises are to be arranged in this ranks memory buffer with matrix-style; And a plurality of picture element elements that comprise according to each first branch such as grade that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, to read a picture element element in each C grade branch that a plurality of C grades that this branch such as second grade comprises divide in regular turn simultaneously;
Wherein these a plurality of C grades of comprising of this branch such as second grade quantity of dividing is the brake cable number that the one scan driver element that comprises corresponding to this color sequence displayer is opened at one time.
21. image data ordering and the read method of using on color sequence displayer according to claim 20 is characterized in that:
Wherein this ranks memory buffer is with temporary these a plurality of picture element elements of two-dimensional approach;
Wherein a plurality of picture element elements of comprising of each second five equilibrium of these a plurality of second five equilibriums are that one first dimension along this ranks memory buffer is temporary in the one first dimension row in this ranks memory buffer, the a plurality of picture element elements that make this each second five equilibrium comprise are that the mode of a plurality of elements of being comprised with this first dimension row is temporary in this ranks memory buffer, and this a plurality of second five equilibriums that comprised on this ranks memory buffer are the one second dimension arrangements along this ranks memory buffer;
Wherein this first dimension row's size is the number of the picture element element that comprises for this each second branch such as grade;
Wherein this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on this ranks memory buffer;
Wherein this first cutting number is the quantity that divides exactly these a plurality of picture element elements of being kept in this ranks memory buffer;
Wherein this second cutting number is the quantity that divides exactly a plurality of picture element elements that each first branch such as grade comprises in this;
Wherein the quantity of a plurality of C grades branches of this that is comprised in each second five equilibrium at this is to divide exactly the picture element element number that each second branch such as grade comprises in this.
22. image data ordering and the read method of using on color sequence displayer according to claim 20, it is characterized in that: described picture element element is to be a picture element, and this method comprises in addition:
According to the color of institute's this a plurality of each self-contained sub-picture elements of picture element element of keeping in and reading, should each self-contained sub-picture element of a plurality of picture element elements be classified and sorted; Reach the sub-picture element of a plurality of different colours of classifying and sorting, to produce a full-color picture according to mistiming output institute.
23. image data ordering and the read method of using on color sequence displayer according to claim 20, it is characterized in that: described picture element element is to be a sub-picture element, and this method comprises in addition:
According to the color of institute's this a plurality of each self-contained sub-picture elements of picture element element of keep in and reading, each self-contained sub-picture element of these a plurality of picture element elements being classified and sort is a plurality of sub-picture element groups corresponding to different colours; And according to the sub-picture element group of mistiming output institute's this a plurality of different colours of classifying and sorting, to produce a full-color picture.
24. color sequence displayer system, it is characterized in that comprising: a host side comprises: a display card comprises: a color data sorting unit, be used for color according to a plurality of each self-contained sub-picture element of picture element, should each self-contained sub-picture element of a plurality of picture elements classified and sort; One raw column data sequencing unit is used for keeping in and reading these a plurality of picture elements that this color data sequencing unit is classified and sorted, and this ranks buffering sequencing unit is to comprise: a ranks memory buffer is used for keeping in these a plurality of picture elements; Reach one and insert ranking circuit, be used for being divided into a plurality of first five equilibriums according to these a plurality of picture elements that one first cutting number is kept in this ranks memory buffer, to read in parallel each self-contained picture element of arranging with matrix-style of these a plurality of first five equilibriums, this insertion ranking circuit and a plurality of picture elements that comprise according to each branch such as first that one second cutting number will this a plurality of first five equilibriums are divided into a plurality of second five equilibriums, read picture element in proper order to read according to a picture element in each second five equilibrium in regular turn; And a memory buffer, be used for being used as this color data sequencing unit and this raw column data sequencing unit to classify buffer cell when sorting of these a plurality of picture elements; An and color sequence displayer, comprise: an input buffer storage, receive its these a plurality of picture elements of keeping in and reading, the outside is inputed to a synchronous signal, a picture element frequency, and these a plurality of picture elements of this color sequence displayer with this raw column data sequencing unit of cause, do synchronous processing with the employed system frequency of this color sequence displayer; An and driving control unit, be used for producing the control data-driven unit that this color sequence displayer comprised, one scan driver element, and the sequential of a LED driving circuit, and control this data-driven unit and this scan drive cell shows this full-color picture that is produced on the display panel that this color sequence displayer comprised according to the sub-picture element of this different colours that this color sequence time control circuit is exported according to this sync signal and this system frequency;
Wherein this color sequence displayer is a sub-picture element of exporting a plurality of different colours that this color data sequencing unit classified according to a mistiming, to produce a full-color picture;
This picture element that wherein is used for reading in each second five equilibrium at this in regular turn picture element read order be with read simultaneously each C grade that a plurality of C grades that this branch such as second grade comprises divide divide in the mode of a picture element read picture element, and the quantity of should a plurality of C grades dividing is the interior at one time brake cable number of being opened of one scan driver element that comprises corresponding to this color sequence displayer;
Wherein this color sequence displayer is to share this display card and this memory buffer with this host side.
25. color sequence displayer according to claim 25 system is characterized in that:
Wherein this ranks memory buffer is with temporary these a plurality of picture elements of two-dimensional approach;
Wherein a plurality of picture elements of comprising of each second five equilibrium of these a plurality of second five equilibriums are that one first dimension along this ranks memory buffer is temporary in the one first dimension row in this ranks memory buffer, the a plurality of picture elements that make this each second five equilibrium comprise are that the mode of a plurality of elements of being comprised with this first dimension row is temporary in this ranks memory buffer, and this a plurality of second five equilibriums that comprised on this ranks memory buffer are the one second dimension arrangements along this ranks memory buffer;
Wherein this first dimension row's size is the number of the picture element that comprises for this each second branch such as grade;
Wherein this second dimension row's size is the total quantity for these a plurality of second five equilibriums that comprised on this ranks memory buffer;
Wherein this first cutting number is the quantity that divides exactly these a plurality of picture elements of being kept in this ranks memory buffer;
Wherein this second cutting number is the quantity that divides exactly a plurality of picture elements that each first branch such as grade comprises in this;
Wherein the quantity of a plurality of C grades branches of this that is comprised in each second five equilibrium at this is to divide exactly the picture element number that each second branch such as grade comprises in this.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009103080789A CN101661704B (en) | 2009-10-05 | 2009-10-05 | Color sequence time control circuit and correlative color sequence displayer system and method thereof |
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| CN2009103080789A CN101661704B (en) | 2009-10-05 | 2009-10-05 | Color sequence time control circuit and correlative color sequence displayer system and method thereof |
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| CN101661704B CN101661704B (en) | 2011-08-24 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814261A (en) * | 2010-04-16 | 2010-08-25 | 华映视讯（吴江）有限公司 | The driving method of color sequential liquid crystal display and color sequential liquid crystal display |
| CN107018297A (en) * | 2015-11-27 | 2017-08-04 | 钰立微电子股份有限公司 | Image acquiring device |
| CN107886896A (en) * | 2017-11-03 | 2018-04-06 | 惠科股份有限公司 | Three colors and four color pixel display panel compatible systems and method |
-
2009
- 2009-10-05 CN CN2009103080789A patent/CN101661704B/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814261A (en) * | 2010-04-16 | 2010-08-25 | 华映视讯（吴江）有限公司 | The driving method of color sequential liquid crystal display and color sequential liquid crystal display |
| CN101814261B (en) * | 2010-04-16 | 2012-09-05 | 华映视讯（吴江）有限公司 | Color sequential liquid crystal display and drive method thereof |
| CN107018297A (en) * | 2015-11-27 | 2017-08-04 | 钰立微电子股份有限公司 | Image acquiring device |
| CN107886896A (en) * | 2017-11-03 | 2018-04-06 | 惠科股份有限公司 | Three colors and four color pixel display panel compatible systems and method |
| CN107886896B (en) * | 2017-11-03 | 2019-08-23 | 惠科股份有限公司 | Three colors and four color pixel display panel compatible systems and method |
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| CN101661704B (en) | 2011-08-24 |
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