CN101655643A

CN101655643A - Manufacturing method for thin-film transistor array panel

Info

Publication number: CN101655643A
Application number: CN200910164010A
Authority: CN
Inventors: 朴云用; 李元熙; 金一坤; 林承泽; 宋俞莉; 田尚益
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2003-02-03
Filing date: 2004-02-03
Publication date: 2010-02-24
Also published as: KR100910566B1; KR20040070396A

Abstract

A method of manufacturing a thin film transistor array panel is provided. The method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductormember; forming a data conductive layer including a data line and a drain electrode; forming a passivation layer having a contact hole exposing at least a portion of the drain electrode and a portionof the gate insulating layer near an edge of the drain electrode; and forming a pixel electrode connected to the drain electrode through the contact hole, wherein the pixel electrode is brought into contact with the upper surface of the drain electrode and at least one part of the upper area of the gate insulating layer near the edge of the drain electrode. According to the invention, undercut isprevented from occurring under the wiring portion when the exposure portion is exposed from the wiring boundary, and the lateral surface of the contact portion is ensured slowly. Thereby, line break is prevented in the contact portion, a driving integrated circuit can be stably installed, therefore, reliability of the contact portion is ensured.

Description

The manufacture method of thin-film transistor display panel

The application is that application number is 200410039503.6, the applying date is on February 3rd, 2004, denomination of invention is divided an application for the original bill application of " thin-film transistor display panel and manufacture method thereof and be used for the mask of this panel ".

Technical field

The present invention relates to a kind of thin-film transistor display panel and manufacture method thereof and the mask that is used for this panel.

Background technology

LCD (LCDs) is one of the most widely used flat-panel screens at present.LCD comprises having the two sides that produces electric field electrode and place liquid crystal layer therebetween.LCD is by applying voltage to produce the electric field display image in liquid crystal (LC) layer to producing electric field electrode, and its orientation that can determine liquid crystal molecule in the liquid crystal layer is to adjust polarization of incident light.

Comprising and can on the corresponding panel, produce in the LCD of electric field electrode, wherein a kind of LCD have a plurality of on a panel with matrix form pixel electrodes arranged and the common electrode that can cover another panel all surfaces.The demonstration of this LCD image realizes by apply different voltages to corresponding pixel electrode.To be used to control a plurality of three terminal component TFT that are applied to pixel electrode voltage for this reason and be connected to corresponding pixel electrode, a plurality of gate lines that will transmit this TFT signal of control again are arranged on the panel with a plurality of data lines that transmission is applied to pixel electrode voltage.

This panel that is used for LCD has the layer structure that comprises a plurality of conductive layers and a plurality of insulation courses.Gate line, data line and pixel electrode are made up of different conductive layers (following branch another name " grid conductor ", " data conductor " and " pixel conductor "), preferably deposit and be insulated layer successively separately.TFT comprises three electrodes: grid that is formed by grid conductor and source electrode and the drain electrode that is formed by data conductor.Usually connect by the semiconductor that is positioned at below it between source electrode and the drain electrode, drain electrode then connects pixel electrode by the hole on the insulation course usually.

In order to reduce the signal lag in gate line and the data line, grid conductor and data conductor are preferably made by the aluminum-based metal such as aluminium and this class of aluminium alloy with low-resistivity.For the electric field that applies voltage forms and has light transmission, pixel electrode is usually by making such as the transparent conductive material of tin indium oxide (ITO) and this class of indium zinc oxide (IZO).

The problem that the contact resistance of corrosion of aluminium series metal and contact portion increases when simultaneously, also existing the aluminium series metal to contact with ITO or IZO.

As mentioned above, drain electrode is connected by the contact hole on the insulator with pixel electrode.This connection forms as follows, at first on insulator, punch to expose the top aluminium series metal layer of drain electrode, the exposed portions serve of removing upper metallization layer by comprehensive etching (blanket-etching) forms pixel electrode thereon at last to expose the good lower layer of contact again.But the aluminium series metal of lower sidewall that often comes in contact the hole in comprehensive etching process of aluminium series metal layer is formed incision (undercut) by over etching on insulation course.This incision may cause near near the pixel electrode that forms thereafter side tender incision at broken string or the pixel electrode incision, thereby has increased the contact resistance between pixel electrode and the drain electrode.

Summary of the invention

The invention provides a kind of thin-film transistor display panel, it comprises: be formed at the gate line on the insulated substrate, be formed on the gate insulator on the described gate line, be formed on the semiconductor layer on described gate insulator top, be formed on the data line that a described insulation course top and a part and described semiconductor layer join, have the described data line of covering and partly expose the passivation layer of described data line or described gate line boundary line, at least cover the border of the described gate line that exposes by described first contact hole or data line end portion in addition and be formed on the auxiliary duplicate of contact on described passivation layer top.

Lower layer that described gate line or described data line can be made up of chromium or molybdenum or molybdenum alloy and aluminum or aluminum alloy are formed upper layer and are formed, and preferentially, the auxiliary duplicate of being made up of IZO or ITO of described contact contacts with described lower layer.

This thin-film transistor display panel can also comprise being separated with described data line and be formed on described gate insulator top and a part and the drain electrode of joining of described semiconductor layer, the pixel electrode that is formed on described passivation layer top in addition, is connected with described drain electrode by second contact hole that exposes described drain electrode.

According to the invention provides a kind of exposure mask, it comprises: the zone of opacity that stops light, be formed on the slit grating that zone of opacity comprises a plurality of slits in addition, slit is essentially the straight line form, and described slit width and spacing are within the 0.8-2.0 mu m range.

Described slit can have depressed part.

Described mask can be used to make thin-film transistor display panel, this panel has viewing area and the residing neighboring area of described wiring end portion that a plurality of wirings intersect, described slit comprises first slit that is positioned at the viewing area and second slit that is positioned at the neighboring area, and described first slit and described second slit can have mutually different width and spacing.

Described slit comprises first slit that is positioned at described viewing area and described neighboring area and is positioned at second slit in remaining zone that first slit and second slit can have mutually different width and spacing.

According to the manufacture method that the invention provides a kind of thin-film transistor display panel, this method comprises: form the gate line stage on insulating panel; Form the gate insulator stage; Form semiconductor stage; Formation comprises the data conductive layer stage of data line and drain electrode; Formation has the passivation layer stage of contact hole, and this contact hole exposes drain electrode at least a portion and is adjacent to the gate insulator layer segment of grain boundaries line; Form the pixel electrode stage that is connected with drain electrode by contact hole on passivation layer top; With the mask fabrication wiring pattern that forms a plurality of slits, at least one has the straight line form and this slit has about 0.8-2.0 mu m range width and spacing in semiconductor and the passivation layer.

Mask can comprise that residing of first area, the slit that can not see through light see through the second area of a part of light, the 3rd zone that light can see through fully.

In the optical etching operation, form positive photoresist, photoresist comprises first on the first of data line and drain electrode, the second portion on the drain electrode second portion, the third part on the gate line end portion, the photoresist second portion can be thinner than photoresist first, and the photoresist third part can be thinner than photoresist second portion.

Photoresist can also comprise respective data lines end portion and four part littler than first thickness.

This manufacture method can also comprise uses photoresist to carry out etching, the stage of exposing the gate insulator below the third part of passivation layer below the second and the 4th part of photoresist and photoresist, remove the exposed portions serve and the gate insulator exposed portions serve of passivation layer in addition, the contact hole stage of exposing data line end portion and gate line end portion of formation.

In mask, the slit that is distributed in corresponding photoresist second portion zone can form mutually different spacing and width with the slit that is distributed in corresponding photoresist the 4th subregion.

At least one comprised with the stage that the optics etching work procedure forms in semiconductor and the passivation layer: in the gate insulator top depositing semiconductor layers stage; The depositing insulating layer stage on the data conductive layer; Form the photoresist stage on insulation course top; Carry out etching with photoresist and expose gate insulator stage below the third part of passivation layer below the second and the 4th part of photoresist and photoresist; Remove the contact hole that exposes data line end portion and gate line end portion that passivation layer part and gate insulator exposed portions serve form, and the stage of exposing a semiconductor layer part; Remove the semiconductor layer exposed portions serve in addition and finish semiconductor stage.

Semiconductor is included in a plurality of semiconductor portions that are separated from each other between the adjacent data line.

Thin-film transistor display panel comprises viewing area and gate line end portion and the residing neighboring area of data line end portion that gate line and data line intersect, slit is made up of with being positioned at the slit of viewing area and remainder corresponding region, neighboring area the slit that is distributed in viewing area and corresponding region, neighboring area, and they form with mutually different spacing and width.

At least one comprises the top conductive layer that the lower conducting layer be made up of chromium or molybdenum or molybdenum alloy and aluminum or aluminum alloy are formed in gate line and the data conductive layer.

Drain electrode comprises lower conducting layer and top conductive layer, can also comprise before the pixel electrode formation stage and removing the top conductive layer stage.

In the optical etching operation, the permutation slit grating makes wherein at least one and grain boundaries line overlap.

In the optical etching operation, with at least one can have the concaveconvex structure of depression in the slit grating of grain boundaries line overlap.

In the optical etching operation, the permutation slit grating makes wherein to be positioned at outside the drain electrode more than two.

Description of drawings

The present invention will become clearer by describing its specific embodiment with reference to the accompanying drawings in detail, wherein:

Fig. 1 is the synoptic diagram that is used for liquid crystal display substrate according to an embodiment of the invention;

Fig. 2 is the schematic configuration diagram that is used for the thin-film transistor display panel of LCD according to an embodiment of the invention;

Fig. 3 is the arrangement plan that is used for the typical thin film transistor display panel and manufacturing method thereof of LCD according to an embodiment of the invention;

Fig. 4 is a thin-film transistor display panel shown in Figure 3 cross-sectional view along IV-IV ' line;

Fig. 5 A, Fig. 6 A, Fig. 7 A, and Fig. 9 A be the arrangement plan of the thin-film transistor display panel in interstage of the manufacture method according to an embodiment of the invention shown in Fig. 1-4;

Fig. 5 B, Fig. 6 B, Fig. 7 B, and Fig. 9 B be respectively Fig. 5 A, Fig. 6 A, Fig. 7 A, and Fig. 9 A shown in thin-film transistor display panel along VB-VB ' line, VIB-VIB ' line, VIIB-VIIB ' line, and the cross-sectional view of IXB-IXB ' line;

Fig. 8 is the cross-sectional view of the thin-film transistor display panel shown in Fig. 7 A along VIIB-VIIB ' line, is to scheme Fig. 7 B next stage;

Figure 10 is the figure that shows the permutation between the slit of drain electrode and mask;

Figure 11 and Figure 12 are the cross-sectional view of the thin-film transistor display panel shown in Fig. 9 A along IXB-IVB ' line, and it is to scheme Fig. 9 B next stage;

Figure 13 is the arrangement plan that is used for the thin-film transistor display panel of LCD according to another embodiment of the present invention;

Figure 14 and Figure 15 are respectively thin-film transistor display panel shown in Figure 13 cross-sectional view along XIV-XIV ' line and XV-XV ' line;

Figure 16 A is according to thin-film transistor display panel arrangement plan in the phase one of one embodiment of the invention manufacturing Figure 13 thin-film transistor display panel method extremely shown in Figure 15;

Figure 16 B and Figure 16 C are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 16 A along XVIB-XVIB ' line and XVIC-XVIC ' line;

Figure 17 A and Figure 17 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 16 A along XVIB-XVIB ' line and XVIC-XVIC ' line, and it is to scheme Figure 16 B and Figure 16 C next stage;

Figure 18 A is the thin-film transistor display panel arrangement plan of Figure 17 A and Figure 17 B next stage;

Figure 18 B and Figure 18 C are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 18 A along XVIIIB-XVIIIB ' line and XVIIIC-XVIIIC ' line;

Figure 19 A, Figure 20 A, Figure 21 A and Figure 19 B, Figure 20 B and Figure 21 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 18 A along XVIIIB-XVIIIB ' line and XVIIIC-XVIIIC ' line, and it is by the B of Figure 18 shown in the operation and Figure 18 C next stage;

Figure 22 A is the thin-film transistor display panel arrangement plan of Figure 21 A and Figure 21 B next stage;

Figure 22 B and Figure 22 C are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 22 A along XXIIB-XXIIB ' line and XXIIC-XXIIC ' line;

Figure 23 A, Figure 24 A and Figure 25 A and Figure 23 B, Figure 24 B and Figure 25 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 22 A along XXIIB-XXIIB ' line and XXIIC-XXIIC ' line, and it is to scheme Figure 22 B and Figure 22 C next stage;

Figure 26 is the arrangement plan that is used for the thin-film transistor display panel of LCD according to another embodiment of the present invention;

Figure 27 is a thin-film transistor display panel shown in Figure 26 cross-sectional view along XXVII-XXVII ' line;

Figure 28 A, Figure 29 A and Figure 30 A are the arrangement plans according to thin-film transistor display panel in the interstage of one embodiment of the invention manufacturing thin-film transistor display panel method shown in Figure 27;

Figure 28 B, Figure 29 B and Figure 30 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 28 A, Figure 29 A and Figure 30 A along XXVIIIB-XXVIIIB ' line, XXIXB-XXIXB ' and XXIXB-XXIXB ' line;

Figure 31 and Figure 32 are the cross-sectional view of the thin-film transistor display panel shown in Figure 30 A along XXXB-XXXB ' line, and it is to scheme Figure 30 B next stage;

Figure 33 is the arrangement plan of thin-film transistor display panel according to another embodiment of the present invention; And

Figure 34 is a thin-film transistor display panel shown in Figure 33 cross-sectional view along XXXIV-XXXIV ' line.

Embodiment

The present invention now is illustrated more comprehensively with reference to the accompanying drawings hereinafter, and it illustrates in a preferred embodiment of the invention.It is multi-form that but the present invention can show as, and it is not limited to the specific embodiment in this explanation.

In the accompanying drawings, the thickness and the zone of each layer have for the sake of clarity been exaggerated.In full piece of writing instructions, similar elements is being enclosed identical symbol, should be understood that when mention elements such as layer, film, zone or substrate other part " on " time, refer to that it is located immediately on other element, it is mediate perhaps also to have other element.On the contrary, when certain element referred " directly " was positioned on other part, it was mediate to refer to there is no other element.

Referring now to tft array panel and the manufacture method thereof of accompanying drawing detailed description according to the specific embodiment of the invention.

Fig. 1 is the synoptic diagram that is used for liquid crystal display substrate according to an embodiment of the invention.

As shown in Figure 1, on an insulated substrate, form the multiple arrangement zone simultaneously.For example: as Fig. 1, form 4

device zones

10,20,30,40 on the glass substrate 100, if when the substrate that forms was thin-film transistor display panel,

panel zone

10,20,30,40 comprised

viewing area

11,21,31,41 and the neighboring area of being made up of a plurality of

pixel regions

12,22,32,42.On the

viewing area

11,21,31,41 with matrix form repeat to distribute TFT, wiring and pixel electrode etc., the factor that is connected with external drive component of distributing on the neighboring

area

12,22,32,42 promptly connect up end portion and other electrostatic discharge protective circuit etc.

When forming this LCD, generally use the stepping exposure machine.When using this exposure machine,

viewing area

11,21,31,41 and neighboring

area

12,22,32,42 are divided into a plurality of exposure areas (in the zone that Fig. 1 divides with dotted line), the light-sensitive surface that is coated with on the film is exposed with same mask or different photomasks by the zone, the whole substrates of exposure back video picture form photoresist, etching lower film afterwards, thus the certain thin films grating formed.Repeat to form this thin film grating, finally finish the thin-film transistor display panel that is used for LCD.

Fig. 2 is the schematic configuration diagram that is used for the thin-film transistor display panel of LCD according to an embodiment of the invention.

As shown in Figure 2, in the viewing area that surrounds with line 1, distribute and comprise the gate line 121 that a plurality of TFT3 and the pixel electrode 191 that is electrically connected with each TFT3 respectively intersect and the wiring of data line 171.The enlarged portion 125,179 that prolongs distribution gate line 121 and data line 171 in viewing area circumferential perimeter zone, enlarged portion 125,179 is connected with grid and data-driven integrated circuit for the signal that receives to gate line 121 and data line 171 transmission.And, the element that causes for the discharge that prevents static destroys, arranged that respectively electric connection grid polar curve 121 and data line 171 form equipotential grid shortening bar 124 and data short bar 174, are electrically connected grid short bar 124 and data short bar 174 by short bar connecting portion 194.This short bar 124,174 finally will separate from gate line 121 and data line 171 electricity, and in order to separate their when cutting off substrate, cutting off line is Reference numeral 2.Though in figure, do not represent, between short bar connecting portion 194 and grid shortening bar 124 and data short bar 174, got involved insulation course (not shown), form the contact hole that connects them on this insulation course.And TFT3 and pixel electrode 191 also can be put into insulation course betwixt, at this moment also form the contact hole that connects them.

First embodiment

At first, the while describes the arraying bread board that is used for LCD TFT according to an embodiment of the invention with reference to Fig. 3 and Fig. 4 in detail with Fig. 1 and Fig. 2.

Fig. 3 is the TFT that is positioned at thin-film transistor display panel viewing area shown in Figure 2 according to an embodiment of the invention, be positioned at the example of the signal wire enlarged portion arrangement plan of pixel electrode and signal wire part and neighboring area, and Fig. 4 is a thin-film transistor display panel shown in Figure 3 cross-sectional view along IV-IV ' line.

On insulated substrate 110, form many gate lines 121 of transmission signal and the grid shortening bar 124 of main horizontal expansion.Gate line 121 main horizontal expansions, the part of each gate line 121 forms a plurality of grids 123.And each gate line 121 comprises outstanding a plurality of juts 127 downwards, in order to be connected extension 126 between enlarged portion 125 and the grid shortening bar 124 in addition with the enlarged portion 125 of expanding its width being connected of other layer or external device (ED).Gate line 121 major parts are positioned at the viewing area, but the enlarged portion 125 of gate line 121 and extension 126 are positioned at the neighboring area together with grid shortening bar 124.

Grid shortening bar 124 comprises that with gate line 121 two different layers of physical property are lower layer 121p and the upper layer 121q on it.Upper layer 121q for postpone signal or reduce voltage descend by the Low ESR metal for example aluminium series metal such as aluminum or aluminum alloy form.Different therewith, lower layer 121p particularly has good physical, chemistry, compositions such as the material of electrically contacting property such as molybdenum, molybdenum alloy (molybdenum-tungalloy), chromium, tantalum, titanium with ITO (indium tin oxide) and IZO (indium zinc oxide) by other material.The example of lower layer 121p and upper layer 121q combination is chromium/aluminum-neodymium alloys.The lower layer of grid 123 and upper layer are used

symbol

123p, 123q respectively in Fig. 4, and the lower layer of jut 127 and upper layer are represented with

symbol

127p, 127q respectively.But the enlarged portion 125 of gate line 121 includes only lower layer.

Also have the side of lower layer 121p and upper layer 121q to tilt respectively and its inclination angle for substrate 110 is become 30-80 ° (degrees) approximately.

On gate line 121 and grid shortening bar 124, form the gate insulator of forming by silicon nitride 140.

Form a plurality of linear semiconductor of forming by amorphous silicon materials such as (amorphous silicon abbreviate a-Si as) 151 on insulation course 140 tops.The main longitudinal extension of linear semiconductor, therefrom a plurality of juts 154 extend to grid 123.Also have, linear semiconductor 151 enlarges its width in the place of meeting with gate line 121, covering gate polar curve 121 than large tracts of land.

Form a plurality of linear and island Ohmic contact duplicate of forming by the n+ type amorphous silicon hydride class material of silicide or the diffusion of n type impurity high concentration 161,165 on semiconductor 151 tops.Linear contact duplicate 161 has a plurality of juts 163, and this jut 163 contacts 165 one-tenth dibits of duplicate on the jut 154 of semiconductor 151 with island.

The side of semiconductor 151 and Ohmic contact duplicate 161,165 also tilts, and the inclination angle is 30-80 °.

On impedance contact duplicate 161,165 and gate insulator 140, form many data lines 171 and a plurality of drain electrode 175, a plurality of electric conductor 177 and data short bar 174 that is used for energy-storage capacitor respectively.

Data line 171 main longitudinal extensions intersect with gate line 121 and transmit data voltage.Each data line 171 comprise for the enlarged portion 179 of expanding its width being connected of other layer or external device (ED), be connected the extension 176 between enlarged portion 179 and the data short bar 174.Data line 171 major parts are positioned at the viewing area, but the enlarged portion 179 of data line 171 and extension 176 are positioned at the neighboring area together with data short bar 174.

The a plurality of branches that extend to drain electrode 175 in each data line 171 form source electrode 173.A pair of source electrode 173 and drain electrode 175 are separated from each other, and being as the criterion with grid 123 is positioned at the opposite mutually.Grid 123,

source electrode

173 and 175 juts 154 with semiconductor 151 that drain form TFT, the TFT passage be formed on source electrode 173 and the jut 154 between 175 of draining on.

Be used for the electric conductor 177 of energy-storage capacitor and jut 127 overlaids of gate line 121, the 174 main horizontal expansions of data short bar.

Lower layer

171p, 175p, the 177p that data short bar 174 and data line 171, drain electrode 175 and the electric conductor 177 that is used for energy-storage capacitor are made up of molybdenum, molybdenum alloy, chromium class and be positioned on aluminium

upper layer

171q, 175q, 177q serial or that silver-colored series metal is formed form.But the enlarged portion 179 of data line 171 includes only lower layer and removes upper layer 175q, the 177q part of drain electrode 175 and storage electrode 177, has exposed the part of its

underpart layer

175p, 177p.

Data short bar 174 and data line 171, drain electrode 175 and lower layer 171p, the 175p, 177p and

upper layer

171q, 175q, the 177q that are used for the electric conductor 177 of energy-storage capacitor are also as gate line 121, and its side is separately with about 30-80 ° inclination.

161,165 of Ohmic contact duplicates are in semiconductor 151 and its upper data lines 171 of its underpart and drain and exist between 175, play the reduction contact impedance.Linear semiconductor 151 has not by the

data line

171 and 175 exposed portions serve that stop that drain, and its exposed portions serve comprises source electrode 173 and drains between 175; Width at the local linear semiconductor 151 of major part is littler than the width of data line 171, but as front explanation, broadens at its width of part that meets with gate line 121, makes the smooth broken string that prevents data line 171 in side.

Data short bar 174, data line 171, drain electrode 175 and be used for the electric conductor 177 of energy-storage capacitor and the semiconductor 151 that exposes on form by planarization characteristics good and have photosensitive organism, the capacitive constants such as a-Si:C:O, a-Si:O:F that form with PCVD (Plasma Chemical Vapor Deposition) are low permittivity megohmite insulant below 4.0 or silicon nitride class inorganics is formed passivation layer 180.

On passivation layer 180, form, expose drain electrode 175 lower layer 175p respectively, be used for a plurality of contact holes 185,187,189 of energy-storage capacitor electric conductor 177 lower layer 177p and data line 171 enlarged portion 179, form a plurality of contact holes 182 that expose gate line 121 enlarged portion 125 with gate insulator 140.Passivation layer 180 and/or gate insulator 140 have a plurality of contact holes (not shown) that expose grid shortening bar 124 and data short bar 174 adjacent end part.

And, show further that in Fig. 3 and Fig. 4 contact hole 182,185,187,189 exposes the state of lower layer 125,175p, 177p, 179 marginal edge boundary line parts and gate insulator 140 and substrate 110 parts.There is not incision in the contact hole 182,185,187,189.

Form a plurality of pixel electrodes 190 of forming by ITO or IZO, the auxiliary duplicate 192,199 of a plurality of contact and short bar connecting portion 194 on the passivation layer 180.

Pixel electrode 190,175 receives data voltages and transmits data voltages to electric conductor 177 from draining respectively with drain electrode 175 and be used for energy-storage capacitor electric conductor 177 physics, be electrically connected by contact hole 185,187.

The pixel electrode 190 of reception data voltage forms electric field with the common electrode (not shown) of another arraying bread board (not shown) that receives common voltage, with this liquid crystal molecule from liquid crystal layer (not shown) between new arrangement the two poles of the earth 190,270.

And, pixel electrode 190 and common electrode form electric storage means (to call the liquid crystal electric storage means in the following text), also keep applying voltage behind the TFT of pass, keep ability in order to improve voltage, another electric storage means in parallel with the liquid crystal electric storage means can also be set, it be called " energy-storage capacitor ".Energy-storage capacitor is overlapped to form by pixel electrode 190 and adjacent gate lines 121 (claiming the leading portion gate line) thereof, for the static capacity that increases energy-storage capacitor is a stored energy capacitance, the jut 127 of expansion gate line 121 is set, handle is connected with pixel electrode 190 and is placed on below the passivation layer 180 with the overlapping electric conductor that is used for energy-storage capacitor 177 of jut 127 when enlarging overlapping area with this, and making between the two, distance diminishes.

Pixel electrode 190 and adjacent gate lines 121 and data line 171 overlapping raising aperture opening ratios, but also can be not overlapping.

The auxiliary duplicate 192,193 of contact is connected with gate line enlarged portion 125 and data line enlarged portion 179 respectively by contact hole 182,189.Whether the contact of auxiliary duplicate 192, the 199 supply gate polar curves 121 of contact and data line 171 each enlarged portion 125,179 and external device (ED) plays their effect of protection, but also nonessential, use them to vary with each individual.

Short bar connecting portion 194 is connected with them by the contact hole that exposes grid shortening bar 124 and data short bar 174.

As explanation in front, near the edge, expose and ITO, the enlarged portion 125 of the gate line 121 that the IZO contact is good, the enlarged portion 179 of data line 171, drain electrode 175 and be used for the lower layer 125 of energy-storage capacitor electric conductor 177,179,175p, 177p, contact hole 182,185,187,189 expose lower layer 125 at least, 175p, 177p, the part edge of 179p, therefore duplicate 192 is assisted in pixel electrode 190 and the contact of being made up of IZO, 199 with their

lower layer

175p, 177p, 125,179 with abundant wide area contact, can guarantee low contact impedance between them.And, contact hole 185,187,189 no incisions, pixel electrode 191 assists duplicate 199 to be connected with gate insulator 140 by contact hole 185,187,189 with contacting, so pixel electrode 191 assists duplicate 199 to have smooth side with contacting.

According to another embodiment of the present invention, pixel electrode 190 materials use transparent conducting polymer etc., and reflection LCD is also harmless with opaque reflective metal.At this moment, the auxiliary duplicate 192,199 of contact particularly can be made up of ITO and IZO by forming with pixel electrode 190 different materials.

The first embodiment method

So, describe Fig. 3 in detail and shown in Figure 4 be used for the method that the LCD thin-film transistor display panel is made according to one embodiment of the invention with reference to Fig. 5 A to Figure 12 and Fig. 3 and Fig. 4.

Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 9 A are according to thin-film transistor display panel arrangement plan in the interstage of one embodiment of the invention shop drawings 3 and thin-film transistor display panel method shown in Figure 4.Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 9 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 9 A along VB-VB ' line, VIB-VIB ' line, VIIB-VIIB ' line and IXB-IXB ' line.And Fig. 8 is the cross-sectional view of the thin-film transistor display panel shown in Fig. 7 A along VIIB-VIIB ', is to scheme Fig. 7 B next stage.Figure 11 and Figure 12 are the cross-sectional view of the thin-film transistor display panel shown in Fig. 9 A along IXB-IVB ', are to scheme Fig. 9 B next stage.Last Figure 10 shows the permutation of drain electrode and mask slits.

At first, on the insulated substrate 110 that forms by the clear glass class, deposit two metal layers in turn, i.e. lower metal layer and upper metallization layer with the sputter class.Upper metallization layer is made up of aluminium series metal such as Al-Nd alloys, preferentially has

About thickness.The sputter scale should comprise the Na of 2atm%.

Shown in Fig. 5 A and 5B,, form the gate line 121 and the grid shortening bar 124 that comprise a plurality of grids 123 and a plurality of jut 127 to upper metallization layer and lower metal layer patterning case in turn.

Shown in Fig. 6 A and 6B, successive sedimentation gate insulator 140, pure property amorphous silicon layer, impurity amorphous silicon layer trilamellar membrane, optical etching impurity amorphous silicon layer and pure property amorphous silicon layer form the linear pure property semiconductor 151 that comprises a plurality of linear extrinsic semiconductors 164 and a plurality of jut 154 respectively.The material of gate insulator 140 preferentially is a silicon nitride, and the preferential deposition temperature is 250～500 ℃, thickness for approximately

To about

Then, deposit two metal layers in turn, i.e. lower layer and upper layer with the sputter class.Preferential lower layer is made up of molybdenum, molybdenum alloy, chromium and its thickness is

About, upper layer preferentially has

Left and right thickness, scale material are fit to aluminium or comprise the Al-Nd alloy of 2atomic%Nd, and sputter temperature is preferably about 150 ℃.

Shown in Fig. 7 A and 7B, to upper layer with wet etching, to lower layer with dry ecthing patterning case or to two-layer many data lines 171, a plurality of drain electrode 175, a plurality of electric conductor 177 and the data short bar 174 that is used for energy-storage capacitor of all using wet etching patterning case to form to comprise respectively a plurality of source electrodes 173 in turn.Can the etching condition patterning case identical when lower layer 701 is molybdenum or molybdenum alloy with upper layer 702.

Then, remove not extrinsic semiconductor 164 parts that covered by gate line 171, drain electrode 175, the electric conductor 177 that is used for energy-storage capacitor and data short bar 174 and expose, expose pure property semiconductor 151 parts below it when forming a plurality of linear Ohmic contact duplicate 161 that comprises a plurality of juts 163 respectively and a plurality of island Ohmic contact duplicate 165.For stable pure property semiconductor 151 surfaces of exposing, preferentially carry out oxygen plasma subsequently.

Then, as shown in Figure 8, deposit passivation layer 180, the rotary coating photographic layer 210 in the above.Then, shown in Fig. 9 B, pass through photomask 300 video picture after photographic layer 210 irradiates lights.The photographic layer thickness that is rasterized is different because of the position, and photographic layer is by first forming to third part that thickness diminishes gradually in Fig. 9 B.The second portion of zone C 1 (to call " data contact area " in the following text) is not represented with Reference numeral 212 and 214 on the enlarged portion 179 that is positioned at the first of regional A1 and is positioned at data line 171 and drain electrode 175 parts, the third part symbol that is positioned at area B 1 on gate line 121 enlarged portion 125 (to call " gate contact region territory " in the following text) is not represented in figure, this is because the thickness of third part, has exposed the cause of leading passivation layer 180 below it near 0.The part 214 that is positioned on gate line 121 enlarged portion 125 can have and the third part same thickness.And photographic layer second portion 214 is positioned on the part of data short bar 174, and photographic layer third part or second portion 214 can be positioned on the part of grid shortening bar 124.The thickness of first 212 and second portion 214 is than different along with the condition in the subsequent handling.

Like this, the method that makes photographic layer have different-thickness because of the position can have multiple, is exactly one of them as transparent region and lightproof area not only being set on exposure mask, translucent area also being set.Being fit to slit grating, right angle grating or transmitance at translucent area is medium or thickness is medium film.When using slit grating, the resolution of exposure machine that the width of preferential slit or the gap ratio of slit are used in optical etching is little.Another example is to use the possible photographic layer that refluxes.Reflux after promptly forming the possible photographic layer that refluxes, make it to flow out, form thin part to not residual photographic layer zone with the traditional mask that has only transparent region and lightproof area.

With reference to Figure 10, mask 300 according to the present invention has a plurality of slits 310 that form photographic layer second portion 214.Slit 310 is almost the straight line form and has depressed part (or jut).Slit 310 extension that almost is parallel to each other is arranged to its Width.Preferentially, the width of each slit is about the 0.8-2.0 mu m range, and this is because if slit grating width cause the same with transparent region when to be 2.0 μ m above.Mask with this slit grating is easily with making at a low price and having a uniform repeatability.

When exposure mask 300 and substrate 110 permutations, the length direction of 175 slit 310 of being used to drain is substantially parallel on one side with drain electrode 175, at least two slits 310 are positioned at drain electrode 175 outsides, make in the slit 310 a boundary line overlapping, slit 310 depressed parts and drain electrode 175 imbricates with drain electrode 175.Part in addition, for example the slit 310 to the electric conductor 177, enlarged portion 179 and the short bar 124,174 that are used for energy-storage capacitor also carries out similar permutation.Preferentially at this moment, for viewing area drain electrode 175 and be used for the slit 310 of energy-storage capacitor electric conductor 177 and be arranged to different for the width and the spacing of the slit 310 of the enlarged portion 179 of neighboring area and short bar 124,174.This permutation method is guaranteed the permutation difference of exposure mask and the thickness difference of photographic layer second portion 214, helps even photographic layer second portion 214 thickness, and in addition the permutation method can have several between slit 310 and the related factors 175,177,179.

If proper technical conditions is provided, because of there being the thickness difference of photographic layer 212,214, so etching lower layer optionally.Therefore form a plurality of contact holes 182,185,187,189 by a series of etch phase.Second portion 214 can be positioned on all contact holes, prevent that at the contact hole 185,187,189 that exposes drain electrode 175, be used for the enlarged portion 179 of the electric conductor 177 of energy-storage capacitor and data line 171 gate insulator 140 is etched, prevent the incision of contact hole 185,187,189 with this.

For convenience of description, the part that is positioned at regional A1 is called first; Be positioned at the passivation layer 180, drain electrode 175 of data contact area C1, electric conductor 177, data line 171 and gate insulator 140 parts that are used for energy-storage capacitor are called second portion; The passivation layer 180, gate insulator 140 and gate line 121 parts that are positioned at gate contact region territory B1 are called third part.

The following describes and form this example of structure.

At first, as shown in figure 11,, passivation layer 180 and photographic layer 212,214 are carried out etching with the same etch ratio basically by the third part that the passivation layer 180 that is exposed at other area B 1 is removed in dry ecthing.This is to remove photographic layer second portion 214 or in order to dwindle its thickness for next etching process.If carry out dry ecthing, the second portion top of the third part of possible etching grid insulation course 140 and passivation layer 180, but make the third part thickness of gate insulator 140 littler than the second portion thickness of passivation layer 180, the second portion of gate insulator 140 was not removed in next stage, prevents incision.Then,, remove the photographic layer second portion 214 that remains in data contact area C1 fully, expose passivation layer 180 second portions that are positioned at drain electrode 175 tops at contact site C1 by polishing process.

As shown in figure 12, remove the third part of gate insulator 140 and the second portion of passivation layer 180 and finish contact hole 183,185,187,189.This removing used dry ecthing, and gate insulator 140 and passivation layer 180 are carried out etching with the same etch ratio basically.

Then, remove gate line 121 upper layer 125q third parts and drain electrode 175, be used for the electric conductor 177 of energy-storage capacitor and enlarged portion 179

upper layer

175q, 177q, the 179q second portion of data line 171, expose

lower layer

125p, 175p, 177p, 179p below it.

At last, as shown in Figures 1 to 4,, carry out optical etching and form a plurality of pixel electrodes 190 and a plurality of auxiliary duplicate 192,199 and short bar connecting portions 194 of contacting with sputtering sedimentation ITO or IZO.At this moment, in drain electrode 175, the electric conductor 177 and enlarged portion 125,179 bottoms that are used for energy-storage capacitor incision not taking place, can slowly form the side of pixel electrode 190 and the auxiliary duplicate 192,199 of contact.And, pixel electrode 191 and the auxiliary duplicate 192,199 of contact between IZO or ITO layer with have the lower layer 125,179 of low-impedance gate line 121 and data line 171 and drain 175 and the electric conductor 177 lower layer 175p, the 177p that are used for energy-storage capacitor join, reduced the contact impedance of contact site.

Like this, not only comprise aluminum or aluminum alloy according to gate line 121 in the thin-film transistor display panel of present embodiment and data line 171, can also make the contact impedance between the auxiliary duplicate 192,199 of these signals and pixel electrode 190 and contact become minimum with low-resistivity.And the side of the auxiliary duplicate 192,199 of contact becomes smooth, therefore improved the contact reliability between they and the external drive circuit chip.

Second example structure

Describe the thin-film transistor display panel that is used for LCD according to another embodiment of the present invention in detail with reference to Figure 13 to Figure 15.

Figure 13 is used for LCD thin-film transistor display panel arrangement plan according to another embodiment of the present invention, and Figure 14 and Figure 15 are respectively thin-film transistor display panel shown in Figure 13 cross-sectional view along XIV-XIV ' line and XV-XV ' line.

Omitted extension shown in Figure 3 126,176 for convenience.

To shown in Figure 15, probably identical as Figure 13 with Fig. 3 and the thin-film transistor display panel layer structure that is used for LCD shown in Figure 4 according to the thin-film transistor display panel layer structure that is used for LCD of the embodiment of the invention.Promptly, on substrate 110, form many gate lines 121 comprise a plurality of grids 123, form gate insulator 140 on it in turn, comprise a plurality of linear semiconductor 151 of a plurality of juts 154, comprise a plurality of linear Ohmic contact duplicate 161 and a plurality of island Ohmic contact duplicate 165 of a plurality of juts 163 respectively.Form many data lines 171, a plurality of drain electrode 175 that comprises a plurality of source electrodes 153 at Ohmic contact duplicate 161,165 and above the gate insulator 140, form passivation layer 180 on it.Form a plurality of contact holes 182,185,189 at passivation layer 180 and/or gate insulator 140, form a plurality of pixel electrodes 190 and a plurality of duplicates 192,199 that contact on the passivation layer 180.

But different with Fig. 3 and thin-film transistor display panel shown in Figure 4, do not have jut and a plurality of storage electrode lines 131 of separating with gate line 121 electricity in gate line 121 identical layer settings according to the thin-film transistor display panel gate line 121 of the embodiment of the invention.Storage electrode line 131 also comprises lower layer 131p and upper layer 131q as gate line 121.Storage electrode line 131 receives the quota voltage of common voltage and so on from the outside.Fig. 3 and the electric conductor that is used for energy-storage capacitor 177 shown in Figure 4 are not set, overlap to form energy-storage capacitor with storage electrode line 131 but prolong drain electrode 175.If the stored energy capacitance of pixel electrode 190 and gate line 121 overlapping generations can omit storage electrode line 131 and be used for the electric conductor 177 of energy-storage capacitor when sufficient.

And contact hole 182,189 does not all expose gate line 121 and data line 179 enlarged portion 125,179 and only exposes their part, the part of therefore remaining

upper layer

125q, 179q.

If semiconductor 151, has the plane configuration substantially the same with the Ohmic contact duplicate 161,165 of data line 171, drain electrode 175 and its underpart so except the jut 154 at TFT place.That is, linear semiconductor 151 except data line 171 and drain 175 and its underpart Ohmic contact duplicate 161,165 below the part that exists, also have in source electrode 173 and the part that drains and do not stopped between 175 and expose by them.

The second embodiment method

Describe with reference to Figure 16 A to Figure 25 B and Figure 13 to Figure 15 so that manufacturing has the method for the thin-film transistor display panel that is used for LCD of Figure 13 to Figure 15 structure according to one embodiment of the invention in detail.

Figure 16 A is according to thin-film transistor display panel arrangement plan in the phase one of one embodiment of the invention manufacturing Figure 13 thin-film transistor display panel method extremely shown in Figure 15; Figure 16 B and Figure 16 C are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 16 A along XVIB-XVIB ' line and XVIC-XVIC ' line; Figure 17 A and Figure 17 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 16 A along XVIB-XVIB ' line and XVIC-XVIC ' line, are to scheme Figure 16 B and Figure 16 C next stage; Figure 18 A is the thin-film transistor display panel arrangement plan of Figure 17 A and Figure 17 B next stage; Figure 18 B and Figure 18 C are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 18 A along XVIIIB-XVIIIB ' line and XVIIIC-XVIIIC ' line; Figure 19 A, Figure 20 A, Figure 21 A and Figure 19 B, Figure 20 B, Figure 21 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 18 A along XVIIIB-XVIIIB ' line and XVIIIC-XVIIIC ' line, are by the B of Figure 18 shown in the operation and Figure 18 C next stage; Figure 22 A is the thin-film transistor display panel arrangement plan of Figure 21 A and Figure 21 B next stage; Figure 22 B and Figure 22 C are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 22 A along XXIIB-XXIIB ' line and XXIIC-XXIIC ' line; Figure 23 A, Figure 24 A, Figure 25 A and Figure 23 B, Figure 24 B and Figure 25 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 22 A along XXIIB-XXIIB ' line and XXIIC-XXIIC ' line, are to scheme Figure 22 B and Figure 22 C next stage.

At first shown in Figure 16 A to Figure 16 C, on insulated substrate 110, form many gate lines 121 that comprise a plurality of grids 123 respectively, many storage electrode lines 131 and grid shortening bar 124 with the optical etching engineering.Gate line 121 and storage electrode line 131 comprise

lower layer

121p, 131p and

upper layer

121q, 131q respectively with grid shortening bar 124.

Shown in Figure 17 A and 17B, utilize chemical vapor deposition method respectively with about

Extremely

Approximately

Extremely

Approximately

Extremely

Thickness successive sedimentation gate insulator 30, pure property amorphous silicon layer 150, impurity amorphous silicon layer 160.Then, form approximately with sputter class methods successive sedimentation lower layer 170p and upper layer 170q

To about

After the conductor layer 170 of thickness, thereon with 1 μ m to 2 μ m thickness photosensitive coated layer 310.

Then, by photomask video picture after photographic layer 310 irradiates lights.The photographic layer thickness of video picture is different because of the position, at the photographic layer of Figure 18 B and Figure 18 C by first forming to third part that thickness diminishes gradually.Be positioned at regional A2 (to call " wiring zone " in the following text) first and be positioned at zone C 2 (to call " passage area " in the following text) second portion and do not represent with Reference numeral 52 and 54, be positioned at symbol not expression in figure of area B 2 (to call " other zone " in the following text) third part, this is because third part thickness becomes 0, exposes the cause of conductor layer 170 below it.

If suitable engineering specifications is provided, because of there is thickness difference in photographic layer 312 314, so can the selective etch lower layer.Then form many data lines 171, a plurality of drain electrode 175 and the data short bar 174 that comprises a plurality of source electrodes 173 respectively by a series of etch phase, form a plurality of linear Ohmic contact duplicate 161 and a plurality of island Ohmic contact duplicate 165 that comprise a plurality of juts 163 respectively, also form a plurality of linear semiconductor 151 that comprises a plurality of juts 154.

For convenience of description, the conductor layer 170, impurity amorphous silicon layer 160, pure property amorphous silicon layer 150 parts that are positioned at the regional A2 of wiring are called first, be positioned at conductor layer 170, the impurity amorphous silicon layer 160 of passage area C2, the part of pure property amorphous silicon layer 150 is called second portion, is positioned at conductor layer 170, the impurity amorphous silicon layer 160 of other area B 2, the part of pure property amorphous silicon layer 150 is called third part.

The order that forms this structure is exemplified below:

(1) removes the third part of the conductor layer 170 that is positioned at other area B, impurity amorphous silicon layer 160, amorphous silicon layer 150.

(2) remove the photographic layer second portion 314 that is positioned at passage area.

(3) remove the conductor layer 170 that is positioned at passage area C and the second portion of impurity amorphous silicon layer 160.

(4) remove the photographic layer first 312 that is positioned at the regional A of wiring.

Another of this order is for example following:

(1) removes conductor layer 170 third parts that are positioned at other area B.

(2) remove the photographic layer second portion 314 that is positioned at passage area C.

(3) remove the impurity amorphous silicon layer 160 that is positioned at other area B and the third part of amorphous silicon layer 150.

(4) remove conductor layer 170 second portions that are positioned at passage area C.

(5) remove the photographic layer first 312 that is positioned at the regional A of wiring.

(6) remove impurity amorphous silicon layer 160 second portions that are positioned at passage area C.

First example here is described.

At first, shown in Figure 19 A and 19B,, expose impurity amorphous silicon layer 160 third parts below it with the third part that the conductor layer 170 that is exposed at other area B 2 is removed in wet etching or dry ecthing.In the conductor layer 170, comprise that the conducting film of one of Mo or MoW alloy, Al or Al alloy, Ta can be with dry ecthing or wet etching.But can not remove Cr fully with dry-etching method, therefore if lower layer 701 only utilizes wet etching better when being Cr.When lower layer 701 is the wet etching of Cr, can use CeNHO ₃Etching solution; When lower layer 701 is the dry ecthing of Mo or MoW, can use CF ₄With HCl mixing etching gas or CF ₄With O2 mixing etching gas, the latter to the etching of photographic layer than similar.

Reference numeral 178 refers to data line 171 and drain electrode 175 electric conductors that also are attached to together.Because the use dry ecthing, so photographic layer 312,314 tops may be by the certain thickness attenuation.

Shown in Figure 20 A and Figure 20 B, remove passage area C2 photographic layer second portion 314 when removing pure property amorphous silicon layer 150 third parts of the impurity amorphous silicon layer 160 that is positioned at other area B 2 and its underpart, expose following electric conductor 178 second portions.Remove the photographic layer second portion and remove impurity amorphous silicon 160 and pure property amorphous silicon layer 150 third parts are carried out simultaneously or carried out respectively.For example use SF ₆With the mixed gas of HCl, SF ₆And O ₂Mixed gas, can be two-layer with thickness etching much at one.Remove the residue that remains at passage area C2 second portion 314 with polishing.

Form linear pure property semiconductor 151 in this stage.Reference numeral 164 refers to that linear Ohmic contact duplicate 161 and island Ohmic contact duplicate 165 also are attached to linear impurity amorphous silicon layer 160 together, call it (linear) extrinsic semiconductor later on.

Then, shown in Figure 21 A and Figure 21 B, the electric conductor 178 that is positioned at passage area C2 and the second portion of linear extrinsic semiconductor 164 are removed in etching.Also remove remaining photographic layer first 312.

At this moment, can only carry out dry ecthing to electric conductor 178 and extrinsic semiconductor 164.

Different therewith, can be to electric conductor 178 usefulness wet etchings, extrinsic semiconductor 164 is used dry ecthing.At this moment, the side of the electric conductor 178 of usefulness wet etching is etched, but almost not etched with the extrinsic semiconductor 168 of dry ecthing, therefore forms stepped.For example; Use SF ₆And O ₂The mixed gas etching is used for the electric conductor 178 of source/drain.If use CF ₄And O ₂, can be left thickness homogeneous semiconductor 152.

At this moment, shown in Figure 21 B, remove linear pure property semiconductor 151 juts 154 upper parts that are positioned at passage area C2, can reduce thickness; Also there is etching to a certain degree in photographic layer first 312.

So, each electric conductor 178 is divided into a data line 171 and a plurality of drain electrode 175 and finishes it, and each extrinsic semiconductor 164 is divided into a linear Ohmic contact duplicate 161 and a plurality of island Ohmic contact duplicate 165 and finishes it.

Then, shown in Figure 22 A to 22C, deposit passivation layer 180, rotary coating photographic layer thereon.Then, by photomask (not shown) video picture after the photographic layer irradiates light.The photographic layer thickness of video picture is different because of the position, at the photographic layer of Figure 22 B by first forming to third part that thickness diminishes gradually.Be positioned at the first and the second portion that is positioned at the data contact area C3 on data line 171 enlarged portion 179 and drain electrode 175 parts of regional A3, represent with Reference numeral 412,414 respectively; The third part that is positioned at the gate contact region territory B3 on gate line 121 enlarged portion 125 do not represent with Reference numeral, and this is because third part thickness becomes 0, exposes the cause of passivation layer 180 below it.The thickness beguine of first 412 and second portion 414 is decided according to the process conditions in the subsequent handling.

If suitable engineering specifications is provided, because of there is thickness difference in photographic layer 412,414, so can the selective etch lower layer.Then form contact hole 182,185,187,189 by a series of etch phase.

For convenience of description, the part that is positioned at regional A3 is called first, the part that is positioned at passivation layer 180, drain electrode 175, data line 171 and the gate insulator 140 of data contact area C3 is called second portion, and the part that is positioned at passivation layer 180, gate insulator 140 and the gate line 121 of gate contact region territory B3 is called third part.

Illustrate and form this example of structure.

At first, shown in Figure 23 A and 23B, passivation layer 180 third parts that are exposed at gate contact region territory B3 are removed in etching.If carry out dry ecthing, possible etching grid insulation course 140 third parts and passivation layer 180 second portion tops, but make the thickness of gate insulator 140 third parts littler, gate insulator 140 second portions were not removed in next stage than passivation layer second portion thickness.Then, remove the photographic layer second portion 414 that remains in data contact area C3 fully, expose passivation layer 180 second portions that are positioned at drain electrode 175 tops by polishing process.

Shown in Figure 24 A and Figure 24 B, remove gate insulator 140 third parts and passivation layer 180 second portions are finished contact hole 182,185,189.This etching dry ecthing is carried out etching with the same etch ratio basically to gate insulator 140 and passivation layer 180.Like this, gate insulator 140 third parts are thinner than passivation layer 180 second portions, keep gate insulator 140 second portions when therefore removing gate insulator 140 third parts and passivation layer 180 second portions fully, with these 175 following gate insulator 140 incisions that prevent to drain.

Shown in Figure 25 A and Figure 25 B, remove after the photographic layer 412,414, remove third part and drain electrode 175 and the second portion of data line 171 enlarged portion 179

upper layer

175q, 179q of gate line 121 upper layer 125q, expose

lower layer

125p, 175p, 179p below it.

At last,, deposit to shown in Figure 15 as Figure 13 with sputtering method

Extremely

The ITO of thickness or IZO also carry out optical etching, form a plurality of pixel electrodes 190, the auxiliary duplicate 192,199 of a plurality of contact and short bar connecting portion 194.IZO preferentially uses HNO ₃/ (NH ₄) ₂Ce (NH ₃) ₆/ H ₂O etc. are used for the wet etching of chromium etching solution, and this etching solution does not corrode aluminium, can prevent the corrosion of data line 171, drain electrode 175 and gate line 121.

Form data line 171 with optical etching operation in the present embodiment and drain 175 and the Ohmic contact duplicate 165,165 and the semiconductor 151 of its underpart, can simplify manufacturing process with this.

The 3rd example structure

Describe the method that is used for the LCD thin-film transistor display panel according to another embodiment of the present invention in detail with reference to Figure 26 and Figure 27.

Figure 26 is the thin-film transistor display panel arrangement plan that is used for LCD according to another embodiment of the present invention, and Figure 27 is a thin-film transistor display panel shown in Figure 26 cross-sectional view along XXVII-XXVII ' line.

As Figure 26 and shown in Figure 27, probably identical with Fig. 3 and the thin-film transistor display panel layer structure that is used for LCD shown in Figure 4 according to the thin-film transistor display panel layer structure that is used for LCD of the embodiment of the invention.Promptly, on substrate 110, form many gate lines 121 comprise a plurality of grids 123, on form gate insulator 140 in turn, comprise a plurality of linear semiconductor 151 of a plurality of juts 154, comprise a plurality of linear Ohmic contact duplicate 161 and a plurality of island Ohmic contact duplicate 165 of a plurality of juts 163 respectively.Form many data lines 171, a plurality of drain electrode 175 that comprises a plurality of source electrodes 153 on Ohmic contact duplicate 161,165 and the gate insulator 140, form passivation layer 180 on it.Form at passivation layer 180 and/or gate insulator 140 and to expose a plurality of contact holes 182,189 of gate line 121 and data line 171 enlarged portion 125,179, and form a plurality of pixel electrodes 190 and contact auxiliary duplicate 192,199 with a plurality of.

But different with Fig. 3 and thin-film transistor display panel shown in Figure 4, comprise a plurality of parts of extending along data line 171 and be positioned near gate line 121 enlarged portion 125 a plurality of parts according to the passivation layer 180 of the thin-film transistor display panel of present embodiment.Passivation layer 180 covers a data line 171 and drain electrode 175 parts that comprise source electrode 173, and the remainder of drain electrode 175 is not passivated layer 180 with the electric conductor 177 that is used for energy-storage capacitor and covers.

And a plurality of island semiconductors 157 and following a plurality of island contact duplicates 167 thereof are formed between the electric conductor 177 and gate insulator 140 that is used for energy-storage capacitor with linear semiconductor 151 and Ohmic contact duplicate 161,165.

Semiconductor 151,157 is except the jut 154 at TFT place, has the plane configuration substantially the same with data line 171, drain electrode 175, the electric conductor 177 that is used for energy-storage capacitor and its underpart Ohmic contact duplicate 161,165,167 so.Specifically, island semiconductor 157 has identical plane configuration basically with electric conductor 177 that is used for energy-storage capacitor and island Ohmic contact duplicate 167.Different therewith, linear semiconductor 151 not only have data line 171 and drain 175 and the part that below the Ohmic contact duplicate 161,165 of its underpart, exists outside, also have in source electrode 173 and the part that drains and do not stopped between 175 and expose by them.The major part of pixel electrode 191 is located immediately on the gate insulator 140, the part of pixel electrode 191 is located immediately at drain electrode 175 exposed portions serve 175 and is used on electric conductor 177 parts of energy-storage capacitor, and is electrically connected with drain electrode 175 and the electric conductor 177 that is used for energy-storage capacitor.

The 3rd embodiment method

Describe with reference to Figure 28 A to Figure 32 and Figure 26 to Figure 27 so that manufacturing has the method for the thin-film transistor display panel that is used for LCD of Figure 26 to Figure 27 structure according to one embodiment of the invention in detail.

Figure 28 A, Figure 29 A and Figure 30 A make thin-film transistor display panel arrangement plan in the thin-film transistor display panel method interstage shown in Figure 27 according to one embodiment of the invention, Figure 28 B, Figure 29 B and Figure 30 B are respectively the cross-sectional view of the thin-film transistor display panel shown in Figure 28 A, Figure 29 A and Figure 30 A along XXVIIIB-XXVIIIB ' line, XXIXB-XXIXB ' and XXXB-XXXB ' line, Figure 31 and Figure 32 are the cross-sectional view of the thin-film transistor display panel shown in Figure 30 A along XXXB-XXXB ' line, and it is the next stage figure shown in Figure 30 B.

At first, shown in Figure 28 A and Figure 28 B, on insulated substrate 110, deposit with the sputter class methods

Extremely

The metal species conductor layer of thickness carries out dry ecthing or wet etching and forms many gate lines 121 and the grid shortening bar 124 that comprises a plurality of grids 123 respectively.

Shown in Figure 29 A and Figure 29 B, about respectively with the chemical vapor deposition method successive sedimentation

Extremely

Approximately

To about

Approximately

Approximately

The gate insulator 140 of thickness, pure property amorphous silicon layer 150, impurity amorphous silicon layer 160.Then, with sputter class methods successive sedimentation lower layer 170p and upper layer 170q, form approximately

To about

After the conductor layer 170 of thickness, to conductor layer 170 and following impurity amorphous silicon layer 160 patterning cases thereof, form many data lines 171, a plurality of drain electrode 175, a plurality of electric conductor 177 of energy-storage capacitor and the Ohmic contact duplicate 163,165,167 of data short bar 171 and their bottoms of being used for that comprise a plurality of source electrodes 173.

Then, shown in Figure 30 A and Figure 30 B, deposit approximately by the chemical vapor deposition of silicon nitride or the rotary coating of organic insulation The passivation layer 180 of above thickness, rotary coating photographic layer thereon.Then, by photomask (not shown) video picture after the photographic layer irradiates light.The photographic layer thickness of video picture is different because of the position, and photographic layer is by first forming to third part that thickness diminishes gradually in Figure 30 B.Be positioned at the first of first area A4 and be positioned at the enlarged portion 179 of data line 171 and drain electrode 175 parts on the second portion of second area C4 do not represent with Reference numeral 512 and 514, the third part that is positioned at the 3rd area B 4 on gate line 121 enlarged portion 125 is not represented with Reference numeral, this is because the thickness of third part is 0, has exposed the cause of passivation layer 180.The thickness ratio of first 512 and second portion 514 is different because of the engineering specifications in the middle of the subsequent handling.Be necessary to remove and be positioned at viewing area and neighboring area pure property amorphous silicon layer 150 with exterior domain, at this moment being positioned at this regional photographic layer part (not shown) can be different with second portion 514 thickness, and this can realize by the slit width and the slit separation that change exposure mask.

Provide proper technical conditions, because of there being the thickness difference of photographic layer 512,514, so can the selective etch lower layer.Therefore form passivation layer 180 by a series of etch phase with a plurality of contact holes 182,189 and a plurality of transistor Ts.

For convenience of description, the part that is positioned at regional A4 claims first, the part that is positioned at passivation layer 180, drain electrode 175, data line 171, pure property amorphous silicon layer 150 and the gate insulator 140 of second area C4 claims second portion, is positioned at three parts that the part of the passivation layer 180 of the 3rd area B 4, pure property amorphous silicon layer 150, gate insulator 140 and gate line 121 claims.

Illustrate and form this example of structure.

At first, as shown in figure 31, use SF ₆+ N ₂Or SF ₆Mixed gass such as+HCl carry out dry ecthing and remove the passivation layer 180 that the 3rd area B 4 exposes and the third part of pure property amorphous silicon layer 150, first and second part 512,514 of the photographic layer of etching simultaneously.Gate insulator 140 third parts also may preferentially, be regulated the photographic layer consumption by together etching, make passivation layer 180 second portions be unlikely to expose.

By using N ₆+ O ₂Or Ar+O ₂Remove the second portion 514 of the photographic layer that remains in second area C4 fully Deng the polishing process of mixed gas, expose the second portion of the passivation layer 180 that is positioned at drain electrode 175 tops.

Shown in figure 32, the second portion of removing the third part of gate insulator 140 and passivation layer 180 expose gate line 121 third part, be used for the electric conductor 177 of energy-storage capacitor, second portion, data line 171 and the pure property amorphous silicon layer 150 of drain electrode 175.Use the etching condition that pure property amorphous silicon layer 150 and gate insulator 140 and passivation layer 180 are had an outstanding etching selectivity to carry out etching in the etching of using when removing these parts.Then, use Cl ₂+ O ₂Or SF ₆+ HCl+O ₂Mixed gas etchings such as+Ar are also removed the second portion that pure property amorphous silicon layer exposes, thereby finish linear or island semiconductor 151,157 and transistor T.

Remove after the photographic layer 512,514, remove gate line 121 enlarged portion 125 upper layer 125q third part and drain electrode 175, be used for the second portion of the electric conductor 177 of energy-storage capacitor and data line 171 enlarged portion

upper layer

175q, 177q, 179q, expose

lower layer

125p, 175p, 177p, 179p below it.

At last, as Figure 26 and shown in Figure 27, approximately with the sputtering method deposition To about

The ITO of thickness or IZO carry out optical etching, form a plurality of pixel electrodes 190, the auxiliary duplicate 192,199 of a plurality of contact and short bar connecting portion 194.

The 4th example structure

Describe the thin-film transistor display panel that is used for LCD according to another embodiment of the present invention in detail with reference to Figure 33 and Figure 34.

Figure 33 is the arrangement plan of thin-film transistor display panel according to another embodiment of the present invention, and Figure 34 is a thin-film transistor display panel shown in Figure 33 cross-sectional view along XXXIV-XXXIV ' line.

Omit extension shown in Figure 3 126,176 for convenience.

As Figure 33 and shown in Figure 34, probably identical with Fig. 3 and thin-film transistor display panel layer structure shown in Figure 4 according to the thin-film transistor display panel layer structure of present embodiment.Promptly, on substrate 110, form many gate lines 121 comprise a plurality of grids 121 and a plurality of enlarged portion 127 respectively, on form in turn gate insulator 140, respectively comprise a plurality of linear semiconductor 151 of a plurality of juts 154, comprise a plurality of linear Ohmic contact duplicate 161 and a plurality of island Ohmic contact duplicate 165 of a plurality of juts 163 in addition.Form many data lines 171, a plurality of drain electrode 175, a plurality of electric conductor 177 that is used for energy-storage capacitor that comprises a plurality of source electrodes 153 on the Ohmic contact duplicate 161,165 respectively, form passivation layer 180 on it.On passivation layer 180 and/or gate insulator 140, form a plurality of contact holes 182,185,187,189, form a plurality of pixel electrodes 190 on the passivation layer 180 and assist duplicate 192,199 with a plurality of the contact.

Different with Fig. 3 and thin-film transistor display panel shown in Figure 4, a plurality of red, green, blue or green color filter R, G, B are formed on below the passivation layer 180.Color filter R, G, B have a plurality of peristome C1, the C2 that exposes drain electrode 175 and be used for the electric conductor 177 of energy-storage capacitor.Here, the border of color filter R, G, B is overlapped, has the function that stops that light is revealed, and contact hole 185,187 is positioned at the inboard of color filter R, G, B peristome C1, C2.Different therewith, peristome C1, C2 and contact hole 185,187 can have stepped side walls.

And contact hole 182,189 spills enlarged portion 125,179 part of gate line 121 and data line 179 rather than all, therefore the part of remaining

upper layer

125q, 179q also.

Prevent according to the present invention like this that when contact site exposes the cloth line boundary incision, the side that can slowly guarantee contact site take place in the wiring bottom.Can prevent to break by it, can stablize the installation drive integrated circult, therefore, can guarantee the reliability of contact site at contact site.And the conductive layer that exposes low contact impedance forms contact site, thereby makes the contact site contact impedance become minimum.

And, form the wiring that comprises low-impedance aluminum or aluminum alloy, conductive layer, can improve the characteristic of large-screen high-resolution product with this.Also have, simplify manufacturing process and make the thin-film transistor display panel that is used for LCD, therefore can simplify manufacturing process, reduce manufacturing expense.

And, according to the embodiment of the invention, when contact site or cushion part are exposed the cloth line boundary, for preventing that the signal wire bottom from producing incision, or in order to reduce manufacturing expense to greatest extent and to form the interior thickness photographic layer, utilize mask to form it, and mask fabrication get up to want easily with straight line form and 0.8-2 mu m range slit grating, can with uniformly again dominance form photoresist, can reduce manufacturing expense by bottom line.

In addition, append concaveconvex structure for the mask slits grating, the boundary line of permutation signal wire and slit grating make them overlapping, the photographic layer that exposes then, thus can form the part that has interior thickness in the photoresist with uniform thickness.

As mentioned above, want the insulation course of residual drain electrode bottom when contact portion is exposed drain edge, in case the incision at stop signal line place, and prevent that the profile of contact portion from polishing, thus the broken string of pixel electrode prevented.In addition, expose conductive film, to guarantee the reliability of contact portion with low contact resistance.In addition, formation comprises that low-resistance upper film is to improve the quality of product.And, can simplified manufacturing technique.

Though the present invention is described with the preferred embodiments, be to be understood that the present invention is not limited to these preferred specific embodiments, those skilled in the art can carry out various substitutions and modifications in the spirit and scope of claims.

Claims

1. the manufacture method of a thin-film transistor display panel, described method comprises:

On insulated substrate, form gate line;

Form gate insulator;

Form semiconductor;

Formation comprises the data conductive layer of data line and drain electrode;

Form passivation layer, described passivation layer has a part of exposing described drain electrode and abuts against the contact hole of a part of upper surface of the described gate insulator of described grain boundaries line; And

Form the pixel electrode that is connected with described drain electrode by described contact hole,

Wherein, described pixel electrode by the contact hole in the described passivation layer and described drain electrode upper surface and the part of upper surface that abuts against the described gate insulator of described grain boundaries line contact.

2. method according to claim 1, it is characterized in that, use mask by the optical etching operation come in described semiconductor of patterning and the described passivation layer at least one, described mask comprise the impervious first area of light, can be through the second area of a part of light and the 3rd zone that light sees through fully.

3. method according to claim 2, it is characterized in that, form photoresist in described optical etching operation, described photoresist comprises and is positioned at the first in described data line and the described drain electrode first and is positioned at second portion on the described drain electrode second portion, is positioned at the third part on the described gate line end portion; Described photoresist second portion is thinner than described photoresist first, and described photoresist third part is thinner than described photoresist second portion.

4. method according to claim 3 is characterized in that: described photoresist also be included on the described data line end portion and the thickness that has than the 4th little part of described photoresist first's thickness.

5. method according to claim 4 is characterized in that: also comprise:

Utilize described photoresist to carry out etching, to expose the described passivation layer part below the second and the 4th part that is positioned at described photoresist and to be positioned at the part of the described gate insulator below the third part of described photoresist; And

Remove the exposed portions serve of described passivation layer and the exposed portions serve of described gate insulator, expose the contact hole of described data line end portion and described gate line end portion with formation.

6. method according to claim 5, it is characterized in that, the described second area of described mask comprise with corresponding first slit of described photic etchant second portion and with corresponding second slit of described photic etchant the 4th part, described first slit has different width and spacing with described second slit.

7. method according to claim 4 is characterized in that: come at least one the step in described semiconductor of patterning and the described passivation layer to comprise by the optical etching operation:

On described gate insulator, deposit semi-conductor layer;

Deposition one insulation course on described data conductive layer;

On described insulation course, form described photoresist;

Utilize described photoresist to carry out etching, the part of the described gate insulator below the third part of exposing described passivation layer part below the second and the 4th part that is positioned at described photoresist and described photoresist;

Remove the exposed portions serve of described passivation layer and the exposed portions serve of described gate insulator, expose the contact hole and the described semiconductor layer of exposed portions serve of described data line end portion and described gate line end portion with formation; And

Remove the exposed portions serve of described semiconductor layer, to form described semiconductor.

8. method according to claim 7 is characterized in that: a plurality of semiconductor portions that described semiconductor comprises between adjacent data line and is separated from each other.

9. method according to claim 7 is characterized in that: described thin-film transistor display panel comprises viewing area that described gate line and described data line intersect and the neighboring area that is provided with described gate line end portion and described data line end portion; Described slit is included in first slit and second slit in all the other zones in described viewing area and the described neighboring area, and described first slit has different width and spacing with described second slit.

10. according to the method for claim 1, it is characterized in that at least one in described gate line and the described data conductive layer comprises by at least a lower conducting layer that constitutes in chromium, molybdenum and the molybdenum alloy and by at least a top conductive layer that constitutes in aluminium and the aluminium alloy.

11. method according to claim 10 is characterized in that: described drain electrode comprises described lower conducting layer and described top conductive layer, and described method also comprises:

Before forming described pixel electrode, remove the described top conductive layer of at least a portion of described drain electrode.

12. method according to claim 2 is characterized in that, the described mask of permutation makes that the boundary line of the part of second area of described mask and described drain electrode is overlapping.

13. method according to claim 2 is characterized in that, the second area of described mask comprises one or more slits, and wherein, at least one described slit has depression.

14. method according to claim 2 is characterized in that, the second area of described mask comprises one or more slits, and wherein, the described mask of permutation makes that at least two in the described slit are positioned at outside the described drain electrode.

15. method according to claim 2 is characterized in that, described second area is provided with one or more slits.

16. method according to claim 15 is characterized in that, described one or more slits comprise a plurality of slits that are essentially the straight line form, and the width of each slit and the spacing between the slit arrive within about 2.0 micrometer ranges at about 0.8 micron.

17. method according to claim 1 is characterized in that, at least one in described gate line and the described data conductive layer comprises at least a in chromium, molybdenum, molybdenum alloy, aluminium and the aluminium alloy.