CN1016552B - Method of transmitting writing broadcast signal and apparatus of receiving same - Google Patents

Abstract

The present invention is a transmission method and a receiving device of PAL standard text broadcasting. The transmission method is: to generate a clock pulse signal for a text signal that has a simple frequency-modulation relationship with the PAL standard TV signal color sub-carrier, and set the clock pulse length of a block signal to 272 bits, and the same error correction symbols as the Japanese standard can be applied (272, 190). The receiving device is: take out the color sub-carrier signal from the PAL standard TV signal, and use the APC circuit to generate a signal with the same frequency and phase as the clock pulse series signal for text broadcasting from this signal, and use it as a clock pulse signal to count the first TV signal The scanline number of the field, meanwhile. In the case of multi-channel text signals, the framing code is detected, and the device for regenerating the time stamp of the frame code is protected from the front and rear.

Description

The present invention belongs to the transmission mode of text broadcasting signal and its receiving device, in particular to the transmission mode and its receiving device of PAL standard text broadcasting with strong error correction capability.

The so-called text broadcasting is to transmit multiple signals in the TV wave, broadcast the text and simple graphics and other information about TV programs and display them on the cathode ray tube screen.

In the past, PAL text broadcasting adopted the British system called System B in CCIR. This standard does not pay much attention to error correction, so it is not suitable for receiving systems in places where receiving conditions are very strict or for receiving systems in countries that use ideographic characters like China.

As for the Japanese standard, error correction has been developed as the most important content since the system was developed, and a system with strong error correction capability has been completed due to the use of (272, 190) symbols.

In this Japanese system, the continuity of the clock pulse signal and the phase of the framing code are maintained between each block, so under normal circumstances, the reception of the framing code is very weak, and the following (272, 190) It is impossible to give full play to the error correction ability of the symbol, but due to the front protection and the rear protection, the time mark of the framing code is detected, and the error correction ability of the (272, 190) symbol can be exerted.

Due to impulse noise and random noise, detection errors also occur on the framing code, but the framing timing can also be ensured as long as the detection errors do not occur continuously.

In foreign systems such as the United Kingdom, since the signal processing is only performed in one block, there is no simple frequency relationship between the clock pulse frequency and the color sub-carrier frequency, and an error occurs in the framing code and the framing time scale cannot be extracted. In this case, all the signals in the block will be lost. Moreover, as far as error correction symbols are concerned, for important symbols or program selection symbols, energy The (8,4) enlarged symbols capable of correcting 1 out of 8 bit errors are used; while for the other symbols, only error detection symbols capable of detecting 1 out of 8 bit errors are used.

Therefore, there is a problem that wrong characters and important information are not transmitted in places where reception conditions are very severe.

The disadvantages of the above-mentioned PAL textcasting are described in detail below.

Multi-channel text broadcasting is carried out in the PAL standard TV signal, and there is a text broadcast called "Ceefax" developed in the United Kingdom. As shown in Figure 6, in this method, at a bit rate of 6.9375Mbps, the text broadcasting signal is used as a block of 360 bits for multiplexing, and the first 16 bits are used as a clock pulse series signal for bit synchronization. The 8 bits are a framing signal of a prescribed pattern that identifies where the signal is disconnected, and 336 bits are the information portion. So exactly 444 bits during 1 row.

In the British system, there is no direct frequency relationship between the clock frequency and the color sub-carrier. Although there is a certain frequency relationship between the clock pulse frequency and the horizontal synchronization signal frequency, because ① the gain of the APC circuit is not utilized, ② the horizontal synchronization time scale after vertical synchronization is prone to subtle phase jumps, so the clock pulse is regenerated from the horizontal synchronization signal Signaling is difficult.

For the above reasons, Ceefax adopts a receiving method in which signal processing is performed within one block regardless of the frequency relationship with the TV signal. Therefore, as a transmission signal, it is not necessary to match the phases of the first bits of the block signal in each row, and there is no problem in performing multiplexing with various phases.

That is: at the receiving end, use the first 16 bits of the block signal as clock pulse synchronization to extract the framing pattern. When there is one bit error in the framing pattern, it is still possible to extract the time mark, but when there is a two-bit error, the extraction of the time mark is impossible, and all the signals of this word group cannot be used.

Compared with the Japanese system in which framing code reception is performed based on front protection and rear protection, Ceefax mentioned above has a big disadvantage of weak reception of framing codes. In the case of low reception capability of the framing code, the error correction capability of subsequent signals will of course not be very strong.

As mentioned above, Ceefax does not take error correction into consideration, and only adds 1 bit of parity to 7-bit symbols for text symbols after framing codes, and does not have an error detection function.

As mentioned above, the PAL standard TV multi-channel text broadcasting (Ceefax) has a very weak ability to correct bit errors. It has a lot of information for ideographic transmission systems such as Japanese or Chinese, and a large number of important information transmission systems. Information transmission systems (such as telex software for transmitting computer programs), etc. are not suitable.

The purpose of the present invention is to provide a transmission method and a receiving device for improving the error correction ability of PAL text broadcasting.

In order to achieve the above object, the characteristics of the transmission method of the present invention are: extract the color sub-carrier signal from the PAL TV signal, produce a clock pulse signal for the text signal that is in a simple integer ratio with the signal, and then start from a specific vertical blanking period , the following 296-bit signals are transmitted sequentially: a series of 16-bit clock pulses as clock pulse synchronization, an 8-bit framing code as a framing time stamp, 190 bits of information, and an 82-bit parity signal calculated from this information.

The receiving device has: a regeneration device that regenerates a signal having the same frequency as the text signal from the color burst signal, and a signal that regenerates a signal that is in phase with the multi-channel clock pulse series; detects the framing code, and uses the signal at a certain time scale The protection device with multi-channel framing codes for front and rear protection processing can also receive framing codes in the event of receiving errors.

As mentioned above, the present invention has adopted the clock pulse signal that has the same frequency relationship with the color sub-carrier of the PAL system television signal, and has kept the continuity of the clock pulse signal, In one line of the PAL signal, the clock pulse frequency is the same (272, 190) symbols as the Japanese text broadcasting, so it has the same powerful error correction capability as the Japanese text broadcasting.

Brief description of the attached drawings:

Figure 1 is a block diagram of the circuit for generating the television signal of the present invention.

Figure 2 shows multiplexed blocks of 362 bit spacing.

Figure 3 shows multiplexed blocks of 361 bit spacing.

Figure 4 shows the vertical blanking of a PAL television signal.

Fig. 5 shows the relative positions of the block signals.

Figure 6 is a text broadcast signal called "Ceefax".

Fig. 7 is a block diagram of an embodiment of the text signal receiving device of the present invention.

Fig. 8 is a block diagram of a framing code generation circuit.

The present invention will be described in detail below with examples.

First, the principle of the transmission method will be described.

In the PAL standard TV signal, the frequency fsc of the color sub-carrier signal is defined as:

fsc=4433618.75Hz

Use fcl to represent the clock pulse frequency of the text broadcasting signal, hope

fcl= (m)/(n) fsc

m and n are simple integers. In the PAL system, the cycle T of 1 frame is:

T＝ 1/25＝40×10 ^-3 (seconds)

The conditions for maintaining the continuity of the clock pulse signal are:

Tcl×N=M×40×10 ^-3

N represents the number of clock pulses in the above cycle, and M represents the number of frames in units of one frame. therefore,

$\mathrm{<span\; class="notranslate">\; N\; =</span>}\frac{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; Tcl</span>}}{\mathrm{<span\; class="notranslate">\; \times \; 40\; \times \; 10</span>}}^{\mathrm{<span\; class="notranslate">\; -3</span>}}$

$\mathrm{<span\; class="notranslate">\; =</span>}\frac{{\mathrm{<span\; class="notranslate">\; n.f</span>}}_{\mathrm{<span\; class="notranslate">\; sc.</span>}}{\mathrm{<span\; class="notranslate">\; M.\; 40\; \times \; 10</span>}}^{\mathrm{<span\; class="notranslate">\; -3</span>}}}{\mathrm{<span\; class="notranslate">\; m</span>}}$

$\mathrm{<span\; class="notranslate">\; =</span>}\frac{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; m</span>}}\mathrm{<span\; class="notranslate">\; \times \; M\; \times \; 177344.75</span>}$

N must be an integer satisfying the above formula.

When M=1, that is, the clock signal in one frame is continuous, m/n=12/11, 16/11, 20/11, etc., the bit rates at this time are 4.836675MHz, 6.44890MHz, and 8.061125MHz respectively. It is not possible to multiplex 272+8+16=296 bits during the 54 microseconds possible multiplexing of the PAL signal.

When M=2, that is, the clock signal is continuous within 2 frames, m/n=12/11, 14/11, 16/11 and so on. Here, except that m/n=14/11, it is the same as the above-mentioned case of maintaining continuity within one frame. In the case of m/n=14/11, the bit rate is 5.6427875 MHz, which is approximately equal to the bit rate of 5.727 MHz of Japanese text broadcasting. During about 54 microseconds, the number of bits to realize multiplexing is 304.7 bits, and the necessary 296 bits are sufficient Multiplexed bitrates.

1 line of the PAL signal is exactly 64 microseconds. Therefore, the number of bits to implement multiplexing in 1 row is:

64*5.6427875=361.1384 bits is approximately equal to 364 bits in Japan. With this bit rate, every 296 bits in a row, the clock pulse multiplexing of continuous phase is realized; after 8 rows, the phase of the first bit is shifted by about 1 bit. The number of bits after one frame is 225711.5 bits, and after two frames, the phase is shifted by 0.5 bits from the first frame. After the third frame, it is the same phase.

As mentioned above, in the TV signal of the PAL standard, the multiplexing of the text signal can achieve the same strong error correction capability as the Japanese standard. It is a good method to use the frequency of 14/11 of the color sub-carrier as the bit rate. .

In the PAL system, text broadcasting can be multiplexed during the 8-25 lines and the corresponding field vertical blanking periods. However, when 272-bit block signals are multiplexed sequentially from 8 lines, since the block cycle is set to 272 bits, the multiplex positions of each line are shifted sequentially (see Fig. 2). Its offset is 0.8616 bits. Therefore, the offset to line 25 is

0.8616×17=14.6472 bits

The corresponding amount of time is

14.6472×1/5.6427875＝2.595738365

(microseconds)

Therefore, only in the last part of the multiplexed block signal of the first 8th line, there is a time margin; if the multiplexed block signal of each line is multiplexed every 362 bits, then at the receiving end It is also easy to handle.

At this time, from the first bit multiplexed on line 8 to the last bit multiplexed on line 25 So far, from the perspective of peers, its full length is:

(296+14.6472)/5.6427875＝55.05208197

(microseconds)

Because the color burst signal of the PAL TV signal is 10 microseconds, and one line is 64 microseconds, the multiplexing time is no more than 54 microseconds at most. It can be seen that the above-mentioned offset has exceeded 54 microseconds, and multiplexing cannot be realized according to the current situation.

When the block signal is multiplexed with a period of 361 bits (refer to FIG. 3 ), each line advances only by a phase of 0.1384 bits. At this time, from the 18th line from the 8th line to the 25th line:

(296+17×0.1384)/5.6427875＝52.87330065

(microseconds)

within 54 microseconds. However, since the color burst is 10 microseconds, the time margin for multiplexing is:

54-52.8978275＝1.1021725 (microseconds)

It's not impossible, it's just less affluent.

The original 1-word group length is 296 bits, which is:

296×1/5.6427875＝52.45634361 (microseconds)

The situation in Figure 3 above is:

52.87330065-52.45634361＝0.41695704 (microseconds)

Just a little bit shorter.

Compare with "Ceefax" shown in Figure 6

52.87330065-51.89189189＝0.98140876 (microseconds)

That's less than 1 microsecond longer than that. It is roughly the same as the character group length of Ceefax.

The beginning of each word group can be changed. For example: the 9th line after the 8th line, its clock pulse The rush series can start at 361 bits, and the 10th line can start at 362 bits.

In this way, when the clock pulse series of each row starts at 361 bits, and when the clock pulse series of each row starts at 362 bits, there is a phase shift to the initial multiplexed clock pulse series, because there are 6- 7 times of offset, then the row of the clock pulse series that starts at 361 bits can be mixed into the word group of the clock pulse series that starts after 362 bits after 6-7 rows.

The above description is for all possible multiplexed behaviors during vertical regression, so 361-bit or 362-bit multiplexed is of course possible in the case of limiting multiple lines.

However, in the above case, the color sub-carrier is not rich, and the 372-bit information unit can be shortened, for example, the unit length can be:

272-8=264 (bits)

272-16=256 (bits)

(272, 190) The information bits of the symbol are 190 bits, since there is no byte unit, if it is taken as

272-6=266 (bits)

272-14=258 (bits)

The information bits are respectively 184 bits=23 bytes and 176 bits=22 bytes, which are easy to use. In this case, the signals from the clock pulse series can be arranged in each row at intervals of 361 bits or 362 bits as described above.

The multi-channel method of vertical blanking at the beginning of a frame has been described above, but the vertical blanking of the next field must be considered. The number of the line starting from the next field is the 313th line, and the possible multi-way lines are 17 lines starting from the 321st line. The relationship is shown in Figure 4.

However, at 361 bits or 362 bits, if the next block is continuous, Then line 321 will produce a large offset, which is inappropriate. Therefore, multiplexing is performed after specifying a clock pulse of a certain length starting from the eighth line. The next field starts to implement multiplexing from line 633, which is also performed after another clock pulse of a certain length. In this case, the phase of the clock pulse signal is only shifted by 0.5 bit with respect to the beginning field. This is because 14/11×fsc determined here is 2 frames as 1 cycle.

Figure 4 is based on the 8th row, and the bit clock pulse offset of the 321th row in the next field is:

313×64×5.6427875＝113036.3192 (bits)

After line 312 of the next field is:

312×64/5.6427875=112675.1808 (bits)

Therefore, the offset of the same time point after 1 frame is:

113036.3192+112675.1808＝225711.5 (bits)

Expressed in time, the offsets below 1 bit unit are:

0.05656778675 microseconds, 0.03204090177 microseconds, 0.08860868852 microseconds.

Therefore, if the phase of the clock pulse series of the multi-channel block signal in the 313th row is set to the 113036th clock pulse, then the phase after the 312th row (that is, after 1 frame) is after 112674.5 bits (that is, 1 frame), so that the bit clock If the phase of the pulse moves half a bit, then the phase becomes continuous within a frame period.

Fig. 5 shows the relative positions of the block signals.

Figure 1 shows a circuit for generating a television signal according to the invention. In the figure: 101 is the color sub-carrier (4.43361875MHz) signal, 102 is the frame pulse for shifting the clock pulse phase of each frame by half a bit, 103 is the horizontal synchronization signal for calculating the number of lines, 104 is the text data output from the computer, 105 is the usual PAL TV signal, 106 is the specified signal for specifying the line number of multiple lines, 107 is the frequency division circuit, 108 is the phase difference detection circuit, and 109 is the frequency division circuit , 110 is a voltage-controlled oscillator (VCO), 111 is a phase adjustment circuit for adjusting the phase of the clock pulse, 112 is a phase conversion circuit for shifting the phase of the clock pulse by half a bit in each frame, and 113 is reading data from the memory 114 with a time scale 114 is a memory for temporarily storing output data, 115 is an address and a control signal for controlling the memory 114, 116 is a multiplex block data, and 117 represents a multiplexing device for multiplexing in a specified row of a television signal .

The following describes the working conditions of the signal generator.

5.6427875MHz signal is obtained by the color sub-carrier frequency divider 107 of the PAL system TV signal and the PLL circuit composed of VCO110. This signal is adjusted to the phase of the data output signal by a phase adjuster 111 . Next, the signal is shifted by a half bit on each frame by frame pulses, and the block signal of each frame is output with the same time scale relative to the horizontal synchronization time scale.

This output is used as a clock pulse signal to control the DMA controller 113 through the frame timing and line synchronization, and output the address signal and control signal from the DMA controller 113 in the same way as the above-mentioned timing output data.

According to the signal from the DMA controller 113, the data already stored in the memory 114 is outputted, and the television signal of the specified line is multiplexed by the multiplexing means 117. On the other hand, since the clock pulse series and the framing code are also predetermined signals rather than being output from the memory 114, they can be output from a fixed memory such as a ROM.

Figure 1 shows the basic configuration, the input of the memory output data 116 to the multiplexing device 117, and the frequency band restricted.

Next, the receiving device will be described.

Fig. 7 is an embodiment of the text broadcasting signal receiving apparatus of the present invention. 201 in the figure is the signal obtained by multiplexing the text signal on the PAL standard TV signal according to the method of the present invention, and the bit rate is (14/11)×fsc. Here fsc is the color sub-carrier frequency of the PAL TV signal

fsc=4.43361875 MHz

However, the bit rate of the text signal is 5.6427875 Mbps.

202 is a color sub-carrier regeneration circuit, from the multi-channel color burst signals of each row, the APC circuit outputs the regenerated color sub-carrier 4.43361875MHz signal as a continuous signal.

203 is color sub-carrier frequency, a frequency division circuit by 1/11 frequency division. Therefore, the frequency of the output signal of the frequency dividing circuit 203 is: 0.40305625 MHz.

204 is a phase comparison circuit that generates the input signal of VCO205. The output frequency of VCO205 is 5.6427875MHz, which is divided by 1/14 by frequency division circuit 206 . Therefore, the frequency of the output signal of the frequency division circuit 206 is the same as the frequency of the output signal of the frequency division circuit 203 at 0.40305625 MHz.

The output signal of the VCO 205 is input to the phase selection circuit 207, and signals of various phases are prepared, for example, the phases may be shifted by 10 ns.

208 is an extraction circuit of clock pulse series. The frequency of the clock series signal 209 is the same as the frequency of the output signal of the VCO 205 , and the signal closest to the phase of the clock series signal 209 is selected from various phase signals of the phase selection circuit, and output as the signal 210 . That is, signal 210 and clock series signal 209 are substantially phase-synchronized signals.

211 is a vertical synchronization signal detection circuit, especially a circuit for detecting only the first field. From the framing code generation circuit 214 via the line counter 213, the multi-channel time stamp signal of the second field is output.

212 is a horizontal synchronous time scale signal generating circuit, which generates a signal for counting line pulses.

215 is a circuit for detecting the framing code of the input signal, and generates the input signal of the framing code generation circuit 214 . The framing code generation circuit 214 receives the framing code according to the signal of the row of the output signal 217 of the designated row counter 213, the clock pulse signal 210, the identification signal 209 of the presence or absence of multiple lines, the framing code detection signal 215, etc. Front and rear protection. Based on the timing of the output 216 of the framing code generation circuit, only the data portion (the data group after the framing code) of the block signal (output of the block signal detection circuit 217) is correctly captured by the data sampling circuit 218.

According to FIG. 7, the phase selection circuit 207 should automatically invert the 180° phase in the first field, however, the 180° phase can be forcibly switched by the output of the vertical synchronization signal detection circuit 211.

FIG. 8 is a detailed circuit diagram of the framing code generating circuit 214 of FIG. 7. 301 is a PAL TV signal, 302 is the signal 210 generated in Figure 1 (a clock pulse signal with a 180° phase inversion in the first field), and 303 represents the gate of the multiplex lines 8-25 and lines 312-329 Signal, 304 is the gate signal of 8 rows, 305 is the framing code detection circuit, 306 is the 361-bit counter, 307 is the AND circuit, 308 is the 113036-bit counter, 309 is the AND circuit, 310 is the coincidence detection circuit, 311 is the Non-coincidence pulse, 312 is coincidence pulse, 313 is non-coincidence counter, 314 is coincidence counter, 315 is non-coincidence counter output signal, 316 is coincidence counter output signal, 317 is AND circuit, 318 is AND circuit, 319 is from internal counter The framing time stamp signal, 320 is the 113036 counter output signal, 321 is the framing time scale output signal.

Next, the operation of the circuit shown in Fig. 8 will be described in order.

In the initial state, the time mark signal detected by the framing code detection circuit 305 passes through the gate circuit 309 to reset the 361-bit counter 306, and thereafter, the 361-bit counter 306 counts the clock pulse signal 302 to generate an internal framing code signal 319 . The counter 306 operates only during lines 8-25 and lines 312-329 of the multiplex signal.

The internal counter output signal 319 is constantly compared with the output of the framing code detection circuit 305 . Here, the signal indicating whether or not the character signal 303 is multiplexed can be detected from a series of clock pulses.

The output signals compared by the coincidence detection circuit 310 are a non-coincidence signal 311 and a coincidence signal 312 . When the coincidence counter 314 has counted, the non-coincidence signal 311 arrives, and the coincidence counter 314 is reset by the signal 317 . That is, the coincidence counter 314 counts the number of consecutive coincidences, and when the framing codes can be received with the same phase after 3 consecutive coincidences, the count-up signal 316 is output. The non-coincidence counter 313 counts the number of consecutive non-coincidences, and when the signal 315 is output, the coincidence counter 314 is reset to zero.

According to the time scale of the multi-line framing code at the top of the first field of the gate signal 304, the top of the second field is reset, counting 113036 bits, and the 361-bit counter 306 is reset again through the output of the counter to generate the internal framing code .

The 8th line or the 312th line of the gate signals 303, 304 shown in FIG. 8 can be regarded as the front line of a certain field of the multi-channel signal.

According to the circuit in Fig. 8, the framing code of the multiplex 296-bit text signal on the PAL system TV signal has indeed been received.

The row numbers of the above-mentioned 8th row etc. are given according to the counting method in Fig. 4 .

The text signal sequence shown in Fig. 7 is decoded by (272, 190) symbols, and error-free 190-bit information is extracted. The CPU interprets 190-bit information and expresses text and graphics on the CRT.

As can be seen from the above description, the present invention can indeed realize the regeneration of the clock pulse signal and the framed time scale on the receiver according to the relationship between the clock pulse frequency of the multi-channel text signal and the color sub-carrier frequency on the PAL system television signal.

For example, the frequency of the above-mentioned clock pulse signal is taken as (14/11) fsc, every framing time scale (40ms) of the TV signal, the phase of the clock pulse is reversed, and the offset is half a bit, so that the front of the block signal The time scale is consistent every 40ms, so it is easier for the receiver to process the signal.

In this way, like the Japanese text broadcasting signal, multiplexing of 296 bits per block can be realized, and (272, 190) symbols with strong error correction capabilities can be applied. Only the signal extraction method of the receiver is different, and an integrated circuit developed for Japanese text broadcasting can be used. In addition, symbolic methods can also be used.

Claims (4)

1. A method for transmitting a text broadcast signal, comprising: Extract the color sub-carrier signal from the PAL standard TV signal; A clock pulse signal for generating a text signal that is a simple integer ratio to the signal; It is characterized by: From a specific vertical blanking interval, the following 296-bit signals are transmitted sequentially; a series of 16-bit clock pulses used for clock synchronization, an 8-bit framing code used as a framing time stamp, 190 bits of information, calculated from the 190 bits of information out of the 82-bit parity signal. 2. The method of claim 1, wherein said integer ratio is 14/11. 3. The apparatus for receiving the text broadcast signal in claim 1, characterized in that it comprises: means for reproducing a color subcarrier signal (202); A device for multiplying the color sub-carrier signal by 14/11, which regenerates a signal with a frequency for a text broadcast and a clock series, which includes a frequency division circuit (203) for dividing the color sub-carrier signal into 1/11 components, a phase comparison circuit (204), a voltage controlled oscillator (205), a frequency divider (206) generating 1/14 components; Means (207) for selecting a signal in phase with the series of clock pulses for use as a clock signal for the textcast signal. 4. The device for receiving the text broadcast signal in claim 3, characterized in that the framing code is multiplexed at regular intervals to detect the framing code, so as to provide reliable reception of the framing code sex.

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