CN101651333B - Delay time control circuit for reducing delay time in battery protector - Google Patents

Abstract

The invention provides a battery protection IC, which is used for reducing a delay time when using a charge control pin Cout for an IC test (CP or FT test). The battery protection IC is provided with a delay time control circuit, a comparer and a signal delay selector, wherein the comparer is provided with a negative input terminal, a positive input terminal and an output terminal; the negative input terminal is connected with a VCC; the positive input terminal is connected with the Cout pin; and the output terminal is connected with the signal delay selector. In order to implement the test, a voltage source is added to trigger a short delay time module rather than a conventional delay time module.

Description

Delay time control circuit reduces time of delay in battery protector

Technical field

The invention relates to a delay time control circuit, be meant a battery protection integrated circuit especially, this battery protection integrated circuit embeds a delay time control circuit, and therefore, when carrying out test process, the testing time can reduce significantly.

Background technology

In order to protect one quite generally but be relatively costly lithium ion/lighium polymer rechargeable battery unfortunately; Protection lithium electricity rechargeable battery is with the generation to anti-over-charging or overcurrent; Usually can embed battery protector; Or the title battery protection ic, for preventing the for example removal of problem such as noise of misoperation, the battery protector of prior art has an internal latency circuit usually.Typically overcharge time of delay approximately between 0.1 second to 2.0 seconds.

Yet in the test phase of battery protection ic, in order to try to achieve the parameter of the condition of overcharging (overcharge), test many times is necessary, and therefore all institute's time spent is just considerable, and therefore, it is very disadvantageous that a large amount of protection IC products is done test; In addition, general prior art, as shown in Figure 1; Comprise and build pin in five; Time of delay (CP test) when VCC, VSS, Dout, COUT, Vm and an extra test pin DS carry out the wafer stage test to reduce is to find out the condition of overcharging, (FT test when prior art is tested for final stage; Promptly encapsulate the back battery protection ic), it is necessary that the test pin is extended out.

Summary of the invention

The objective of the invention is to disclose a delay time control circuit and be embedded in this battery protection ic to reduce the time of delay of carrying out CP or FT test.

Another object of the present invention is to reduce the testing time.

According to technology of the present invention, a control pin Cout is used to reduce battery protection ic and tests required time of delay, need not add the test pin; Battery protection ic has a delay time control circuit; Delay time control circuit comprises a comparator and a signal delay selector; Comparator has a negative input end, a positive input terminal and an output; Negative input end is connected with the supply voltage of battery protection ic, and positive input terminal is connected with this Cout pin, and output is connected with the signal delay selector.In order to carry out above-mentioned test, need add a voltage source with the trigger delay control circuit, delay control circuit is exported a short delaing time, but not exports regular time of delay; Current probe is in order to detect the variation of circulation overcurrent, to detect the phenomenon that overcharges of battery protection ic.

Description of drawings

Fig. 1, prior art has one and adds the DS pin to reduce time of delay;

Fig. 2, comparator of the present invention is embedded in the sketch map of battery protection ic;

Fig. 3, battery protection ic of the present invention have delay time control circuit and connect a voltage source, to touch delay time control circuit;

Fig. 4, several key point frequency change of embodiments of the invention figure.

Drawing reference numeral:

VCC, VSS, Dout, COUT, Vm pin

DS tests pin

The CP wafer sort

The FT final test

The D0 diode

10 protection IC

20 comparators

30 signal delay selectors

40 time of delay circuit

50 overcharge testing circuit

M0, M1, M2, M3, M4, M5, M6, M7 transistor

The G0 control signal

V, VSD voltage

Id drain electric current

The μ charge mobility

C _OXUnit are comprises the electric capacity of gate pole oxidation layer

L2, L3 passage length

W2, W3 channel width

The Iprob0 galvanometer

The R1 resistor

V0, V1 voltage source

The FET-2N transistor npn npn

Embodiment

About technology of the present invention, can further be understood through following detailed Description Of The Invention and accompanying drawing.

Before explanation technology of the present invention; Earlier with regard to battery protection ic five in build pin; It is power end and voltage detecting end that VCC, VSS, Dout, COUT, Vm are an explanation: VCC; VSS be earth terminal, COUT be external control to overcharge (overcharge) transistorized control end, Dout be that external control is crossed and put (overdischarge) transistorized control end, Vm is the current detecting end.

Of above-mentioned prior art; In order to obtain important parameters, the problem below regular test exists: (1) for wafer sort (CP test), one is attached at and adds outside the protection IC that to test pin DS be necessary; And for final test (FT test), an encapsulation pin DS is necessary; (2) each test needs 1.2 seconds approximately; But accomplish test for battery protection ic, must carry out test many times, and consumed time is just more considerable when testing a large amount of protection IC.The present invention discloses has battery protection ic when carrying out CP or FT test; Can reduce the circuit design of testing time in large quantities; The more important thing is that the pin Cout that only needs to export with former control tests pin or extra encapsulation pin as the test pin and need not any other.

Cout can be used for testing principle, is that the operating voltage range that builds on following basis: Cout is to (VCC-(V from VCC (supply voltage of protection IC) _Charger) _Max), (V wherein _Charger)=V _BP+-V _Bp-V can not take place during use _Cout＞VCC, so voltage VCC+ Δ V puts on the Cout pin and can be applied to just making and reduce circuit time of delay.

Battery protection ic of the present invention has a delay time control circuit and is embedded in protection IC circuit; In order to carry out test; This battery protection ic only needs an applied voltage source, a galvanometer (probe) or a potentiometer connects with it; The general utility functions of battery protection ic of the present invention are identical with prior art, can't receive the delay time control circuit influence.

In the preferred embodiment of the present invention, delay time control circuit comprises a signal delay selector 30 and a comparator 20, please with reference to Fig. 3; Comparator 20 can be any form, and an embodiment is as shown in Figure 2, and an asymmetric comparator 20 comprises a plurality of transistor M1 to M7; In this circuit; Diode D0 between pin Cout and VCC is a parasitic diode, and transistor M0 is an oxide-semiconductor control transistors, and it is controlled by a control signal G0.

When battery charge, signal G0 opens this transistor M0 so that C _OUTThe voltage of=VCC is up to battery and overcharges phenomenon, and signal G0 closes transistor M0 afterwards.In asymmetric comparator, transistor M2 and M3 form an asymmetric differential pair to control a voltage Δ V.Following formula can be in order to calculate Δ V value:

$\mathrm{\ΔV}=\sqrt{\frac{2\mathrm{Id}}{\mathrm{\μCox}}}(\frac{\sqrt{L2}}{W2}-\sqrt{\frac{L3}{W3}}).$

Wherein, Id is the drain electric current, and (μ is a charge mobility, and Cox is the electric capacity that per unit area comprises gate pole oxidation layer, and L2, W2 are respectively passage length and the width of transistor M2, and L3, W3 are respectively passage length and the width of transistor M3.

When pin Cout is used for carrying out test, in build delay time control circuit and receive this voltage Δ V and touch, need be reduced to about 5-10ms time of delay this moment.

In a preferred embodiment, as shown in Figure 3, comprise that in order to the equipment that FT or CP test is provided protection IC10, a voltage source V 1 is to provide Δ V, a voltage source V 0, a resistor R 1 and a galvanometer Iprob0.Because galvanometer or potentiometer be only in order to the voltage drop of monitored resistance device R1 or Cout pin or resistor R 1 two ends, so galvanometer is a selectivity assembly, can a potentiometer as replacement.

Please with reference to Fig. 3, voltage source V 0, voltage source V 1, resistor R 1 are connected with the Cout pin all continuously, and in addition, battery voltage source V0 has a positive electrode and a negative electrode, and is connected between VSS pin and the VCC pin; Protection IC10 comprise one time of delay circuit 40, an oxide-semiconductor control transistors M0, a parasitic diode D0 and overcharge testing circuit 50, time of delay circuit 40 comprise a comparator 20 and one time of delay signal selector 30.

Comparator 20 has a negative input end, a positive input terminal and an output, and negative input end is connected with VCC, and positive input terminal is connected with the Cout pin, and output is connected with signal delay selector 30.The output of signal delay selector 30 be connected in one time of delay circuit 40, time of delay, circuit 40 allowed to overcharge testing circuit 50 outputs one control signal G0 to oxide-semiconductor control transistors M0.

It is following to have the CP or the FT testing procedure that reduce the testing time cost:

Voltage source V 1 is in order to adjust a voltage, and with the trigger delay time control circuit, this voltage is between between 0.1V to 0.6V; Voltage V1 should be lower than 0.6V avoiding opening parasitic diode D0, but must be higher than 0.1V at least, possibly have noise and causes execution error because voltage V1 is too little.

In regular application circuit, voltage source V 1 equals 0, and at this moment, pin Cout has a voltage Vcout, Vcout=VCC-Vsd, and wherein, Vsd is the voltage of transistor M0 source electrode to drain end, therefore, this Vcout voltage always is lower than VCC; Comparator 20 output one negative supply voltage to signal delay selectors 30, with select one regular time of delay signal.

Please be simultaneously with reference to Fig. 4, at the beginning, battery voltage source V0 is lower than and overcharges.Next; Battery voltage source V0 changes a critical condition by electronegative potential; As: overcharge Vovercharge, pin Cout current potential Vcout=(V0+V1-I1*R1), comparator 20 output one positive voltage to signal delay selectors 30; Selecting a short delaing time signal, and the short delaing time signal is closed transistor M0 to overcharging testing circuit 50 to export a signal G0 via delay time control circuit 40.

Because comparator 20 has a very high output group anti-(desirable comparator), and therefore when transistor M0 closes, it is zero that electric current I PROB0 will drop to, and therefore, we know that in the test of each short time cell voltage V0 can reach one and overcharge condition.When pin Cout normally uses at battery protection ic; If it were not for when charging, opening N transistor npn npn FET-2; When overcharging, close N transistor npn npn FET-2 exactly, external equipment for example voltage source V 1, galvanometer IPRB0 (or potentiometer), resistor R 1 does not have, and delay time control circuit of the present invention will can not influence the regular running of battery protection ic; In order to reach this purpose; Voltage Δ V must be lower than the built-in voltage of diode D0, and (Δ V＜0.6V), in the case, be a conventional value or approximate 1.2 seconds time of delay.

Under general situation about using, comparator 20 and the signal delay selector 30 in protection IC10 will can not influence circuit 40 time of delay, because comparator 20 outputs one negative supply voltage, in order to select the regular time of delay as existing battery protection ic.The present invention also is applicable to FET-1, and FET-2 is the occasion of PMOS, utilizes PMOS to design the structure that this has the protection IC of delay time control circuit again, and in this case, the Cout pin has a negative control voltage Δ V.

Advantage of the present invention is following:

1. for battery protection ic, can directly carry out CP or FT test, need not any external pin or close beta pin.

Above-mentioned CP or FT test can significantly reduce running time.

It is top that comparator needs not be, because the scope of voltage Δ V is between between the 0.1V to 0.6V; IC has delay time control circuit when protection, and then applied voltage source V1 can adjust and select suitable voltage Δ V.

Though the present invention illustrates as above with preferred embodiments, so it is not only to terminate in the foregoing description that in order to limit spirit of the present invention with the invention entity.Be with, the modification of in not breaking away from spirit of the present invention and scope, being done all should be included in the claim scope.

Claims (3)

1. the device that has a delay time control circuit in the battery protection ic is in order to carrying out wafer stage test or terminal stage test, it is characterized in that this device comprises:

One resistor;

One first voltage source;

One battery voltage source;

One battery protection ic; Have five pins, a comparator, a signal delay selector, one time of delay circuit, one overcharge a testing circuit and an oxide-semiconductor control transistors; Wherein said five pins comprise that power end and voltage detecting end VCC, ground connection pin VSS, current detecting pin Vm, charging control pin Cout and external control are crossed and put transistorized control end Dout; This comparator has a negative input end, a positive input terminal and an output; This negative input end is connected with the supply voltage of battery protection ic, and this positive input terminal is connected with described Cout pin, and described output is connected with described signal delay selector; This signal delay selector output one test inhibit signal extremely described time of delay of circuit, the described testing circuit that overcharges of this circuit permission time of delay is controlled described oxide-semiconductor control transistors; And

Described battery voltage source, first voltage source, resistor are connected in regular turn; Be connected in described Cout pin again; The positive pole of described first voltage source is connected with described resistor; The negative pole of described first voltage source is connected with the power end of battery protection ic and voltage detecting end VCC, and the positive and negative electrode of described battery voltage source is connected to power end and the voltage detecting end VCC and the ground connection pin VSS of battery protection ic, and described first voltage source is in order to adjust a voltage; And

One galvanometer or a potentiometer; Use and judge whether described battery voltage source overcharges; When use be galvanometer the time, this galvanometer is connected between this resistor and the described Cout pin, passes through the electric current of this resistor with monitoring; When use be potentiometer the time, this potentiometer is the voltage drop in order to monitored resistance device two ends.

2. device as claimed in claim 1 is characterized in that, described first voltage source is in order to adjusting a voltage, and described voltage is between between 0.1V to 0.6V.

3. device as claimed in claim 2 is characterized in that, the adjustment of described first voltage source is relevant with described comparator.

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