CN101650655A - Method for analyzing test data of chip - Google Patents
Method for analyzing test data of chip Download PDFInfo
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- CN101650655A CN101650655A CN200910182798A CN200910182798A CN101650655A CN 101650655 A CN101650655 A CN 101650655A CN 200910182798 A CN200910182798 A CN 200910182798A CN 200910182798 A CN200910182798 A CN 200910182798A CN 101650655 A CN101650655 A CN 101650655A
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Abstract
The invention relates to a method for analyzing test data of a chip. The method finally realizes the analysis of a test result through data generated by test machines. In the method, a kind of analysis software is utilized, and the analysis software comprises library functions which correspond to all the test machines. The method for analyzing test data of a chip has simple step; besides, becausea reprogramming operation is not needed, the method can effectively save plenty of time and energy for testers so as to shorten an engineering period and reduce the labor cost.
Description
Technical field
The present invention relates to analytical approach, refer in particular to the analytical approach of IC test chip data such as the IC test chip.
Background technology
In semi-conductor industry, generally before using, can test its product, its purpose be to control test system hardware guarantee in some way measured device reach or surmount it those specifically be defined in design objective in the device specification book; Its test procedure is divided into several sections usually, as DC test, functional test, AC test etc.DC testing authentication voltage and current parameters; The correctness of the inner a series of logic function operations of functional test proofing chip; The AC test can be operated by completion logic in specific time-constrain in order to guarantee chip; Wherein program also will have the ability of control peripheral test equipment such as handle Handler and detector Probe; Also will collect and provide the test result or the data of summary character (or form), these results or data provide valuable information to test or production engineer, are used for yield (Yield) and analyze and control.It now is example with chip testing, conventional semiconductor design corporation and testing factory are when analyzing a large amount of IC test datas at present, the method for testing and analyzing that oneself is all arranged separately, entire chip test industry is a unified pattern not, so just cause a new chip of every exploitation, the document format data that all needs to generate according to tester table again utilizes certain language to go to develop corresponding test analysis formula again, because the development and testing program is not a simple correct or wrong thing, it is a process of seeking best solution under given situation, so it is more time-consuming, such as to a chip newly developed, select a specific quantity, after choosing corresponding board, the document format data that generates according to this board chooses certain language to write corresponding program to draw the data analysis result again, the once different classes of chip of every like this change, must take much time usually time of at least one month is carried out one-time programming, must waste a large amount of time of programming personnel like this, and just constantly do repetitive operation probably between the industry, so wasted great amount of manpower and material resources virtually.
Therefore need solve above problem for users provide a kind of easier method.
Summary of the invention
The actual technical matters to be solved of the present invention is how a kind of analytical approach that does not need the data of using all standard chips of overprogram is provided.
In order to realize above-mentioned purpose of the present invention, the invention provides a kind of new data analysing method, its data that generate by tester table finally realize the analysis of test result, it is characterized in that: utilized a kind of analysis software in this method for testing and analyzing, comprised the pairing built-in function of all tester tables in this analysis software.
The analytical approach of chip data of the present invention, not only method step is simple, and owing to do not need overprogram, therefore can effectively save tester's plenty of time and energy, shortens construction period, so reduced human cost to a great extent.
Description of drawings
Fig. 1 is a specific embodiment when operating according to the present invention;
Fig. 2 is the analytic system process flow diagram of the test data of chip according to the present invention;
Embodiment
The present invention is further illustrated below in conjunction with drawings and Examples.
So-called test macro is called ATE, form by electronic circuit and mechanical hardware, it is aggregate by power supply, gauging instrument, signal generator, pattern generator and other item of hardware under the same master controller commander, be used for imitating the operating conditions that measured device will be experienced in application, to find underproof product.This test macro comprises test system hardware and testing system software.Wherein test system hardware is by the computer control of one group of instruction of operation (test procedure), the time provide suitable voltage, electric current, sequential and functional status to measured device and monitor the response of measured device in test, the result and the predefined boundary of the each test of contrast are made the judgement of pass or fail.Wherein the programmed control test system hardware is tested, each test item is provided the result of pass or fail.Pass refers to that device reaches or surmounted its design specification; Fail is then opposite, and device does not reach designing requirement, can not be used for final application.Test procedure will make full use of the performance of test macro to obtain good test coverage, so some method of testings can be subjected to the restriction of test system hardware or software performance.
Because the existing chip test need be chosen the board of specific model earlier, generate corresponding data by this tester table then, the Test Engineer comes coding according to certain language of data recycle of this generation, with draw need as variance, various test results such as mean value, so that the Test Engineer analyzes chip according to this data result, in order to save tester's energy, can be with existing as V50,6700, all IC tester tables of various models such as V77 combine, utilize certain a language development to go out a kind of test analysis software, this analysis software is owing to comprised the tester table of existing all models, so when test chip, need choose corresponding tester table, and then call the pairing built-in function of this selected tester table, so just realized the generation data of this tester table are analyzed, can analyze the chip of any model, therefore no longer need the other again coding of Test Engineer just can directly obtain test result, so not only save Test Engineer's time, and shortened whole construction period.
Now exemplify the example explanation with this new being applied as of analysis software, please illustrated in figures 1 and 2 in conjunction with consulting, now a kind of chip if any some needs test analysis, because the test event of each chip is a variable, the tester at first needs to remove to write the test event document that meets this software according to test event, promptly need to utilize the test event converter, make its test event change into the text that test macro can be discerned, again it is imported in the test data analysis software systems, then on opener's machine interface, from the tester table of number of different types, choose corresponding board, so that call built-in function corresponding in the analysis software, described built-in function is meant the function of depositing in the function library of set of the function of being set up by system with certain function, the corresponding a kind of corresponding board of each built-in function wherein, again according to the test event of its generation be provided with on the text that generates described test event on, lower range, select the path that to analyze data again, promptly begin to enter the chip testing Report Builder after the affirmation, convert thereof into a data document, just enter data report then and analyzed maker, begin to analyze data, data document is analyzed in one of final generation, Test Engineer's all data of intuitive analysis very just like this, preserve to generate and analyze data document, close whole analysis software at last, what need replenish is, the analytic system of whole test data also comprises some other system assemblies, is used to support the related software and the installation file of this data analysis system.
The method of above analysis software is to embody a kind of method of this operation with a specific embodiment, the method of this kind analytical test chip has been utilized the analysis software of a test data, comprising all corresponding built-in functions of existing board, the user is when test chip, the function that only needs to derive corresponding board in this analysis software can carry out data analysis to chip, so just no longer need the Test Engineer to repeat coding, reduced engineering staff's workload so undoubtedly.In other words, do an analysis software at all different type boards, promptly this analysis software is applicable to existing all boards, after getting well corresponding board in elected like this, the program of this corresponding in the analysis software wherein board is derived, like this Test Engineer just needn't be more specially at chip or board coding respectively, and only need derive this analysis software both can, can finish follow-up data analysis action like this.
More than the method for this new analytical test chip, utilized an analysis software just to integrate the analytical approach of test data in the whole test industry, not only method is tending towards simpler, and saved tester's time, shorten construction period, also reduced human cost to a great extent.
Claims (6)
1. the analytical approach of a test data of chip, its data that generate by tester table finally realize the analysis of test result, it is characterized in that: utilized a kind of analysis software in this method for testing and analyzing, comprised the pairing built-in function of all tester tables in this analysis software.
2. analytical approach as claimed in claim 1 is characterized in that: described analysis software can be to be formed by any certain a language development.
3. analytical approach as claimed in claim 1 is characterized in that: in the method, after choosing pairing tester table, and then call the pairing built-in function of this selected tester table.
4. as claim 1 or 3 described analytical approachs, it is characterized in that: described built-in function is meant the function of depositing in the function library of set of the function of being set up by system with certain function.
5. as any described analytical approach of claim in the claim 1,3,4, it is characterized in that: the corresponding a kind of corresponding board of described each built-in function.
6. analytical approach as claimed in claim 1 is characterized in that: in the analytical approach of described test data of chip, after having selected the pairing built-in function of tester table, analyze data by analyzing the final test that can draw this chip.
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| CN200910182798A CN101650655A (en) | 2009-09-07 | 2009-09-07 | Method for analyzing test data of chip |
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| CN200910182798A CN101650655A (en) | 2009-09-07 | 2009-09-07 | Method for analyzing test data of chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102565685A (en) * | 2010-12-14 | 2012-07-11 | 苏州工业园区谱芯科技有限公司 | Logic built-in self-test system |
| CN104597392A (en) * | 2015-01-09 | 2015-05-06 | 上海华岭集成电路技术股份有限公司 | Data depth traceability test method |
| CN108627764A (en) * | 2017-03-21 | 2018-10-09 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system and its control method |
| CN109144528A (en) * | 2018-07-27 | 2019-01-04 | 深圳市浦洛电子科技有限公司 | A kind of method and system of automatic detection pin identification SPI Flash concrete model |
| CN110750951A (en) * | 2019-10-15 | 2020-02-04 | 四川豪威尔信息科技有限公司 | Method for processing integrated circuit layout data |
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| CN1632747A (en) * | 2003-12-22 | 2005-06-29 | 联想(北京)有限公司 | Software interface testing method |
| CN1670710A (en) * | 2004-03-16 | 2005-09-21 | 鸿富锦精密工业（深圳）有限公司 | Rapid diagnosis testing system and method for computer hardware |
| CN1991780A (en) * | 2005-12-28 | 2007-07-04 | 技嘉科技股份有限公司 | Modularized test method and device |
| CN101131660A (en) * | 2006-08-25 | 2008-02-27 | 佛山市顺德区顺达电脑厂有限公司 | Method for integrating module testing work |
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2009
- 2009-09-07 CN CN200910182798A patent/CN101650655A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632747A (en) * | 2003-12-22 | 2005-06-29 | 联想(北京)有限公司 | Software interface testing method |
| CN1670710A (en) * | 2004-03-16 | 2005-09-21 | 鸿富锦精密工业（深圳）有限公司 | Rapid diagnosis testing system and method for computer hardware |
| CN1991780A (en) * | 2005-12-28 | 2007-07-04 | 技嘉科技股份有限公司 | Modularized test method and device |
| CN101131660A (en) * | 2006-08-25 | 2008-02-27 | 佛山市顺德区顺达电脑厂有限公司 | Method for integrating module testing work |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102565685A (en) * | 2010-12-14 | 2012-07-11 | 苏州工业园区谱芯科技有限公司 | Logic built-in self-test system |
| CN102565685B (en) * | 2010-12-14 | 2014-04-02 | 苏州工业园区谱芯科技有限公司 | Logic built-in self-test system |
| CN104597392A (en) * | 2015-01-09 | 2015-05-06 | 上海华岭集成电路技术股份有限公司 | Data depth traceability test method |
| CN104597392B (en) * | 2015-01-09 | 2018-02-09 | 上海华岭集成电路技术股份有限公司 | The method that test data depth is traced to the source |
| CN108627764A (en) * | 2017-03-21 | 2018-10-09 | 深圳市华宇半导体有限公司 | Bank safety chip automatization test system and its control method |
| CN109144528A (en) * | 2018-07-27 | 2019-01-04 | 深圳市浦洛电子科技有限公司 | A kind of method and system of automatic detection pin identification SPI Flash concrete model |
| CN110750951A (en) * | 2019-10-15 | 2020-02-04 | 四川豪威尔信息科技有限公司 | Method for processing integrated circuit layout data |
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Application publication date: 20100217 |