CN101650645A - Device for expanding coprocessor command set - Google Patents
Device for expanding coprocessor command set Download PDFInfo
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- CN101650645A CN101650645A CN 200910102227 CN200910102227A CN101650645A CN 101650645 A CN101650645 A CN 101650645A CN 200910102227 CN200910102227 CN 200910102227 CN 200910102227 A CN200910102227 A CN 200910102227A CN 101650645 A CN101650645 A CN 101650645A
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Abstract
The invention relates to a device for expanding a coprocessor command set. A command set of a main processor connected with a coprocessor comprises an immediate data generating command and a coprocessor command code loading command, wherein the immediate data generating command is used for generating a coprocessor command code; the coprocessor command code loading command is used for realizing theloading of the coprocessor command code from a main processor general-purpose register to a coprocessor command register; a processor comprises an immediate data generating unit, the main processor general-purpose register and a coprocessor command loading execution unit for loading the coprocessor command code stored in the main processor general-purpose register into the coprocessor command register; and the coprocessor comprises the coprocessor command register and a coprocessor command executing module. The invention has favorable expansion performance and flexibility.
Description
Technical field
The present invention relates to the coprocessor command set in the processor design, especially a kind of expanding unit of coprocessor command set.
Background technology
Instruction set is the mutual interface of processor software and hardware, and processor passes through reading command from internal memory automatically, and complex calculations and control task are finished in go forward side by side row decoding and execution.Each processor all needs specific instruction set and carries out corresponding with it.Whether the advanced person of instruction set, directly has influence on the performance of processors performance, so instruction set is the important content of processor design.
In the design of present processor, except needs for fundamental operation and the control definition corresponding instruction collection, also need the instruction set subsystem of design surface to application-specific.Instruction set subsystem towards application-specific is that the complex calculations control flow is reduced to abstract operation, and is directly moved according to the information of decoding by processor, avoids producing complicated control computing flow process by basic instruction set.This method has obtained very using widely in present flush bonding processor field, as the SIMD instruction set of ARM, and the DSP ASE of MIPS etc.
The instruction set expansion technique mainly can be divided into two big classes at present: expansion of primary processor instruction set and coprocessor command set expansion.Primary processor instruction set expansion technique is meant the expansion of carrying out special instruction in the instruction set space of primary processor, and extended instruction is inner by increasing special performance element realization support at primary processor usually; The coprocessor command set expansion technique refers to carry out the expansion of special instruction outside primary processor instruction set space, extended instruction sends to the target coprocessor by coprocessor interface usually and finishes execution.The degree of coupling height of primary processor instruction set expansion technique and primary processor framework, resource multiplex degree height.The degree of coupling of coprocessor command set expansion technique and primary processor is relatively low, but expansion is flexible relatively, can support flexibly according to the feature of using.The coprocessor command set expansion technique becomes the principal mode of present instruction set expansion because expansion is convenient, the design risk is little.
Present coprocessor command set expansion technique is normally divided the definition that a special region is used for coprocessor command set in primary processor order number space, be 0100 to keep and use to coprocessor as the MIPS processor with the highest 4 of 32 machine codes.The advantage of this technology is that the instruction of coprocessor can be looked ahead according to the mode of ordinary instruction by primary processor, and by decoding, rapid differentiation is carried out in primary processor instruction and coprocessor instruction.The getting finger and will become simply of coprocessor like this, it is clear that the interface definition of primary processor and coprocessor can become.But this method exists some problems equally, mainly shows: 1, concentrate the extending space difficulty bigger at 16 bit instructions of instruction code space relative compact; 2, get finger and decoding unit because coprocessor and primary processor are shared, so the form of coprocessor instruction is subjected to the influence of primary processor form.
Summary of the invention
Existingly to divide in primary processor order number space that the scalability that a special region is used for coprocessor command set is poor, the deficiency of very flexible in order overcoming, to the invention provides a kind of expanding unit with good scalability, coprocessor command set that dirigibility is good.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of expanding unit of coprocessor command set, in the instruction set of the primary processor that is connected with described coprocessor, comprise: be used to produce the generation of the number immediately instruction of coprocessor instruction sign indicating number, and the coprocessor instruction sign indicating number loading instruction that is used to realize the loading of described coprocessor instruction sign indicating number from the primary processor general-purpose register to the coprocessor instruction register;
Described primary processor comprises: be used to control and count the several immediately generation units that produce instruction elder generation generation coprocessor instruction sign indicating number immediately, be used for depositing the primary processor general-purpose register that produces the coprocessor instruction sign indicating number that instruction produces by number immediately, and the coprocessor instruction that the coprocessor instruction sign indicating number that is used for depositing in the primary processor general-purpose register is loaded into the coprocessor instruction register loads performance element temporarily;
Described coprocessor comprises: be used to receive the coprocessor instruction sign indicating number that is loaded by primary processor, and the order code that receives is sent to the coprocessor instruction register that coprocessor is carried out, and be used for from coprocessor instruction register read command and the coprocessor instruction execution module finishing decoding and carry out.
Further, the described generation of number immediately instruction is finished by primary processor and is got finger, decoding, execution, and the results that count immediately that will produce are written back in the general-purpose register.
Further, the source operand of described coprocessor instruction sign indicating number loading instruction is stored in the primary processor general-purpose register, and destination register is the coprocessor instruction register.
Further, described number immediately produce instruction for the former number immediately in the multiplexing primary processor produce instruction or separately design be specifically designed to and produce the instruction that the coprocessor instruction sign indicating number is counted immediately.
Described coprocessor instruction execution module comprises: be used for the coprocessor instruction decoding unit of decodes coprocessor instructions, be used to the coprocessor instruction command unit of carrying out coprocessor instruction and producing accordingly result.
Technical conceive of the present invention is: based on the coprocessor expansion technique that the application realizes the instruction space of primary processor and coprocessor is effectively isolated, realized that the coprocessor command set expansion is relatively independent with primary processor.Not only can expand a plurality of parallel independent instruction set by this method, the exploitation of also independently carrying out coprocessor for the user simultaneously lays a solid foundation.
Beneficial effect of the present invention mainly shows: 1, have good scalability, dirigibility is good; 2, effectively simplified the mode of coprocessor command set expansion, provide flexible and efficient support on unified basic instruction set framework, expanding various application oriented user defined commands.
Description of drawings
Fig. 1 is the synoptic diagram of the coded system of the instruction of number generation immediately.
Fig. 2 is the synoptic diagram of the coded system of coprocessor instruction sign indicating number loading instruction.
Fig. 3 is the actuating unit framework synoptic diagram of coprocessor command set extended instruction.
Fig. 4 is the synoptic diagram that obtains to count immediately the execution mechanism of the instruction that produces by precompile.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Fig. 4, a kind of expanding unit of coprocessor command set, in the instruction set of the primary processor that is connected with described coprocessor, comprise: be used to produce the generation of the number immediately instruction of coprocessor instruction sign indicating number, and the coprocessor instruction sign indicating number loading instruction that is used to realize the loading of described coprocessor instruction sign indicating number from the primary processor general-purpose register to the coprocessor instruction register;
Described primary processor comprises: be used to control and count the several immediately generation units that produce instruction elder generation generation coprocessor instruction sign indicating number immediately, be used for depositing the primary processor general-purpose register that produces the coprocessor instruction sign indicating number that instruction produces by number immediately, and the coprocessor instruction that the coprocessor instruction sign indicating number that is used for depositing in the primary processor general-purpose register is loaded into the coprocessor instruction register loads performance element temporarily;
Described coprocessor comprises: be used to receive the coprocessor instruction sign indicating number that is loaded by primary processor, and the order code that receives is sent to the coprocessor instruction register that coprocessor is carried out, and be used for from coprocessor instruction register read command and the coprocessor instruction execution module finishing decoding and carry out.
The described generation of number immediately instruction is finished by primary processor and is got finger, decoding, execution, and the result is written back in the general-purpose register.
The source operand of described coprocessor instruction sign indicating number loading instruction is stored in the primary processor general-purpose register, and destination register is the coprocessor instruction register.
Described number immediately produce instruction for the former number immediately in the multiplexing primary processor produce instruction or separately design be specifically designed to and produce the instruction that the coprocessor instruction sign indicating number is counted immediately.
Described coprocessor instruction execution module comprises: be used for the coprocessor instruction decoding unit of decodes coprocessor instructions, be used to the coprocessor instruction command unit of carrying out coprocessor instruction and producing accordingly result.
The coprocessor command set extended instruction of present embodiment is meant that number produces instruction and two instructions of coprocessor instruction sign indicating number loading instruction immediately.
Number produces the former immediately number of instruction in can multiplexing primary processor and produces instruction immediately, also can design separately to be specifically designed to produce the instruction that the coprocessor instruction sign indicating number is counted immediately.The processes that produce of number both can be by number encoder immediately in order code immediately; Also can will count compiling in advance immediately and deposit in the internal memory, in running program running process, from internal memory, dynamically obtain by the special instruction that is written into by compiler.The destination register of the instruction of number generation immediately is the general-purpose register of primary processor, and the numbering of destination register need be enrolled in the order code.Immediately number produce instruction two kinds of specific coding modes as shown in Figure 1: be that number enrolls a kind of modes of order code immediately (a), the 11st, the operational code of this instruction, in the order code several immediately 13 directly intercepted in the process of implementation, sends into then by storing in the 12 purpose of indicating registers; (b) be based on the number immediately that compiler compiles in advance and be written into instruction, 14 be operational code, and 15 be destination register, and 16 are the side-play amount indicating bit of present instruction, is used for representing the several immediately side-play amounts in the relative present instruction of internal memory of target.
The function of coprocessor instruction sign indicating number loading instruction is that the coprocessor instruction sign indicating number that will temporarily deposit in the primary processor general-purpose register is sent in the order register of coprocessor.This instruction is the instruction in the primary processor space encoder, and essence is a special move instruction.The source-register of coprocessor instruction sign indicating number loading instruction is the general-purpose register of primary processor, and destination register is the order register of coprocessor.During order number, the fixing coding of primary processor general-purpose register and coprocessor instruction register, bit that also can design specialized is used to refer to primary processor general-purpose register and the purpose coprocessor instruction register that this instruction is chosen.Provided the coprocessor instruction sign indicating number as Fig. 2 and reprinted the specific coding mode of instructing: 21 operational codes for instruction, the order register of 22 indicating target coprocessors, a common coprocessor has only an order register, therefore this part is not necessary in the order code, the primary processor general-purpose register numbering of 23 indication storage coprocessor instruction sign indicating numbers.
The implementation of coprocessor command set extended instruction and framework as shown in Figure 3, wherein:
31 for primary processor get the finger unit, except that the common primary processor instruction of looking ahead, the number immediately that increases among the present invention that also looks ahead simultaneously produces instruction and coprocessor instruction loading instruction.
32 is the decoding unit of primary processor, and except that the common primary processor instruction of decoding, the number immediately that increases in the code book invention simultaneously produces instruction and coprocessor instruction loading instruction, and they are sent to respectively in the corresponding performance element.
33 is several immediately generation units of primary processor, is used to carry out number immediately proposed by the invention and produces instruction.
34 is the general register unit of primary processor, and the operand and the operation result of storage computing are also deposited in the general register unit by the coprocessor instruction sign indicating number of counting generation unit 33 generations immediately among the present invention temporarily.
35 for coprocessor instruction sign indicating number reprinting performance element, is used for carrying out that the coprocessor instruction sign indicating number is transported to corresponding coprocessor instruction operation registers from the general-purpose register of primary processor.
36 is the coprocessor instruction register, is used to receive the coprocessor instruction sign indicating number that sends from primary processor.
37 is the coprocessor instruction decoding unit, decodes coprocessor instructions.
38 is the coprocessor instruction command unit, carries out coprocessor instruction, produces accordingly result.
The implementation of the instruction of number generation immediately is: at first primary processor is got and is referred to that unit 31 obtains instruction from storer, deliver to decoding in the decoding unit 32, if present instruction is the instruction of number generation immediately, then this instruction is sent to and counts instruction execution unit 33 immediately, count instruction execution unit 33 immediately and carry out several immediately accordingly production processes according to the operational code of instruction, the result of Chan Shenging is written in the primary processor general-purpose register 34 the most at last.
The implementation of coprocessor instruction sign indicating number loading instruction is: at first primary processor is got and is referred to that unit 31 obtains instruction from storer, deliver to decoding in the decoding unit 32, if present instruction is a coprocessor instruction sign indicating number loading instruction, then this instruction is sent to the coprocessor instruction sign indicating number and loads performance element 35, the coprocessor instruction sign indicating number loads performance element 35 and read corresponding coprocessor instruction operational code from primary processor general register unit 34, sends it in the coprocessor instruction register 36 then.
The implementation of coprocessor instruction is: obtain order code from coprocessor instruction register 36, then order code is sent to coprocessor decoding unit 37, according to decode results instruction is sent in the corresponding performance element 38 and carry out.
Counting instruction execution unit 33 immediately is used for the execution instruction of number generation immediately and generates target several immediately.For counting immediately shown in the conceptual scheme 1 (a) that enrolls order code, performance element only needs to carry out the step-by-step intercepting to order code and just can obtain to count immediately accordingly.For counting the scheme that from internal memory, obtains then by the compiler precompile immediately, can obtain wideer the counting immediately of bit wide, its implementation is as shown in Figure 4.Instruction is fed to immediately and counts after the generation unit, and the low level 41 of instruction is intercepted, and the destination address of counting immediately by acquisition after totalizer 43 additions in the address of present instruction (PC).Initiate read request by steering logic 42 to storer simultaneously in this, several immediately results of acquisition are finally by in the write-back general purpose register set.
General register unit 34 is for comprising the adhoc buffer space that primary processor is used for store operands and result thereof.By corresponding position in the instruction segment, as 12 among Fig. 1,15,23 among Fig. 2 carries out index.
Coprocessor instruction loads performance element 35 after obtaining instruction, obtains corresponding counting immediately from general-purpose register 34, is sent to then in the order register of coprocessor, realizes the successful loading of coprocessor instruction.
Claims (6)
1, a kind of expanding unit of coprocessor command set, it is characterized in that: in the instruction set of the primary processor that is connected with described coprocessor, comprise: be used to produce the generation of the number immediately instruction of coprocessor instruction sign indicating number, and the coprocessor instruction sign indicating number loading instruction that is used to realize the loading of described coprocessor instruction sign indicating number from the primary processor general-purpose register to the coprocessor instruction register;
Described primary processor comprises: be used to control and count the several immediately generation units that produce instruction elder generation generation coprocessor instruction sign indicating number immediately, be used for depositing the primary processor general-purpose register that produces the coprocessor instruction sign indicating number that instruction produces by number immediately, and the coprocessor instruction that the coprocessor instruction sign indicating number that is used for depositing in the primary processor general-purpose register is loaded into the coprocessor instruction register loads performance element temporarily;
Described coprocessor comprises: be used to receive the coprocessor instruction sign indicating number that is loaded by primary processor, and the order code that receives is sent to the coprocessor instruction register that coprocessor is carried out, and be used for from coprocessor instruction register read command and the coprocessor instruction execution module finishing decoding and carry out.
2, the expanding unit of coprocessor command set as claimed in claim 1 is characterized in that: the described generation of number immediately instruction is finished by primary processor and is got finger, decoding, execution, and the results that count immediately that will produce are written back in the general-purpose register.
3, the expanding unit of coprocessor command set as claimed in claim 1 is characterized in that: the source operand of described coprocessor instruction sign indicating number loading instruction is stored in the primary processor general-purpose register, and destination register is the coprocessor instruction register.
4, the expanding unit of coprocessor command set as claimed in claim 2 is characterized in that: the source operand of described coprocessor instruction sign indicating number loading instruction is stored in the primary processor general-purpose register, and destination register is the coprocessor instruction register.
5, as the expanding unit of one of claim 1-4 described coprocessor command set, it is characterized in that: described number immediately produce instruction for the former number immediately in the multiplexing primary processor produce instruction or separately design be specifically designed to and produce the instruction that the coprocessor instruction sign indicating number is counted immediately.
6, as the expanding unit of one of claim 1-4 described coprocessor command set, it is characterized in that: described coprocessor instruction execution module comprises: be used for the coprocessor instruction decoding unit of decodes coprocessor instructions, be used to the coprocessor instruction command unit of carrying out coprocessor instruction and producing accordingly result.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246496A (en) * | 2012-02-10 | 2013-08-14 | 上海算芯微电子有限公司 | Non-blocking coprocessor interface method and non-blocking coprocessor interface system |
| CN104424033A (en) * | 2013-09-02 | 2015-03-18 | 联想(北京)有限公司 | Electronic device and data processing method |
| CN110990086A (en) * | 2019-11-26 | 2020-04-10 | 华中科技大学 | Coprocessor calling method and system for image target detection |
| CN116991477A (en) * | 2023-08-03 | 2023-11-03 | 上海合芯数字科技有限公司 | Rotary instruction execution method, system and execution unit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107656802A (en) * | 2017-09-22 | 2018-02-02 | 中国科学技术大学苏州研究院 | Time trigger instruction collection, coprocessor and device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1438574A (en) * | 2003-02-21 | 2003-08-27 | 中国航天科技集团公司第九研究院七七一研究所 | Instruction collection of 16-bit micro-processor |
| US7917734B2 (en) * | 2003-06-30 | 2011-03-29 | Intel Corporation | Determining length of instruction with multiple byte escape code based on information from other than opcode byte |
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2009
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246496A (en) * | 2012-02-10 | 2013-08-14 | 上海算芯微电子有限公司 | Non-blocking coprocessor interface method and non-blocking coprocessor interface system |
| CN103246496B (en) * | 2012-02-10 | 2015-12-16 | 上海算芯微电子有限公司 | Unblock coprocessor interface method and system |
| CN104424033A (en) * | 2013-09-02 | 2015-03-18 | 联想(北京)有限公司 | Electronic device and data processing method |
| CN104424033B (en) * | 2013-09-02 | 2018-10-12 | 联想(北京)有限公司 | A kind of electronic equipment and data processing method |
| CN110990086A (en) * | 2019-11-26 | 2020-04-10 | 华中科技大学 | Coprocessor calling method and system for image target detection |
| CN110990086B (en) * | 2019-11-26 | 2021-07-02 | 华中科技大学 | Coprocessor calling method and system for image target detection |
| CN116991477A (en) * | 2023-08-03 | 2023-11-03 | 上海合芯数字科技有限公司 | Rotary instruction execution method, system and execution unit |
| CN116991477B (en) * | 2023-08-03 | 2024-01-30 | 上海合芯数字科技有限公司 | Rotary instruction execution method, system and execution unit |
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Inventor after: Meng Jianyi Inventor after: Liang Jing Inventor after: Yan Xiaolang Inventor after: Ge Haitong Inventor after: Sha Ziyan Inventor after: Shen Xiuhong Inventor after: Yang Ting Inventor after: Li Xiaoming Inventor after: Duan Lingxiao Inventor after: Chen Liang Inventor before: Meng Jianyi Inventor before: Yan Xiaolang Inventor before: Ge Haitong Inventor before: Sha Ziyan |
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Free format text: CORRECT: INVENTOR; FROM: MENG JIANYI YAN XIAOLANG GE HAITONG SHA ZIYAN TO: MENG JIANYI YAN XIAOLANGGE HAITONG SHA ZIYAN SHEN XIUHONG YANG TING LI XIAOMING DUAN LINGXIAO CHEN LIANG LIANG JING |
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Effective date of registration: 20160225 Address after: 310012 A403 room, Hangzhou Neusoft building, 99 Huaxing Road, Xihu District, Zhejiang, Hangzhou, China Patentee after: Zhongtian Microsystems Co., Ltd., Hangzhou Address before: 310027 Hangzhou, Zhejiang Province, Xihu District, Zhejiang Road, No. 38, No. Patentee before: Zhejiang University |