CN101650642B - Floating point addition device based on complement rounding - Google Patents
Floating point addition device based on complement rounding Download PDFInfo
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Abstract
The invention relates to a floating point addition device based on complement rounding, which supports the floating point addition operation and the floating point subtraction operation. The floating point addition device comprises an exponent adder, a mantissa shifter, a mantissa operand preparation logic unit, a mantissa adder, a rounding judgment logic unit and a rounding adder, wherein the mantissa operand preparation logic unit is used for processing the mantissa operand according to sign bits and the exponent difference of the first floating point operand and the second floating point operand, the rounding judgment logic unit is used for executing the uniform rounding judgment on a mantissa addition result, judging the positive and the negative of the mantissa sum according to the highest bit output by the mantissa adder, determining a constant bit for the rounding judgment according to the highest four bits output by the mantissa adder, and unifying original code rounding plus 1 judgment logic and complement rounding plus 0 judgment logic; and the rounding adder is used for rounding the mantissa addition result of the floating point and finishing the code extraction and complement operation to the mantissa sum. The invention has the uniform mechanism, avoids the special complex mantissa operand preparation and rounding judgment logic of the floating point addition, and reduces the logic complexity.
Description
Technical field
The present invention relates to a kind of micro-processor architecture design, relate in particular to floating-point calculation component.
Background technology
Floating-point operation is ubiquitous in actual life, and science computing, signal Processing, media application, information communication etc. all need a large amount of floating-point operations.Before the eighties in 20th century, each tame computer vendors is supporting the rule aspect the floating-point operation to be not quite similar, and this is applied in transplanting on the various computing machine platform to floating-point and has brought very big constant.For this reason, IEEE has proposed a cover floating-point operation standard " IEEE-754 for Binary Float-point Arithmetic " in 1985, now become general international standard.In this standard, proposed single precision, double precision, expansion single precision, four kinds of floating point representation forms of expansion double precision, and specifically defined floating-point operation, rounding mode and computing abnormity processing etc.
In all floating-point operation the insides, the floating add subtraction is the most frequent, has on average accounted for the 50%-60% of floating-point operation total amount, and it is extremely important therefore to design a simple, effective floating add subtraction parts.
The most basic floating add subtraction can be with reference to [D.A.Patterson and J.L.Henessy, Computer Architecture-A Quantitative Approach, Morgan KaufmannPublishers, Second edition (1996)], mainly comprise following eight steps:
1. the index that calculates two floating numbers is poor
2. according to the move to right mantissa of the little floating number of index of the index difference of two floating numbers, realize rank
3. mantissa's summation
4. if mantissa and be negative is to mantissa and supplement sign indicating number
Mantissa and in first position probing of 1
6. mantissa and normalization
7. round off
8. cause the result to shift out if round off, again normalization
Wherein, the 4th step is if mantissa and be negative, to mantissa and supplement sign indicating number.One of this action need is got complementer, gets complementer and comes down to a totalizer, and this not only brings the increase of hardware resource, has also caused the elongated of floating add time delay.
So in general floating add subtraction is realized, can judge the size of two floating numbers by the index extent in above-mentioned steps 2.If the index of first floating number deducts the result of index of second floating number for just, represent first floating number greater than second floating number, then in step 3, add/subtract the mantissa of second floating number with the mantissa of first floating number; If the index of first floating number deducts the result of index of second floating number for negative, represent first floating number less than second floating number, then in step 3, add/subtract the mantissa of first floating number, with assurance mantissa with for just with the mantissa of second floating number; If it is zero that the index of first floating number deducts the result of the index of second floating number, then do not go to judge the size of mantissa, the mantissa with first floating number in step 3 adds/subtracts the mantissa of second floating number.Though this process can avoid above-mentioned steps four when mantissa and get complementary operation when negative, but brought very big trouble for rounding off of step 7.Analyze theoretically, do not lose for the information bit that needs that guarantees to round off, when the floating-point subtraction, need big floating number is deducted displacement to the little floating number after the rank, the subtraction result to this perfect information rounds off again.This implementation had both been brought huge hardware logic (for the double precision subtraction, need 106 subtracter, need 46 subtracter for single precision), made the time delay variation of floating-point subtraction again.So in the floating-point subtraction of reality is realized, consider the situation that the floating-point subtraction need round off, the one, need round off during the not borrow of floating-point subtraction, the one, the floating-point subtraction will borrow needs to round off, reduced the size (need 24 for the single-precision floating point subtraction, the double-precision floating point subtraction needs 54) of mantissa adder device.Though brought the saving on the hardware resource by further improvement, but be based on the judgement that floating-point rounds off under the different borrow situations of Floating Subtract method, still need prepare and complicated, machine-processed skimble-scamble operation and judgement are done in last rounding off on judging at the operand of mantissa adder device.The logical complexity that this has not only increased design has also proposed very high requirement to the deviser, the problem because some floating-point subtractions in particular cases of the careful thinking of deviser's needs round off.
Summary of the invention
In order to overcome the high deficiency of machine-processed disunity, logical complexity of existing floating add parts, the invention provides that a kind of mechanism mantissa's operand unified, that avoid the distinctive complexity of floating add is prepared and the decision logic that rounds off, reduce the floating add device that rounds off based on complement code of logical complexity.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of floating add device that rounds off based on complement code is supported floating add operation and floating-point subtraction, and described floating add device comprises:
The index totalizer, the index that is used to calculate the first floating-point operation number and the second floating-point operation number is poor;
Mantissa's shift unit is used for being shifted to rank according to the index difference of the prime input mantissa to the less floating-point operation number of index;
Described floating add device also comprises:
Mantissa operand ready logic unit is used for according to the sign bit and the index difference of the first floating-point operation number and the second floating-point operation number mantissa's operand being carried out following processing:
For the floating add operation, directly will be shifted to mantissa's input mantissa adder device of the floating-point operation number after the rank;
For the floating-point subtraction, if the index difference of the first floating-point operation number and the second floating-point operation number is not 0, according to the mantissa negate of index difference to the bigger floating-point operation number of index, and the mantissa of the less floating-point operation number of index remains unchanged; If the index difference of the first floating-point operation number and the second floating-point operation number is 0, regulation remains unchanged mantissa's negate of the second floating-point operation number to the mantissa of the first floating-point operation number;
The mantissa adder device is used for the mantissa's summation to the operand ready logic input of prime mantissa;
The decision logic unit that rounds off, according to the most significant digit of mantissa adder device output judge mantissa and positive and negative, be identified for the set position of rounding off and judging according to the Gao Siwei of mantissa adder device output,
The totalizer that rounds off is used for the mantissa adder result of floating-point is rounded off, and finish to mantissa and get complementary operation.
Further, the described decision logic that rounds off judges according to the most significant digit of mantissa adder device output, if mantissa adder as a result most significant digit be 0, represent that this operation result is true form and result for just, if mantissa adder most significant digit as a result is 1, represent that this operation result is that complement code and result are negative.
Further again, the described decision logic unit that rounds off comprises true form decision logic subelement and the complement code decision logic subelement that rounds off that rounds off, and true form rounds off and adds a decision logic and complement code and round off that to add 0 decision logic unified.
Described floating add device also comprises: the result normalization shift unit is used for according to the floating point expression form sign bit and exponential sum mantissa being encapsulated.
Further, described mantissa adder device is a carry-in carry-out totalizer; For floating add, the carry-in bit perseverance of mantissa adder device gets 0; For the floating-point subtraction, the carry-in bit perseverance of mantissa adder device gets 1.
As preferred a kind of scheme: the described totalizer that rounds off is an add with carry musical instruments used in a Buddhist or Taoist mass; For floating add, the totalizer that rounds off finish to mantissa and the operation of rounding off; For the floating-point subtraction, when the index difference of the first floating-point operation number and the second floating-point operation number is not 0, the totalizer that rounds off both finished to mantissa and the operation of rounding off, finish again to mantissa and get complementary operation; When the index difference of the first floating-point operation number and the second floating-point operation number is 0, and the mantissa of the first floating-point operation number is less than the mantissa of the second floating-point operation number, and the totalizer that rounds off is re-used and realizes result's the complementary operation of getting.
Beneficial effect of the present invention mainly shows: 1) mechanism is unified.The present invention rounds off by supporting floating-point complement arithmetic and complement code, has realized the unification of floating add and floating-point subtraction; 2) logical design is simple.The present invention has avoided complicated mantissa's operand to prepare and the decision logic that rounds off by floating add computing and floating-point subtraction is unified; 3) dirigibility is good.The method that this adder part relates to is adapted to the floating add subtraction of any precision.
Description of drawings
Fig. 1 is the position view of floating add device in processor and total system.
Fig. 2 is the synoptic diagram of the data layout of the single, double precision of floating-point.
Fig. 3 is the general structure synoptic diagram of floating add device.
Fig. 4 is the process flow diagram that the floating add subtraction is realized.
Fig. 5 is the implementation structure figure of index addition.
Fig. 6 is the implementation structure figure of mantissa's displacement.
Fig. 7 is the exemplary plot of two floating-point operation number displacements.
Fig. 8 is that the exemplary plot that mantissa subtracts each other is counted in two floating-point operations.
Fig. 9 is the structural drawing of mantissa's operand ready logic and mantissa's summation.
Figure 10 is the judgement synoptic diagram that rounds off.
Figure 11 is the implementation structure figure of addition of rounding off.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Figure 11, a kind of floating add device that rounds off based on complement code, described floating add device is supported floating add operation and floating-point subtraction, and described floating add device comprises: the index totalizer, and the index that is used to calculate the first floating-point operation number and the second floating-point operation number is poor; Mantissa's shift unit is used for being shifted to rank according to the index difference of the prime input mantissa to the less floating-point operation number of index; Described floating add device also comprises:
Mantissa operand ready logic unit is used for according to the sign bit and the index difference of the first floating-point operation number and the second floating-point operation number mantissa's operand being carried out following processing:
For the floating add operation, directly will be shifted to mantissa's input mantissa adder device of the floating-point operation number after the rank.
For the floating-point subtraction, according to the mantissa negate of index difference to the bigger floating-point operation number of index, and the mantissa of the less floating-point operation number of index remains unchanged; If the index difference of the first floating-point operation number and the second floating-point operation number is 0, regulation remains unchanged mantissa's negate of the second floating-point operation number to the mantissa of the first floating-point operation number;
The mantissa adder device is used for the mantissa's summation to the operand ready logic input of prime mantissa;
The decision logic unit that rounds off, according to the most significant digit of mantissa adder device output judge mantissa and positive and negative, be identified for the set position of rounding off and judging according to the Gao Siwei of mantissa adder device output;
The totalizer that rounds off is used for the mantissa adder result of floating-point is rounded off, and finish to mantissa and get complementary operation.
Further, the described decision logic that rounds off judges according to the most significant digit of mantissa adder device output, if mantissa adder as a result most significant digit be 0, represent that this operation result is true form and result for just, if mantissa adder most significant digit as a result is 1, represent that this operation result is that complement code and result are negative.
Further again, the described decision logic unit that rounds off comprises true form decision logic subelement and the complement code decision logic subelement that rounds off that rounds off, and true form rounds off and adds a decision logic and complement code and round off that to add 0 decision logic unified.
The true form that comprises the described decision logic unit that rounds off decision logic subelement and the complement code judgment sub-unit logic that rounds off that rounds off, true form round off and add a decision logic unit and complement code and round off that to add 0 decision logic cellular logic unified.
Described floating add device also comprises: the result normalization shift unit is used for according to the floating point expression form sign bit and exponential sum mantissa being encapsulated.
Described mantissa adder device is a carry-in carry-out totalizer; For floating add, the carry-in bit perseverance of mantissa adder device gets 0; For the floating-point subtraction, the carry-in bit perseverance of mantissa adder device gets 1, to realize the complementary operation of getting to the mantissa of the bigger floating-point operation number of index, this mantissa adder device is realized the sum operation to the mantissa of the mantissa of getting the floating-point operation number after the complement code and another floating-point operation number simultaneously.
The described totalizer that rounds off is an add with carry musical instruments used in a Buddhist or Taoist mass; For floating add, the totalizer that rounds off finish to mantissa and the operation of rounding off; For the floating-point subtraction, when the index difference of the first floating-point operation number and the second floating-point operation number is not 0, the totalizer that rounds off both finished to mantissa and the operation of rounding off, finish again to mantissa and get complementary operation; When the index difference of the first floating-point operation number and the second floating-point operation number is 0, and the mantissa of the first floating-point operation number is less than the mantissa of the second floating-point operation number, and the totalizer that rounds off is re-used and realizes result's the complementary operation of getting.
IEEE-754 floating-point standard is the standard about floating point arithmetic that IEEE is organized in 1985 promulgations, has become the floating-point standard of international uniform now.In this standard, defined single precision, double precision, extended pattern single precision, four kinds of floating-point formats of extended pattern double precision, and defined four kinds of rounding modes and relevant other content.
The data layout aspect, single precision floating datum is made up of 1 bit sign position, 23 mantissa of the inclined to one side exponential sum of 8 bit strips; Double-precision floating points is made up of 1 bit sign position, 52 mantissa of the inclined to one side exponential sum of 11 bit strips.Concrete form is with reference to figure 2.
Based on above-mentioned floating-point format, any one floating number can be expressed as following form:
F=(1)
s2
E(b
0.b
1b
2... b
P-1) (formula 2.1)
Wherein: s represents the symbol of floating number, gets 0 or 1;
E represents the index of floating number;
B represents a binary value, gets 0 or 1;
P represents the precision of floating number.
Simultaneously, IEEE-754 floating-point standard definition four kinds of rounding modes, be respectively be respectively nearby round off (Round to Nearest), to zero round off (Round toward Zero), to infinite rounding off (Round toward+INFINITY) just with to negative infinite rounding off (Round toward-INFINITY).Shown in following table (1):
| Nearest value is got and imported to the rounding mode round-off result, if up and down two values are approaching equally, then getting rounds off nearby to make least significant bit (LSB) be 0 value to zero round off with the input truncation to just infinite round off get and import recently and be not less than input value to the negative infinite value that rounds off and get and import recently and be not more than input |
Table 1
The floating add device is to be responsible for parts that floating add and floating-point subtraction are carried out computing, and its position in processor and computer system as shown in Figure 1.
The realization of the floating add subtraction in the present embodiment can divide following step:
1. the index that calculates two floating numbers is poor
2. according to the move to right mantissa of the little floating number of index of the index difference of two floating numbers, realize that mantissa is to rank
3. mantissa's summation
Mantissa and in first position probing of 1 or 0
5. round off according to rounding mode
6. to result's processing of standardizing
The flow process of concrete floating add subtraction is with reference to figure 4.
Here we define two operands of floating add computing, and X1 is counted in first floating-point operation and X2 is counted in second floating-point operation, and wherein each operand comprises three territories again, respectively is-symbol territory S, pointer field E and the territory F of mantissa.Therefore, X1={S1, E1, F1}, X2={S2, E2, F2}.
The index totalizer is the totalizer of a carry-in carry-out, and it accepts the index E 1 and the E2 of two operands, and finishes the operation of E1-E2.In order to represent the positive and negative of index addition results, need expand a bit sign position to index.Therefore, E is just arranged
Difference=E1-E2={0, E1}-{0, E2}={0, E1}+{0, the E2} benefit=0, E1}+{0, E
2}+1.The positive and negative of subtraction result represented in most significant digit is-symbol position.If most significant bits 0, E1 is more than or equal to E2 in expression, E1-E2=E
DifferenceOtherwise E1 is less than E2, E2-E1=-E
Difference=E
Difference+ 1.Specifically with reference to figure 5.
Shift unit is that (single precision: N=24, double precision: the barrel shifter that moves to right N=53), it is poor that it accepts the index of index totalizer input, and according to the index difference the less floating number of index is moved to right, to realize rank in a N position.If E
DifferenceFor just, represent E1 more than or equal to E2, shift unit is shifted to the mantissa of second operand to selecting so, and the mantissa that need move to right is E
Difference, this process be Fig. 6 1.; If E
DifferenceFor negative, E1 is less than E2 in expression, and shift unit is shifted to the mantissa of first operand to selecting so, and the figure place that need move to right is E2-E1=E2-E1=-E
Difference=E
Difference+ 1.Consider and work as E
DifferenceWhen negative, the distance that shift unit need be shifted is E
Difference+ 1, in order to save the hardware resource of an one adder, carry out particular processing to displacement this moment.To be shifted is divided into two stages to the rank process, and the phase one is 53 the barrel shifter that moves to right, and the distance that need move to right is E
Difference, this process be Fig. 6 1., subordinate phase is to continue to move to right one, only need this moment this process of selector switch be Fig. 6 2..By at E
DifferenceUnder negative situation, the process that is shifted to rank is resolved into the execution of two steps, reduced by a totalizer, saved hardware cost.To after the rank, the mantissa that we define the floating-point operation number is respectively and F ' through displacement
1And F '
2Work as E
DifferenceBe timing, F '
2Be F1, F '
1Be that F2 moves to right to the value after the rank; Work as E
DifferenceWhen negative, F '
1Be that F1 moves to right to the value after the rank, F '
2Be F2.The realization of concrete shift unit as shown in Figure 6.Fig. 7 is the sample of mantissa's displacement to rank.
Mantissa's operand ready logic is accepted the mantissa of displacement to two floating-point operation numbers after the rank, and they are prepared to offer the mantissa adder device of back level.The target of operand ready logic is to realize the unification of floating add subtraction.For additive operation X1+X2, the mantissa adder device need be realized F '
1+ F '
2, this moment, the operand ready logic was not done any operation, directly mantissa's bypass of shift unit input was given the mantissa adder device of back, kept the E that shifts out simultaneously
DifferenceThe position information of position is thought that the back is done and is rounded off.For subtraction X1-X2, the mantissa adder device need be finished F '
1-F '
2(X1＜X2) or F '
2-F '
1(X1＞X2).For floating-point subtraction and floating add is unified, this patent takes complement form to realize to mantissa's subtraction, i.e. F1-F2=F1+F
2+ 1.When first floating-point operation is counted X1 and is counted X2 greater than second floating-point operation, in order to keep the full detail position for the rounding off of back, the mantissa adder device need the bit wide of 2N realize (single precision: N=24, double precision: N=53), as shown in Figure 8.In order to save mantissa adder device resource and to obtain good delay performance, the operand ready logic has been done special optimization process at this, and at this moment, the operand ready logic is adjusted the position of two mantissa, always allows little mantissa deduct big mantissa.Work as E
DifferenceFor just, X1-X2=(F '
2-F '
1)=(F1-F '
1)=-(F '
1+ F1 mends)=-(F '
1+ F
1+ 1), the operand ready logic is with F '
1As the source 1 of mantissa adder device, with F
1Be about to the source 2 of F1 negate as the mantissa adder device.Work as E
DifferenceFor negative, X1-X2=F '
1-F '
2=F '
1-F '
2=F '
1+ F
2+ 1, the operand ready logic is with F '
1As the source 1 of mantissa adder device, with F
2Be about to the source 2 of F2 negate as the mantissa adder device.Work as E
DifferenceWhen being zero, this moment, the index of two floating-point operation numbers equated, the operand ready logic does not compare mantissa's size of two floating-point operation numbers, but according to F1-F2=F1+F
2+ 1, with the source 1 of F1, with F as the mantissa adder device
2Source 2 as the mantissa adder device.Concrete mantissa's operand ready logic as shown in Figure 9.The operand of mantissa's operand ready logic output is defined as F "
1And F "
2
The mantissa adder device is the totalizer of a carry-in carry-out, and it accepts the two-way operate source that mantissa's operand ready logic provides, and with its addition.For the carry situation of the positive and negative and addition results of representing the mantissa adder result, need be to two of mantissa's operand expansions, an is-symbol position, one is the carry indicating bit.For floating add, the carry-in of mantissa adder device is always 0; For the floating-point subtraction, the carry-in of mantissa adder device is always 1.Therefore, just have mantissa and=F "
1+ F "
2+ cin={0,0, F "
1}+{ 0/1,0/1, F "
2}+cin.Mantissa and most significant digit is-symbol position, the expression result's of mantissa is positive and negative, most significant digit is 0, expression mantissa and for just, most significant digit is 1, expression mantissa and for bearing.Concrete with reference to shown in Figure 9.
Round off decision logic according to the result of mantissa adder device, finish the judgement of rounding off mantissa's computing.Its basic functional principle is, when the result is positive number, from most significant digit begin to look for first 1, judgement is used to round off after this 1 backward N position (single precision is 24, and double precision is 53); When the result is negative value, from most significant digit begin to look for first 0, judgement is used to round off after this 0 backward N (single precision is 24, and double precision is 53) position.Judge to accelerate the process of looking for first significant figure in order to round off, round off decision logic only need to mantissa and preceding four judge.By to mantissa and most significant digit judge that most significant digit is 0 expression floating add, most significant digit is 1 expression floating-point subtraction.For floating add, mantissa's addition has only two kinds of situations, advances one or not-carry; For the floating-point subtraction, mantissa subtracts each other and has only two kinds of situations, borrows one or not borrow.Concrete process as shown in Figure 10 and Figure 11.
In this definition, the operand of judging that is used to round off is called the set position, represents with f, and the operand lowest order of operating that participates in rounding off is F
0
The concrete decision logic that rounds off is as follows:
One,,, round off by judging the size of set position when mantissa with for timing:
(1) when rounding mode for when zero rounds off, rounding off adds 0;
(2) when rounding mode for to the time to infinite rounding off just, when the floating add result be timing, round off to add 1, when the floating add result when bearing, rounding off adds 0;
(3) when rounding mode for to the time to negative infinite rounding off, when the floating add result when negative, rounding off adds 1, when the floating add result is timing, rounds off to add 0;
(4) when rounding mode for when zero rounds off, the set position greater than 0.5 or the set position equal 0.5 and the lowest order of the operand that rounds off be 1 o'clock, rounding off adds 1, the set position less than 0.5 or the set position equal 0.5 and the lowest order of the operand that rounds off be 0 o'clock, rounding off adds 0.
Can be expressed as with equation:
Round off+1=((rounding mode==just infinite) ﹠amp; ﹠amp; Sign bit
|| (rounding mode==negative infinite) ﹠amp; ﹠amp; Sign bit
|| (rounding mode==) ﹠amp nearby rounds off; ﹠amp; (f＞0.5|| (f==0.5) ﹠amp; ﹠amp; F
0))
&&(f！＝0)；
Two, when mantissa with when negative,, round off by judging the size of set position:
(1) when rounding mode for when zero rounds off, rounding off adds 0;
(2) when rounding mode for to the time to infinite rounding off just, when the floating add result is timing, round off to add 0, when the floating add result is timing, round off to add 1;
(3) when rounding mode for to the time to negative infinite rounding off, when the floating add result when negative, rounding off adds 0, when the floating add result is timing, rounds off to add 1;
(4) when rounding mode for when zero rounds off, the set position greater than 0.5 or the set position equal 0.5 and mantissa and lowest order be 1 o'clock, rounding off adds 0, the set position less than 0.5 or the set position equal 0.5 and mantissa and lowest order be 0 o'clock, rounding off adds 1.
Can be expressed as with equation
Round off+0=((rounding mode==round off to zero)
|| (rounding mode==just infinite) ﹠amp; ﹠amp; Sign bit
|| (rounding mode==negative infinite) ﹠amp; ﹠amp; Sign bit
|| (rounding mode==) ﹠amp nearby rounds off; ﹠amp; (f＞0.5|| (f==0.5) ﹠amp; ﹠amp; f
0))
&&(f！＝0)；
The true form that comprised the decision logic that rounds off decision logic and the complement code decision logic that rounds off that rounds off, based on above analysis, true form rounds off, and to add the round off condition that adds zero decision logic of a decision logic and complement code the same substantially, so can unify in logic.Based on such design, simplified the complicated decision logic that rounds off in the design of floating add subtraction greatly.
The totalizer that rounds off is an add with carry musical instruments used in a Buddhist or Taoist mass.When mantissa and be on the occasion of situation, the logic that rounds off and the totalizer collaborative work of rounding off finish to its mantissa and round off, only need directly to input to the totalizer that rounds off to the mantissa of operand this moment and get final product.But when mantissa be negative situation, the logic that rounds off and round off totalizer except finishing the operation of rounding off, also Parallel Implementation get the operation of complement code.Because get the process of complement code is that mantissa and negate are added one, the decision logic that rounds off of front is judged the situation of rounding off that the negate of set position adds after, so in order to finish the complementary operation of getting simultaneously to it, need be to the operand negate sign indicating number that rounds off, input to the totalizer that rounds off again after the operand negate that needs this moment to round off.The whole totalizer and round off logic as shown in figure 11 of rounding off.
The output of the totalizer that rounds off is exactly the result that the floating-point plus and minus calculation rounds off, and ensuing operation is exactly the encapsulation to the floating add subtraction result, and need encapsulate sign bit and exponential sum mantissa this moment according to the floating-point standard format.
Claims (9)
1. a floating add device that rounds off based on complement code is supported floating add operation and floating-point subtraction, and described floating add device comprises:
The index totalizer, the index that is used to calculate the first floating-point operation number and the second floating-point operation number is poor;
Mantissa's shift unit is used for being shifted to rank according to the index difference of the prime input mantissa to the less floating-point operation number of index;
It is characterized in that: described floating add device also comprises:
Mantissa operand ready logic unit is used for according to the sign bit and the index difference of the first floating-point operation number and the second floating-point operation number mantissa's operand being carried out following processing:
For the floating add operation, directly will be shifted to mantissa's input mantissa adder device of the floating-point operation number after the rank;
For the floating-point subtraction, if the index difference of the first floating-point operation number and the second floating-point operation number is not 0, according to the mantissa negate of index difference to the bigger floating-point operation number of index, and the mantissa of the less floating-point operation number of index remains unchanged; If the index difference of the first floating-point operation number and the second floating-point operation number is 0, regulation remains unchanged mantissa's negate of the second floating-point operation number to the mantissa of the first floating-point operation number;
The mantissa adder device is used for the mantissa's summation to the operand ready logic input of prime mantissa;
The decision logic unit that rounds off, according to the most significant digit of mantissa adder device output judge mantissa and positive and negative, be identified for the set position of rounding off and judging according to the Gao Siwei of mantissa adder device output;
The totalizer that rounds off is used for the mantissa adder result of floating-point is rounded off, and finish to mantissa and get complementary operation.
2. the floating add device that rounds off based on complement code according to claim 1, it is characterized in that: the described decision logic that rounds off is judged according to the most significant digit of mantissa adder device output, if mantissa adder most significant digit as a result is 0, represent that this operation result is true form and result for just, if mantissa adder most significant digit as a result is 1, represent that this operation result is that complement code and result are negative.
3. the floating add device that rounds off based on complement code as claimed in claim 1, it is characterized in that: the described decision logic unit that rounds off comprises true form decision logic subelement and the complement code decision logic subelement that rounds off that rounds off, and true form rounds off and adds a decision logic and complement code and round off that to add 0 decision logic unified logic be that complement code rounds off and adds 0 decision logic.
4. the floating add device that rounds off based on complement code as claimed in claim 2, it is characterized in that: the described decision logic unit that rounds off comprises true form decision logic subelement and the complement code decision logic subelement that rounds off that rounds off, and true form rounds off and adds a decision logic and complement code and round off that to add 0 decision logic unified logic be that complement code rounds off and adds 0 decision logic.
5. as the described floating add device that rounds off based on complement code of one of claim 1-4, it is characterized in that: described floating add device also comprises:
The result normalization shift unit is used for according to the floating point expression form sign bit and exponential sum mantissa being encapsulated.
6. as the described floating add device that rounds off based on complement code of one of claim 1-4, it is characterized in that: described mantissa adder device is a carry-in carry-out totalizer; For floating add, the carry-in bit perseverance of mantissa adder device gets 0; For the floating-point subtraction, the carry-in bit perseverance of mantissa adder device gets 1.
7. as the described floating add device that rounds off based on complement code of one of claim 1-4, it is characterized in that: the described totalizer that rounds off is an add with carry musical instruments used in a Buddhist or Taoist mass; For floating add, the totalizer that rounds off finish to mantissa and the operation of rounding off; For the floating-point subtraction, when the index difference of the first floating-point operation number and the second floating-point operation number is not 0, the totalizer that rounds off both finished to mantissa and the operation of rounding off, finish again to mantissa and get complementary operation; When the index difference of the first floating-point operation number and the second floating-point operation number is 0, and the mantissa of the first floating-point operation number is less than the mantissa of the second floating-point operation number, and the totalizer that rounds off is re-used and realizes result's the complementary operation of getting.
8. the floating add device that rounds off based on complement code as claimed in claim 5 is characterized in that: the described totalizer that rounds off is an add with carry musical instruments used in a Buddhist or Taoist mass; For floating add, the totalizer that rounds off finish to mantissa and the operation of rounding off; For the floating-point subtraction, when the index difference of the first floating-point operation number and the second floating-point operation number is not 0, the totalizer that rounds off both finished to mantissa and the operation of rounding off, finish again to mantissa and get complementary operation; When the index difference of the first floating-point operation number and the second floating-point operation number is 0, and the mantissa of the first floating-point operation number is less than the mantissa of the second floating-point operation number, and the totalizer that rounds off is re-used and realizes result's the complementary operation of getting.
9. the floating add device that rounds off based on complement code as claimed in claim 6 is characterized in that: the described totalizer that rounds off is an add with carry musical instruments used in a Buddhist or Taoist mass; For floating add, the totalizer that rounds off finish to mantissa and the operation of rounding off; For the floating-point subtraction, when the index difference of the first floating-point operation number and the second floating-point operation number is not 0, the totalizer that rounds off both finished to mantissa and the operation of rounding off, finish again to mantissa and get complementary operation; When the index difference of the first floating-point operation number and the second floating-point operation number is 0, and the mantissa of the first floating-point operation number is less than the mantissa of the second floating-point operation number, and the totalizer that rounds off is re-used and realizes result's the complementary operation of getting.
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| CN2009101525059A CN101650642B (en) | 2009-09-11 | 2009-09-11 | Floating point addition device based on complement rounding |
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| CN2009101525059A CN101650642B (en) | 2009-09-11 | 2009-09-11 | Floating point addition device based on complement rounding |
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| CN101847087B (en) * | 2010-04-28 | 2012-03-28 | 中国科学院自动化研究所 | Reconfigurable transverse summing network structure for supporting fixed and floating points |
| CN102243577A (en) * | 2010-05-10 | 2011-11-16 | 上海华虹集成电路有限责任公司 | Circuit for rapidly realizing floating-point addition |
| CN102103479B (en) * | 2011-03-02 | 2015-06-10 | 中兴通讯股份有限公司 | Floating point calculator and processing method for floating point calculation |
| CN104238992A (en) * | 2014-09-09 | 2014-12-24 | 南京航空航天大学 | High-performance imprecise floating point adder and application method thereof |
| CN105045558A (en) * | 2015-09-07 | 2015-11-11 | 浪潮(北京)电子信息产业有限公司 | Radix-minus-one complement adder |
| US9817661B2 (en) * | 2015-10-07 | 2017-11-14 | Arm Limited | Floating point number rounding |
| CN105426156B (en) * | 2015-10-28 | 2018-07-20 | 南京航空航天大学 | A kind of non-precision multiplier of high-performance and its application process |
| CN111290732B (en) * | 2020-03-03 | 2023-03-14 | 南京大学 | Floating-point number multiplication circuit based on posit data format |
| CN111538472B (en) * | 2020-04-27 | 2022-11-04 | 西安交通大学 | Positt floating point number arithmetic processor and arithmetic processing system |
| CN112527240B (en) * | 2020-12-22 | 2023-11-14 | 中国电子科技集团公司第四十七研究所 | Floating point operation device matched with 80C186CPU |
| CN113268219B (en) * | 2021-07-19 | 2021-10-19 | 中科南京智能技术研究院 | Adder circuit with binary complement conversion |
| CN113377334B (en) * | 2021-08-16 | 2021-11-02 | 北京微核芯科技有限公司 | Floating point data processing method and device and storage medium |
| CN115658004A (en) * | 2022-12-09 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | Method and apparatus for performing floating point data operations |
| CN117667008B (en) * | 2023-10-18 | 2024-09-24 | 上海合芯数字科技有限公司 | Rounding method, rounding system, rounding circuit and rounding computer equipment for decimal operation |
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