CN101646083A - High-efficiency AVS video code stream analyzing system and method thereof - Google Patents
High-efficiency AVS video code stream analyzing system and method thereof Download PDFInfo
- Publication number
- CN101646083A CN101646083A CN 200910099560 CN200910099560A CN101646083A CN 101646083 A CN101646083 A CN 101646083A CN 200910099560 CN200910099560 CN 200910099560 CN 200910099560 A CN200910099560 A CN 200910099560A CN 101646083 A CN101646083 A CN 101646083A
- Authority
- CN
- China
- Prior art keywords
- elongated
- code stream
- data
- avs video
- fixed length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention discloses a high-efficiency AVS video code stream analyzing system and a method thereof. Invariable-length analysis and variable-length analysis in the AVS video code stream are dividedinto two production line modes to be simultaneously carried out; in the respective analysis production line, two state machines are set according to code stream characteristic thereof, which are respectively used for controlling the operation of an invariable-length analysis module and the operation of a variable-length analysis module in the code stream. A fifo (first-in first-out buffer memory)is between the two state machines to be used for transition. The invention can fast realize the analysis of the invariable-length code word and the variable-length code word of the AVS video code stream, increases analyzing efficiency and reduces the complexity of an analysis circuit, and the AVS video code stream analysis circuit realized by the system has less circuit area, low working frequencyand low power consumption.
Description
Affiliated technical field
The present invention relates to the parsing field of quick A VS video code flow, specifically a kind of high-efficiency AVS video code stream analyzing system and method.
Background technology
The AVS video code flow is made up of fixed length code word and K rank index Columbus code word, and wherein the former is a fixed length, and the latter is elongated.According to " information technology advanced audio/video coding part 2: video " (GB/T 2000090.2-2006, hereinafter to be referred as the AVS agreement), form by the fixed length code word in the sequence head of code stream, the growth data, but in I, PB frame head, equal each self-contained 3 groups of avriable length codes, in band and macro block definition, each self-contained 1 group, 8 groups avriable length codes, above remainder is all the fixed length code word.In the piece definition, then be avriable length codes entirely simultaneously.These fixed length code words and avriable length codes (especially in the macro block definition) are interlaced, analyse for quick code stream analytic solutions and cause certain difficulty.Simultaneously, the K rank index Columbus that the AVS video adopts carries out the avriable length codes coding, in many groups avriable length codes of mentioning in the above, avriable length codes in the piece definition is particularly complicated, according to encoding characteristics, may produce from 0 rank to the various code words on 3 rank, its length is to be arbitrary value.In the AVS agreement, use ue (v), se (v), me (v) and ce (v) waits the dissimilar syntactic element of description, wherein (v) use 0～3 rank index Columbus sign indicating number, other use 0 rank index Columbus sign indicating number to ce.(value of syntactic element v) equals CodeNum itself to ue; (v): for symbol index Columbus sign indicating number is arranged, the value of element equals (1) k+1 * Ceil (k/2) to se, and wherein Ceil (x) is for getting the smallest positive integral that is not less than x; Me (v) needs to change according to table.(v) the syntactic element of Miao Shuing is the most complicated, need determine the code table that next codeword decoding is required according to current code value, and then next code word is decoded for ce.
After the AVS software decoder is analyzed, obtain following table:
| ??Symbol?Name | ??％ | ??Avg./MB(clk?of?cpu) |
| ??Idct | ??24 | ??4,701 |
| ??Intra/inter?pred | ??20 | ??3,918 |
| ??Deblock | ??18 | ??3,528 |
| ??Decode_golomb_word | ??11 | ??2,155 |
| ??Others | ??27 | ??5,289 |
Two modules of motion compensation and loop filtering have taken the cpu resource of half nearly, and in remaining module, code stream analyzing and decoded portion have also taken the cpu resource of 10%～20% (a plurality of code stream statistics).Realizing with software in code stream analyzing and the decoding that current code word is analyzed in common use displacement mode relatively by turn, therefore common CPU structure all can't increase the speed of code stream analyzing and decoding.Can normally move because of resolving other modules of decoding problems affect undoubtedly when handling big image in different resolution, the resource of CPU should more be distributed on the module that can improve the picture decoding quality.
On the other hand, because the particularity of AVS code stream, its avriable length codes and fixed length code word are intersected mutually, can't use independently fixed length resolver and elongated resolver that code stream is resolved respectively, and then decoding.
In sum, elongated interlaced in the code stream of AVS is formed with code word fixed length, make in the whole code stream analyzing, promptly need to carry out fixed length code and resolve, need variable length code to resolve again.Especially the K rank index Columbus mode that partly adopts of variable length code is encoded, because the code length of variable length code is by its previous code word content decision, can not as separating fixed length code, know definite code length in advance during parsing, only after solving current code word, could determine the starting position and the decoding process of next code word according to the length of current code word.As seen normally used single clock analytic efficiency is too low, can't reach real time parsing, and code stream analyzing system control is very complicated.Thereby cause the resolution system circuit area big, and can't satisfy the demand of specific occasion low-power consumption.
Summary of the invention
In order to solve fixed length, the parsing of elongated index Columbus sign indicating number, and when increasing the analytic solutions code efficiency, can reduce parser circuitry complexity and power consumption, according to system of the present invention and the method that provides, can realize that a kind of circuit area is little, low in energy consumption and realize the method for AVS video code stream analyzing fast.Verify on Xilinx VirtexII 3000 platforms according to native system, under the operating frequency of 27MHz, can realize the AVS JizhunProfile@10Mbps code stream of 1080P is resolved and decoded.
The mode that high-efficiency AVS video code stream analyzing system of the present invention is resolved the fixed length in the AVS code stream and elongated parsing is divided into two streamlines is carried out simultaneously, in resolution flow waterline separately, according to its code stream feature two state machines are set, be respectively applied for the running of fixed length code word parsing module in the control stream and the running of avriable length codes parsing module, adopt a fifo (buffer memory of first in first out) to come transition in the middle of two state machines.Module is fixed according to the empty full State Control of fifo, the job initiation situation of elongated two parsing modules.Fixed length code word parsing module is responsible for fixed length code character segment in the AVS agreement is resolved.Analytical range comprises: all fields in sequence head, I/P/B frame head, the slice head (removing the mb_skip_run field).This module is by the field of the current and next decoding of state machine control, from source code flow request msg that trend is imported, add up filling bit number in the current code stream, judge new slice.The avriable length codes parsing module is responsible for avriable length codes in the AVS agreement is partly resolved.Analytical range comprises: (v), (v), (v), ce (v) for se for me for ue.And the code word that parses is sent into the decoded stream waterline decode.The streamline of decoding is responsible for the avriable length codes that will parse and is decoded by different requirement the separately, and wherein (value of syntactic element v) equals CodeNum itself to ue; (v): for symbol index Columbus sign indicating number is arranged, the value of element equals (1) k+1 * Ceil (k/2) to se, and wherein Ceil (x) is for getting the smallest positive integral that is not less than x; Me (v) needs to change according to table.(v) the syntactic element of Miao Shuing is the most complicated, need determine the code table that next codeword decoding is required according to current code value, and then next code word is decoded for ce.
The AVS video code stream analyzing module that native system is realized, on Xilinx VirtexII 3000 platforms, verify, during 27MHz work dominant frequency, can realize the AVS Jizhun Profile@10Mbps code stream of 1080P is resolved and decoded, when increasing the code stream processing speed, still guarantee lower operating frequency, thereby reduce the actual hardware power consumption.
Description of drawings
Below in conjunction with drawings and Examples native system is further specified.
Fig. 1 is the structured flowchart that high-efficiency AVS video code stream of the present invention is separated system.
Fig. 2 is the fixed length parse state machine state redirect figure of the embodiment of the invention.
Each state description is as follows:
Power_up: power-up initializing state;
Sequence_header, sequence_0～sequence_12: resolve the slice header state;
I_picture_header, i_0～i_8: resolve I frame head state;
Pb_picture_header, pb_0～pb_5: resolve PB frame head state;
Slice_header, s_0a～s_2g: resolve slice (removing the mb_skip_run field) state;
Swait: idle waiting state.
Fig. 3 is the elongated parse state machine state redirect figure of embodiments of the invention.
Each state description is as follows among Fig. 3:
Power_up: power-up initializing state;
Decoding_mb_skip_run: resolve mb_skip_run skip macroblock count area state;
Decoding_mb_type: resolve mb_type macro block (mb) type field status;
Decoding_mb_part_type: resolve mb_part_type macro block sub-type field state;
Decoding_intra_luma_mode: resolve luminance patterns field status in the intra_luma_mode frame;
Decoding_chroma_pred_mode: resolve prediction mode for chroma field status in the chroma_pred_mode frame;
Decoding_mb_reference_index: resolve mb_reference_index macro block reference key field status;
Decoding_mv_diff_x: resolve mv_diff_x motion vector horizontal component difference field status;
Decoding_mv_diff_y: resolve mv_diff_y motion vector vertical component difference field status;
Decoding_mbweighting_prediction: resolve mbweighting_prediction weight estimation field status;
Decoding_cbp: resolve cbp macroblock coding template field state;
Decoding_mb_qp_delta: resolve mb_qp_delta macroblock quantization parameter delta field state;
Decoding_trans_coefficient: resolve trans_coefficient variation coefficient field status;
Decoding_escape_level_diff: resolving escape_level_diff changes ease coefficient difference value field state;
Wait_mb_skip_run: wait for the macroblock skip state;
Wait_p_skip_or_b_skip: wait for p frame or b frame skip state.
Fig. 4 is the elongated analytical framework figure of embodiments of the invention.
Elongated data processing: the fixed length number that is input to elongated parsing module is made up, and send into special parsing modules such as ue;
Ue, me, se, ce: corresponding A VS agreement is carried out the module of special parsing.
Fig. 5 is the parsing decoding process figure of embodiments of the invention.
Embodiment
The mode that native system is resolved the fixed length in the AVS code stream and elongated parsing is divided into two streamlines is carried out simultaneously, with reference to figure 1.In resolution flow waterline separately, according to its code stream feature two state machines are set, be respectively applied for the 8bit state machine fixed length parsing of the above syntactic element of slice and the elongated parsing of 32bit state machine of the following syntactic element of slice.Bound fraction adopts a fifo to come transition.The fifo throat width is 8bit, and exit width is 32bit, and the degree of depth is 8bit*1024=32bit*256.The data bandwidth that is used for the elongated parsing module requirement of final result is bigger than fixed length parsing module, and the band content is done speed-buffering.
According to the empty full state of fifo, fixed, elongated two parsing modules judge whether to begin parsing work automatically.
Fixed length code word parsing module is partly resolved fixed length in the agreement.Analytical range comprises: all fields in sequence head, I/P/B frame head, the slice header (removing mb_skip_run macroblock skip count area).This module is by the field of the current and next decoding of state machine control, automatically to prime cache request source code flow data, with reference to figure 2.Add up and fill the bit number in the current code stream.Produce functions such as new band reset portion sub state machine register.
After the source code flow of input is resolved, the data that obtain are not byte-aligned usually, if deposit fifo in by the mode that does not line up, just there are the data that remain in fifo to read when then reading by 32bit, so when depositing fifo in, need to calculate simultaneously the data number that deposits in and whether be 4 multiple, if last the discovery do not satisfied, then need artificially to add 0xFF, convenient with left and right sidesing shifting resume module in elongated parsing module.And in the end also fill 0x1 as a supplement on the residue bit of a not enough 8bit.
After fixed length parse state machine brings into operation, need the field of resolving in all corresponding agreement of each state.Behind 0x000001BxFFFF, begin to resolve.In fixed length parse state machine, no matter be sequence head or I/P/B frame head or slice header parsing intact after, all enter into the power_up state; After the slice data have outwards been carried, (do not resolve, only carry), enter the power_up state yet.A special state swait is arranged in addition: i.e. itself does not resolve field fixed length parsing, but all data that will arrive before the next slice are all given elongated parsing module, when detecting next slice or frame or sequence head again and being detected, enters the power_up state.In the fixed length resolving, Autonomous Control enters the bit stream data of this module, and puts into fifo, a frame at first, module is received the frame decoding enabling signal, unconditionally outwards sends request, so that obtain bit stream data at once.When ordinary circumstance, if fifo is empty, when receiving that signal is finished in current macro Columbus parsing, current macro numbering and the current macro block of skipping are carried out addition, judge that whether this value surpasses the intra-frame macro block sum, and calculate in the variable modules in the 64bit buffer memory whether consistent on the real surplus bit and filling bit number simultaneously.Also need to judge, be resolved to last macro-block line of frame, but self count of macroblocks device is not counted to last macro block.Determine jointly by above three: current parsing draws to an end, but unsure certificate or have only byte of padding among the fifo at this time just need read source code flow a part of in fifo.
With reference to Fig. 3, what each elongated parsing module can read from fifo continuously is 250 cycles, when the number of reading at last is not 0x000001, illustrate that later data also belong to next NEW BEGINNING, still belong in the current macro scope, when the fifo capacity is big or small far below actual slice so this condition is determined, need to divide several times data to be deposited in the situation of fifo.When the slice content fixed length resolved, module is found next 0x000001 data, need stop new data and enter module, is stopping request simultaneously, state machine enters the swait state.When being resolved to new slice processing, need reset to fifo.Enable common judgement by swait state and input in the state machine.When state machine is in the swait state, illustrate that the fixed length parsing module is idle, and wait for new input, and there is new input this moment, so produce resetting of a fifo at this moment.After resetting, the fixed length parsing module spends a period of time on fixed length is resolved, and does not deposit data in fifo immediately.Fifo resolves as fixed length and the middle buffer module of elongated parsing, fixed length is resolved the mode of the residue code stream one or many in the back slice and deposits so far, calls for elongated parsing module.So when first when using fifo, (just after 4 * 32bit), this moment, elongated parsing module can be resolved when depositing 16 * 8bit in.
Elongated parsing module is (with reference to figure 4) except elongated parse state machine, also comprises ue field parsing module, me field parsing module, se field parsing module and elongated data processing module and ce module (these four parsing modules of following general designation are special elongated data resolution module).Each submodule is resolved multi-form avriable length codes respectively.And elongated data processing module is used to control the job order of each submodule that it comprises, data dispatch etc.Elongated parse state machine is used for controlling whole elongated resolving each sequence of steps and the indivedual fixed-length fields of elongated parsing is resolved.Contain the 64bit fast cache in the elongated data processing module, be used for data recombination, and each all complete data with 32bit send into module such as ue and carry out variable length code and resolve, with reference to figure 5.This module is started by elongated parse state machine control, when elongated parse state machine determines that next field to be resolved is variable-length field, starts elongated data processing module.Variable length code resolve finish after, untapped bit number is given elongated data processing module among the feedback 32bit, module can be adjusted data in the 64bit buffer memory according to value of feedback, and the data of resolving for variable length code are next time prepared.
According to native system, when two parse state machines or any intermediate data processing module are found the error in data of having resolved or do not met protocol requirement, enter power_up state separately automatically, and can wait for always that correct code stream enters, and continuation is decoded.State machine is defined as wrong code stream: 1. data can't be resolved; 2. analysis result and AVS agreement correspondence position do not meet; 3. analysis result exceeds AVS agreement data of corresponding positions scope; 4. analysis result meets the AVS agreement, but does not meet the given parameter of decode system, exceeds the given magnitude range of decoder etc. as the image of resolving.Elongated and metrostasis machine is judged code word with crossing the AVS agreement, does not appear in the video code flow so can compatible meet the data of AVS agreement, and during the data that for example occur occurring makeing mistakes between two normal frame data, native system has fault tolerant mechanism.
What should be understood that is: the foregoing description is just to explanation of the present invention, rather than limitation of the present invention, and any innovation and creation that do not exceed in the connotation scope of the present invention all fall within protection scope of the present invention.
Claims (11)
1. high-efficiency AVS video code stream analyzing system, fixed length in the AVS video code flow and avriable length codes are resolved, it is characterized in that: according to the feature of code word in the AVS video code flow, fixed length part and elongated part are independently resolved respectively in two state machines, use fifo that code stream is carried out buffer memory between the two.
2. a kind of high-efficiency AVS video code stream analyzing system according to claim 1 is characterized in that the fixed length parsing module is made up of fixed length parse state machine and pilot process processing module:
Each state in the fixed length parse state machine all corresponds to each fixed length code word in the AVS video protocols, comprises its length and code word implication.
Fixed length code word next to be decoded is judged and determined to fixed length parse state machine automatically.
Fixed length parse state machine Autonomous Control and the original AVS video code flow of request input.
The fixed length parsing module is sent elongated partial data into buffer memory among the fifo after the fixed length of code stream partly finishes, and can determine whether to continue original AVS code stream is outputed to fifo according to the empty full degree of fifo.
3. a kind of high-efficiency AVS video code stream analyzing system according to claim 1, it is characterized in that metadata cache fifo inlet is the 8bit width, outlet is the 32bit width, the full degree of the sky of fifo is determined the operating state of elongated parse state machine: start when valid data are no less than 32bit in fifo, all valid data of single slice all are to have to close after finishing in fifo.
4. a kind of high-efficiency AVS video code stream analyzing system according to claim 3, it is characterized in that each state in the elongated parse state machine all correspond to the AVS video protocols in each avriable length codes, only comprise the code word implication, do not comprise code word size, elongated parse state machine is after knowing the code word implication that will decode, the 32bit data that transmit a fixed length are to elongated data processing module, and after knowing the code word implication that to decode, need to determine the special data parsing module of startup, comprise ue, me, se, ce parsing module.
5. a kind of high-efficiency AVS video code stream analyzing system according to claim 3, the buffer memory that it is characterized in that the inner 64bit of use of elongated data processing module, according to remaining the bit number among the last 32bit that effectively bit number, back level special data parsing module use in the inner buffer, need to determine whether request fifo to send into the original AVS video codeword data stream of next 32bit in buffer memory, after each avriable length codes is resolved the back or obtained the original AVS video data of new 32bit, all calculate effective bit number in the current 64bit buffer memory again.
6. according to claim 3 and 4 described a kind of high-efficiency AVS video code stream analyzing systems, it is characterized in that the feature according to the AVS video code flow is provided with ue, me, se, ce parsing module respectively in the elongated parsing module, be called the special data parsing module, be respectively applied for and resolve corresponding AVS video code flow, after the special data parsing module is resolved code stream at every turn, need feed back to residue bit number among the 32bit that elongated data processing module feeds.
7. according to claim 3 and 4 described a kind of high-efficiency AVS video code stream analyzing systems, it is characterized in that the startup of special data parsing module is controlled by elongated parse state machine, after having resolved an avriable length codes, stop automatically.
8. a kind of high-efficiency AVS video code stream analyzing system according to claim 1, it is characterized in that when the non-AVS video code flow of the AVS video code flow that can't resolve of input or input data, can continue wait for can be resolved up to the data fit of input the AVS video code flow, and proceed to resolve.
9. high-efficiency AVS video code stream analyzing method, it is characterized in that the fixed length in the AVS code stream resolved and mode that elongated parsing is divided into two streamlines is carried out simultaneously, in resolution flow waterline separately, according to its code stream feature corresponding state machine is set, bound fraction adopts a fifo to come transition, according to the empty full state of fifo, fixed, elongated two parsing modules judge whether to begin parsing work automatically:
The fixed length parsing module, fixed length in the agreement is partly resolved, analytical range comprises sequence head, I/P/B frame head, removes all fields in the slice header of mb_skip_run macroblock skip count area, this module is by the field of the current and next decoding of state machine control, automatically to prime cache request source code flow data, add up and fill the bit number in the current code stream, produce new band reset portion sub state machine register;
Elongated parsing module is resolved elongated part in the agreement, is started by elongated parse state machine control, when elongated parse state machine determines that next field to be resolved is variable-length field, starts elongated data processing module; Variable length code resolve finish after, untapped bit number is given elongated data processing module among the feedback 32bit, module can be adjusted data in the 64bit buffer memory according to value of feedback, and the data of resolving for variable length code are next time prepared.
10. a kind of high-efficiency AVS video code stream analyzing method as claimed in claim 9, it is characterized in that the fixed length parsing module is after resolving the source code flow of input, when depositing fifo in, the data that will obtain calculate the data number that deposits in simultaneously and whether are 4 multiple, if last the discovery do not satisfied, then need artificially to add 0xFF, convenient with left and right sidesing shifting resume module in elongated parsing module, and in the end also fill 0x1 as a supplement on the residue bit of a not enough 8bit.
11. as claim 9 or 10 described a kind of high-efficiency AVS video code stream analyzing methods, it is characterized in that when two parse state machines or any intermediate data processing module are found the error in data of having resolved or do not met protocol requirement, automatically enter power_up state separately, and wait for that always correct code stream enters, continue decoding then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910099560 CN101646083B (en) | 2009-06-18 | 2009-06-18 | AVS video code stream analyzing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910099560 CN101646083B (en) | 2009-06-18 | 2009-06-18 | AVS video code stream analyzing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101646083A true CN101646083A (en) | 2010-02-10 |
| CN101646083B CN101646083B (en) | 2012-02-08 |
Family
ID=41657763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910099560 Expired - Fee Related CN101646083B (en) | 2009-06-18 | 2009-06-18 | AVS video code stream analyzing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101646083B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102469307A (en) * | 2010-11-12 | 2012-05-23 | 珠海全志科技股份有限公司 | Decoder and code stream analyzing device |
| CN103984665A (en) * | 2014-06-05 | 2014-08-13 | 哈尔滨工业大学 | Serial port communication device and method based on LabVIEW |
-
2009
- 2009-06-18 CN CN 200910099560 patent/CN101646083B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102469307A (en) * | 2010-11-12 | 2012-05-23 | 珠海全志科技股份有限公司 | Decoder and code stream analyzing device |
| CN102469307B (en) * | 2010-11-12 | 2014-04-16 | 珠海全志科技股份有限公司 | Decoder and code stream analyzing device |
| CN103984665A (en) * | 2014-06-05 | 2014-08-13 | 哈尔滨工业大学 | Serial port communication device and method based on LabVIEW |
| CN103984665B (en) * | 2014-06-05 | 2017-06-20 | 哈尔滨工业大学 | Serial communication device and method based on LabVIEW |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101646083B (en) | 2012-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7595743B1 (en) | System and method for reducing storage requirements for content adaptive binary arithmetic coding | |
| EP1784986B1 (en) | Parameter set and picture header in video coding | |
| US10104401B2 (en) | Efficient software for transcoding to HEVC on multi-core processors | |
| CN101198051B (en) | Method and device for implementing entropy decoder based on H.264 | |
| EP2839652B1 (en) | Fixed tile structure flag indicating parallel processing possibility for a sequence of compressed video | |
| CN103124353A (en) | Motion prediction method and video coding method | |
| US10341686B2 (en) | Method for dynamically adapting the encoding of an audio and/or video stream transmitted to a device | |
| CN104604235A (en) | Transmitting apparatus and method thereof for video processing | |
| CN109660879A (en) | Frame losing method, system, computer equipment and storage medium is broadcast live | |
| CN104025594A (en) | Tile size in video coding | |
| CN102802024A (en) | Transcoding method and transcoding system realized in server | |
| CN102857746A (en) | Method and device for coding and decoding loop filters | |
| CN102186075B (en) | Entropy coder and realization method thereof | |
| CN105072360A (en) | Multi-screen splicing control and display system and multi-screen splicing control and display method | |
| CN101646083B (en) | AVS video code stream analyzing system | |
| CN112422986B (en) | Hardware decoder pipeline optimization method and application | |
| CN101272497B (en) | Video encoding method | |
| CN110351552B (en) | Fast coding method in video coding | |
| CN100417227C (en) | High performance pipeline system in use for AVS video decoder | |
| CN102196253A (en) | Video coding method and device based on frame type self-adaption selection | |
| US20150334391A1 (en) | Region-based processing of predicted pixels | |
| Iwata et al. | A 256 mW 40 Mbps full-HD H. 264 high-profile codec featuring a dual-macroblock pipeline architecture in 65 nm CMOS | |
| CN103826120A (en) | Code stream parser applicable to HEVC | |
| CN1229989C (en) | Decoding method for reducing delay time | |
| CN103581685A (en) | Method and device for selecting H.264 reference frames |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120208 Termination date: 20140618 |
|
| EXPY | Termination of patent right or utility model |