CN103826120A - Code stream parser applicable to HEVC - Google Patents
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Abstract
The invention relates to a code stream parser applicable to high efficiency video coding (HEVC). The code stream parser comprises a code stream parsing state control module, an EG0 decoding module, an adjacent upper block information and related parameter storage unit, a decoding output storage unit, a code stream first in/first out (FIFO), and a context-adaptive binary arithmetic coding (CABAC) decoding module, wherein the EG0 is 0-order sequence exponential-Golomb code; the code stream FIFO is respectively connected to the CABAC decoding module and the EG0 decoding module through buffering displacement; the EG0 decoding module is connected to the CABAC decoding module through the code stream parsing state control module; the EG0 decoding module is connected to the CABAC decoding module through the adjacent upper block information and related parameter storage unit. The code stream parser disclosed by the invention redesigns a state machine depending on syntax element division in HEVC standard, and can greatly improve data throughout; meanwhile, through storage and corresponding synchronization logic of coding tree unit context variable and independent fragment context variable, the code stream parser realizes a synchronizing function on non-independent fragment context variable specified within the HEVC standard as well as coding tree unit context variable to be synchronized.
Description
Technical field
The present invention relates to the code stream analyzing device of a kind of HEVC of being applicable to, belong to the technical field of digital video signal encoding and decoding.
Background technology
HEVC(High Efficiency Video Codec) be to combine the international video encoding standard of a new generation in formulation by international telecommunication tissue (ITU) and Motion Picture Experts Group (MPEG) at present.With present international video standard H.264/AVC compared with, HEVC can guarantee under the prerequisite of identical image quality, and the code check of video is reduced to 50%.But corresponding, the computation complexity of HEVC has improved 2 to 3 times.Compared with H.264, the coded system of HEVC only has 0 rank order index Columbus coding and CABAC to encode two kinds, does not re-use CAVLC coding.With H.264 the same, in HEVC, the bottleneck of code stream analyzing remains CABAC decoding.
Encode first and to be coded on the division of syntactic element and corresponding code encoding/decoding mode and to improve than, the CABAC in HEVC with the CABAC H.264.In accompanying drawing 1, show the syntactic element that uses CABAC coding in HEVC.These syntactic elements have been described the characteristic of coding unit (CU), predicting unit (PU), conversion unit (TU) and the loop filter (LF) of the block of pixels of coding.For CU, these syntactic elements have been described the structure of piece and the predictive mode of this CU (in frame or interframe); For PU, what the syntactic element in form was described is intra prediction mode and a series of movable information; For TU, mainly comprise the information such as variation coefficient, symbol of residual matrix; LF syntactic element is transmission primaries in each maximum coding unit LCU, has described type and the side-play amount of SAO in loop filtering.These improvement make CABAC module can have larger data throughout, but have also caused the variation of decode procedure.
Out, outside above-mentioned variation, in concrete CABAC decode procedure, the initialization module in HEVC has increased storage and the synchronizing function of context variable, and this variation causes current CABAC joint decoder module in H.264 no longer applicable.
Summary of the invention
For the deficiencies in the prior art, the present invention relates to the code stream analyzing device of a kind of HEVC of being applicable to.
Technical scheme of the present invention is as follows:
The present invention relates to the code stream analyzing device of a kind of HEVC of being applicable to, comprise code stream analyzing status control module, EG0 decoder module, adjacent upper block message and relevant parameter memory cell, decoding output memory cell, code stream FIFO and CABAC decoder module; Described EG0 refers to 0 rank order index Columbus;
Described code stream FIFO is connected with EG0 decoder module with described CABAC decoder module respectively by buffer displacement, and described EG0 decoder module is connected with described CABAC decoder module by code stream analyzing status control module; Described EG0 decoder module is connected with described CABAC decoder module by adjacent upper block message and relevant parameter memory cell;
Described CABAC decoder module comprises CABAC arithmetic decoding, output module and the control of CABAC state; Described CABAC arithmetic decoding is connected with described decoding output memory cell by output module; Described ABAC arithmetic decoding is connected with the control of described CABAC state, and the control of described CABAC state is connected with described decoding output memory cell by output module;
Described buffer displacement is connected with described CABAC arithmetic decoding, and described adjacent upper block message and relevant parameter memory cell are connected with the control of described CABAC state;
Described code stream analyzing status control module is the control centre of whole code stream analyzing device, according to the code stream composition stipulating in HEVC standard and corresponding parsing order, described code stream analyzing status control module is coordinated the work of EG0 decoder module and CABAC decoder module, completes the decode operation of corresponding syntactic element;
Described EG0 decoder module has been used for the decode operation of the syntactic element that uses 0 rank orders index Columbus coding, specifically includes character type and without two kinds of character types;
Described adjacent upper block message and relevant parameter memory cell adopt SRAM to realize, for storing following information:
(1) adjacent upper piece syntax element value, the value of these syntactic elements is for calculating the model index delta of corresponding syntactic element: after the complete macroblock syntax elements value of every solution, upgrade adjacent on the syntax element value of block message SRAM relevant position; By immediately dynamically updating, can avoid storing the syntax elements value of two row macro blocks, and then save memory space, and not affect the calculating of model index delta value simultaneously;
(2) relevant parameter needing for CABAC decode procedure: comprise sequence parameter set, picture parameter set and head syntax element value;
Described decoding output memory cell, for storing residual matrix and the movable information of CABAC decoding output; Because data volume is very large, so adopt SRAM to realize, simultaneously, in order to reduce time delay, the collaborative work of the modules such as realization and inverse quantization, inverse transformation, adopts two SRAM to realize ping-pong operation pattern, for example, when CABAC output module is toward in SRAM1 when data writing, inverse quantization/inverse transform block reads residual error coefficient value from SRAM2.By such realization, can make each module move simultaneously;
Described code stream FIFO for temporary transient memory code stream information, realizes the asynchronous access of code stream information simultaneously;
Described CABAC decoder module, for realizing the decode operation of the syntactic element that uses CABAC coding: comprise CABAC arithmetic decoding module, CABAC status control module and output module.
Preferred according to the present invention, described CABAC arithmetic decoding module comprises arithmetic decoding and renormalization unit and context model administrative unit;
Above-mentioned arithmetic decoding and renormalization unit comprise regular decode logic, bypass decode logic and termination decode logic, and this unit is all realized by combinational logic; This unit selects corresponding decoding mode to decode by the decoding type stipulating in HEVC standard, upgrades current interval width, interval biasing and context variable simultaneously;
Above-mentioned context model administrative unit can complete the initialization of each context model or the initialization of synchronous and arithmetic decoding engine according to corresponding initialization flow process separately in the time resolving new slice, new tile and new a line CTU; Meanwhile, this unit can also be according to memory requirement, and the context variable of just corresponding CTU and slice segment is deposited in corresponding register; In order to improve decoding speed, need within a clock cycle, complete the renewal of context model information, and obtain the context model information that next wish solution bit needs.This administrative unit is controlled by CABAC status control module, and each clock reads in the context model value after arithmetic decoding unit upgrades, the context model value that output decoding simultaneously needs.When reading in when identical with the context model of exporting, arithmetic decoding unit is by the context model value (being the model value that administrative unit is read in) directly using after renewal), like this, can avoid the wait of a clock;
Above-mentioned CABAC status control module is used for according to the code stream composition and the decoding order that stipulate in standard, and state of a control redirect, controls the renewal of corresponding context variable simultaneously and read, and completes corresponding CABAC decode operation;
Above-mentioned output module is for realizing the output control of the result to CABAC decoding.
Preferred according to the present invention, the decoding process of described EG0 decoder module includes character type and without two kinds of character types, this resolver adopts the mode of solidifying look-up table in hardware to realize above-mentioned two kinds of decoding processes.In order to improve decoding efficiency, in the present invention, adopt the mode of solidifying look-up table in hardware to realize this two kinds of decoding processes.
Preferred according to the present invention, described code stream FIFO width is 8.Facilitate the use of CABAC module.
Advantage of the present invention:
Compared with prior art, code stream analyzing device of the present invention is applicable to syntactic element resolving improved in HEVC, and its CABAC decode procedure meets the requirement of HEVC.
Code stream analyzing device of the present invention is divided and is redesigned state machine according to the syntactic element in HEVC standard, can greatly choose high data throughput; Increase storage and the corresponding synchronous logic of code tree unit context variable and independent segments context variable simultaneously, can realize the dependent fragment context variable stipulating in HEVC standard and the synchronizing function that needs synchronous code tree unit context variable.Meanwhile, the submodule of code stream analyzing device of the present invention is divided rationally, can realize the pile line operation of reading, decode, exporting of code stream, improves greatly decoding efficiency.
Accompanying drawing explanation
Fig. 1 uses the syntactic element of CABAC coding to divide in HEVC;
Fig. 2 is the hardware structure of HEVC code stream analyzing device.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in more detail, but be not limited to this.
Embodiment,
Be applicable to a code stream analyzing device of HEVC, comprise code stream analyzing status control module, EG0 decoder module, adjacent upper block message and relevant parameter memory cell, decoding output memory cell, code stream FIFO and CABAC decoder module; Described EG0 refers to 0 rank order index Columbus;
Described code stream FIFO is connected with EG0 decoder module with described CABAC decoder module respectively by buffer displacement, and described EG0 decoder module is connected with described CABAC decoder module by code stream analyzing status control module; Described EG0 decoder module is connected with described CABAC decoder module by adjacent upper block message and relevant parameter memory cell;
Described CABAC decoder module comprises CABAC arithmetic decoding, output module and the control of CABAC state; Described CABAC arithmetic decoding is connected with described decoding output memory cell by output module; Described ABAC arithmetic decoding is connected with the control of described CABAC state, and the control of described CABAC state is connected with described decoding output memory cell by output module;
Described buffer displacement is connected with described CABAC arithmetic decoding, and described adjacent upper block message and relevant parameter memory cell are connected with the control of described CABAC state;
Described code stream analyzing status control module is the control centre of whole code stream analyzing device, according to the code stream composition stipulating in HEVC standard and corresponding parsing order, described code stream analyzing status control module is coordinated the work of EG0 decoder module and CABAC decoder module, completes the decode operation of corresponding syntactic element;
Described EG0 decoder module has been used for the decode operation of the syntactic element that uses 0 rank orders index Columbus coding, specifically includes character type and without two kinds of character types;
Described adjacent upper block message and relevant parameter memory cell adopt SRAM to realize, for storing following information:
(1) adjacent upper piece syntax element value, the value of these syntactic elements is for calculating the model index delta of corresponding syntactic element: after the complete macroblock syntax elements value of every solution, upgrade adjacent on the syntax element value of block message SRAM relevant position; By immediately dynamically updating, can avoid storing the syntax elements value of two row macro blocks, and then save memory space, and not affect the calculating of model index delta value simultaneously;
(2) relevant parameter needing for CABAC decode procedure: comprise sequence parameter set, picture parameter set and head syntax element value;
Described decoding output memory cell, for storing residual matrix and the movable information of CABAC decoding output; Because data volume is very large, so adopt SRAM to realize, simultaneously, in order to reduce time delay, the collaborative work of the modules such as realization and inverse quantization, inverse transformation, adopts two SRAM to realize ping-pong operation pattern, for example, when CABAC output module is toward in SRAM1 when data writing, inverse quantization/inverse transform block reads residual error coefficient value from SRAM2.By such realization, can make each module move simultaneously;
Described code stream FIFO for temporary transient memory code stream information, realizes the asynchronous access of code stream information simultaneously;
Described CABAC decoder module, for realizing the decode operation of the syntactic element that uses CABAC coding: comprise CABAC arithmetic decoding module, CABAC status control module and output module.
Described CABAC arithmetic decoding module comprises arithmetic decoding and renormalization unit and context model administrative unit;
Above-mentioned arithmetic decoding and renormalization unit comprise regular decode logic, bypass decode logic and termination decode logic, and this unit is all realized by combinational logic; This unit selects corresponding decoding mode to decode by the decoding type stipulating in HEVC standard, upgrades current interval width, interval biasing and context variable simultaneously;
Above-mentioned context model administrative unit can complete the initialization of each context model or the initialization of synchronous and arithmetic decoding engine according to corresponding initialization flow process separately in the time resolving new slice, new tile and new a line CTU; Meanwhile, this unit can also be according to memory requirement, and the context variable of just corresponding CTU and slice segment is deposited in corresponding register; In order to improve decoding speed, need within a clock cycle, complete the renewal of context model information, and obtain the context model information that next wish solution bit needs.This administrative unit is controlled by CABAC status control module, and each clock reads in the context model value after arithmetic decoding unit upgrades, the context model value that output decoding simultaneously needs.When reading in when identical with the context model of exporting, arithmetic decoding unit is by the context model value (being the model value that administrative unit is read in) directly using after renewal), like this, can avoid the wait of a clock;
Above-mentioned CABAC status control module is used for according to the code stream composition and the decoding order that stipulate in standard, and state of a control redirect, controls the renewal of corresponding context variable simultaneously and read, and completes corresponding CABAC decode operation;
Above-mentioned output module is for realizing the output control of the result to CABAC decoding.
The decoding process of described EG0 decoder module includes character type and without two kinds of character types, this resolver adopts the mode of solidifying look-up table in hardware to realize above-mentioned two kinds of decoding processes.In order to improve decoding efficiency, in the present invention, adopt the mode of solidifying look-up table in hardware to realize this two kinds of decoding processes.
Described code stream FIFO width is 8.Facilitate the use of CABAC module.
Code stream analyzing device of the present invention is divided (as shown in Figure 1) according to the syntactic element of HEVC standard regulation, again plan state machine can accomplish following some, thereby improve the throughput of data:
(1) total amount of minimizing bin: the syntactic element of HEVC standard regulation is divided, can avoid the modes such as information redundancy to reduce the total amount that needs bin to be processed by changing binarization mode, infer the value of some bin and more senior mark (flag) being set, thus covert raising data throughout;
(2) reduce the dependence that context is selected; Due to the data dependency in context selection course, the multiple bin(of iterative decoding refer to a binary system here) a large amount of predicted operation of needs.Reducing this type of dependence can simplify the process of context selection and reduce the needed predicted operation quantity of the multiple bins of parallel processing;
(3) reduce the dependence of resolving: CABAC parsing itself is exactly a bottleneck, therefore should reduce the dependence to other any video encoding module that may cause CABAC termination as far as possible.Certainly be ideally that process of analysis is completely independent with other process;
(4) reduce memory requirements: conventionally can increase path delay to the access of internal memory, therefore reduce memory access operation necessary, meanwhile, do like this and can also reduce cost, reduction power consumption.
Claims (4)
1. one kind is applicable to the code stream analyzing device of HEVC, it is characterized in that, this resolver comprises code stream analyzing status control module, EG0 decoder module, adjacent upper block message and relevant parameter memory cell, decoding output memory cell, code stream FIFO and CABAC decoder module; Described EG0 refers to 0 rank order index Columbus;
Described code stream FIFO is connected with EG0 decoder module with described CABAC decoder module respectively by buffer displacement, and described EG0 decoder module is connected with described CABAC decoder module by code stream analyzing status control module; Described EG0 decoder module is connected with described CABAC decoder module by adjacent upper block message and relevant parameter memory cell;
Described CABAC decoder module comprises CABAC arithmetic decoding, output module and the control of CABAC state; Described CABAC arithmetic decoding is connected with described decoding output memory cell by output module; Described ABAC arithmetic decoding is connected with the control of described CABAC state, and the control of described CABAC state is connected with described decoding output memory cell by output module;
Described buffer displacement is connected with described CABAC arithmetic decoding, and described adjacent upper block message and relevant parameter memory cell are connected with the control of described CABAC state;
Described code stream analyzing status control module is the control centre of whole code stream analyzing device, according to the code stream composition stipulating in HEVC standard and corresponding parsing order, described code stream analyzing status control module is coordinated the work of EG0 decoder module and CABAC decoder module, completes the decode operation of corresponding syntactic element;
Described EG0 decoder module has been used for the decode operation of the syntactic element that uses 0 rank orders index Columbus coding, specifically includes character type and without two kinds of character types;
Described adjacent upper block message and relevant parameter memory cell adopt SRAM to realize, for storing following information:
(1) adjacent upper piece syntax element value, the value of these syntactic elements is for calculating the model index delta of corresponding syntactic element: the relevant parameter that (2) need for CABAC decode procedure: comprise sequence parameter set, picture parameter set and head syntax element value;
Described decoding output memory cell, for storing residual matrix and the movable information of CABAC decoding output;
Described code stream FIFO for temporary transient memory code stream information, realizes the asynchronous access of code stream information simultaneously;
Described CABAC decoder module, for realizing the decode operation of the syntactic element that uses CABAC coding: comprise CABAC arithmetic decoding module, CABAC status control module and output module.
2. a kind of code stream analyzing device that is applicable to HEVC according to claim 1, is characterized in that, described CABAC arithmetic decoding module comprises arithmetic decoding and renormalization unit and context model administrative unit;
Above-mentioned arithmetic decoding and renormalization unit comprise regular decode logic, bypass decode logic and termination decode logic, and this unit is all realized by combinational logic; This unit selects corresponding decoding mode to decode by the decoding type stipulating in HEVC standard, upgrades current interval width, interval biasing and context variable simultaneously;
Above-mentioned context model administrative unit can complete the initialization of each context model or the initialization of synchronous and arithmetic decoding engine according to corresponding initialization flow process separately in the time resolving new slice, new tile and new a line CTU; Meanwhile, this unit can also be according to memory requirement, and the context variable of just corresponding CTU and slice segment is deposited in corresponding register;
Above-mentioned CABAC status control module is used for according to the code stream composition and the decoding order that stipulate in standard, and state of a control redirect, controls the renewal of corresponding context variable simultaneously and read, and completes corresponding CABAC decode operation;
Above-mentioned output module is for realizing the output control of the result to CABAC decoding.
3. a kind of code stream analyzing device that is applicable to HEVC according to claim 1, it is characterized in that, the decoding process of described EG0 decoder module includes character type and without two kinds of character types, this resolver adopts the mode of solidifying look-up table in hardware to realize above-mentioned two kinds of decoding processes.
4. a kind of code stream analyzing device that is applicable to HEVC according to claim 1, is characterized in that, described code stream FIFO width is 8.
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| CN105657421A (en) * | 2016-01-15 | 2016-06-08 | 珠海全志科技股份有限公司 | 8*8 residual coefficient block encoding method and system |
| CN104918048B (en) * | 2015-06-03 | 2018-04-03 | 复旦大学 | Suitable for the entropy code context probability modeling modeling module design method of HEVC standard |
| CN113038140A (en) * | 2019-12-24 | 2021-06-25 | 扬智电子科技(中国)有限公司 | Video decoding method and video decoding device |
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