CN101645723A - System and method for counteracting serial interference in time division synchronous code division multiple access technology - Google Patents

Abstract

The invention discloses a system and a method for counteracting serial interference in time division synchronous code division multiple access technology. The method comprises the following steps: processing an interference signal in an interference counteracting unit to obtain the signal data of the interference counteracting unit; aligning the signal data of the interference counteracting unit;performing addition and subtraction computations of the aligned signal data to obtain a clean signal; calling the former signal data of the interference counteracting unit by a serial interference counteracting and controlling module; starting the next interference counteracting unit to operate so obtain the signal data of the next interference counteracting unit; repeating the step of calling until the interference counteracting unit finishes processing the interference; displaying the accomplish of the interference counteracting unit; and generating an interrupt signal. The system and the method provided by the invention reduce the time domain serial interference of the system, provide a user with a cleaner signal, improve the quality of the received signal and improve the working efficiency of the overall system by the mode of aligning and accumulating the signal data of the interference counteracting unit after being performed with operations of channel estimation and signal reconstruction.

Description

The system and method for counteracting serial interference in a kind of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access)

Technical field

The present invention relates to the method and the device of Interference Cancellation in a kind of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), relate in particular to the method and the device of counteracting serial interference in a kind of time division synchronization code multiple access technology.

Background technology

TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) TD-SCDMA, 3G (Third Generation) Moblie standard (being called for short 3G) as China's proposition, from 1998 formally since the ITU of International Telecommunication Association submits to, gone through history for many years, expert group assessment, ITU approval and issue, the fusion of standard, a series of International standardization work such as introducing of new technology characteristic have been finished with third generation partnership projects system 3GPP, propose by China thereby make the TD-SCDMA standard become first, based on radio communication international standard Intellectual Property Right in China, that accepted extensively in the world and approve.This is a milestone important on China's telecommunication history.

The substance work of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) TD-SCDMA standard criterion is mainly finished under 3GPP.Datang is boundary operator, equipment manufacturers in other numerous industries, through session discussing, mails discussion many times, by a large amount of manuscripts of submitting to, the content of physical layer process, higher-layer protocols message, network and interface signaling message, radio-frequency (RF) index and the parts such as parameter, uniformity test of TD-SCDMA standard criterion has been carried out each revision and perfect, made that up to the present the TD-SCDMA standard has reached certain stable and maturity.

In 3G technology and system flourish when, no matter be each equipment manufacturers, operator, or each research institution, government, ITU, all begun the later technological development direction of 3G is launched research.In several technological development direction that ITU assert, intelligent antenna technology and time division duplex technology have been comprised, think these two kinds of technology all be after the trend of technical development, and these two technology of smart antenna and time division duplex, in present TD-SCDMA standards system, good embodiment and application have been obtained, from this point, can see that also the TD-SCDMA standard techniques has suitable development prospect.

In addition, the TD-SCDMA standard has also been introduced new technical characteristic to some extent, performance in order to further raising system, wherein mainly comprise: by air interface realize between the base station synchronously, as another alternative scheme of base station synchronization, be particularly useful in emergency circumstances assurance for the communication network reliability; The terminal positioning function can be passed through smart antenna, utilizes the signal angle of arrival that terminal user position is located, so that location-based service is provided better; High speed downlink packet inserts, and adopts and mixes re-transmission, Adaptive Modulation and Coding automatically, realizes the support of two-forty downlink grouping traffic; Many antennas input and output technology (MIMO) adopts base station and terminal multi-antenna technology and signal processing, improves wireless system performance; Up enhancement techniques adopts adaptive modulation and coding, to the mechanism that the quick distribution of special use or shared resource and corresponding physical layer and high-level signaling are supported, strengthens up channel and professional ability.

TD-SCDMA, in real use, have many good qualities, as: availability of frequency spectrum height, to power control require low, adopted smart antenna and joint test to introduce so-called aerial classification, avoided cell breath, different business is less to the size influence of overlay area, is easy to network planning or the like.Simultaneously, it also exists technological deficiency, as: require synchronously highly, in use, exist signal interference problem, up-downgoing, this sub-district, adjacent sub-district all might exist signal in various degree to disturb.

Therefore, prior art awaits further to improve and development.

Summary of the invention

The objective of the invention is to technological deficiency at above-mentioned prior art existence, proposing a kind of signal with serial interference eliminates, obtain the cell signal of relative clean, thus the system and method for counteracting serial interference in the TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) of the time domain serial interference of minimizing system.

Technical scheme of the present invention is as follows:

The system of counteracting serial interference is characterized in that in a kind of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), and described system comprises: counteracting serial interference control module, downlink synchronous pilot frequency sign indicating number read-only memory module, Interference Cancellation unit module; Described counteracting serial interference control module is connected with described downlink synchronous pilot frequency sign indicating number read-only memory module, described Interference Cancellation unit module respectively;

Described counteracting serial interference control module is used for calling the enabling signal of Interference Cancellation unit, and provides the input parameter of Interference Cancellation unit;

Described downlink synchronous pilot frequency sign indicating number read-only memory module is used to read the downlink synchronous pilot frequency sign indicating number;

Described Interference Cancellation unit module is used to offset the interference signal of sub-district.

Described system, wherein, described Interference Cancellation unit module also comprises: an Interference Cancellation unit controls module, a channel estimation module, a signal reconstruction module and an accumulator module, described Interference Cancellation unit controls module respectively with described channel estimation module, signal reconstruction module, and accumulator module is connected;

Described Interference Cancellation unit controls module is used to provide the enabling signal of channel estimating, signal reconstruction, accumulator module and the input parameter of each module;

Described channel estimation module is used for estimating by the computing of downlink synchronous pilot frequency sign indicating number power and associated window being carried out cell channel;

Described signal reconstruction module is used for channel estimation window and downlink synchronous pilot frequency sign indicating number are carried out convolution algorithm;

Described accumulator module is used for the Interference Cancellation unit sequence of complex numbers accumulating operation that aligns.

Described system, wherein, described accumulator module also is used for Interference Cancellation unit sequence of complex numbers alignd and subtracts computing.

Described system, wherein, described counteracting serial interference system is divided into the secondary serial structure, and each level comprises some Interference Cancellations unit.

The method of counteracting serial interference in a kind of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), it comprises the steps:

A, the interference signal in the Interference Cancellation unit module is carried out data processing, obtain this Interference Cancellation cell signal data;

B, with described Interference Cancellation cell signal alignment of data, carry out plus and minus calculation, draw the relative clean signal;

C, described counteracting serial interference control module are called last Interference Cancellation cell signal data, and start next Interference Cancellation unit operations, obtain next Interference Cancellation cell signal data;

D, repeat above-mentioned steps C, dispose, show that then the Interference Cancellation unit finishes signal, and produce interrupt signal up to all Interference Cancellation blocking interferers.

Described method, wherein, described steps A may further comprise the steps:

A1, interference signal in the described Interference Cancellation unit is carried out channel estimation process:

A2, interference signal in the described Interference Cancellation unit is carried out signal reconstruction handle.

Described method, wherein, described steps A 1 may further comprise the steps:

A11, interference signal in the described Interference Cancellation unit carried out successively sync correlation computing, relevant control, power calculation, thresholding are calculated, the active path search is handled, obtain channel estimation value.

Described method, wherein, described steps A 2 may further comprise the steps:

A21, employing flowing water ring structure carry out convolution algorithm with the downlink synchronous pilot frequency sign indicating number and the described channel estimation value of described Interference Cancellation unit.

Described method, wherein, the plus-minus among the described step B by formula: d _Out=d _In+ s _In-s _OutCarry out computing; Wherein:

d _OutBe the signal behind the current Interference Cancellation unit Interference Cancellation;

d _InBe the signal behind the last Interference Cancellation unit Interference Cancellation;

s _InSignal for last Interference Cancellation unit reconstruct respective cell;

s _OutSignal for current Interference Cancellation unit reconstruct current area;

When the Interference Cancellation unit is the first Interference Cancellation unit, s _InBe set to 0.

Described method, wherein, calling by formula among the described step C: $\mathrm{ICU}\_i\_\mathrm{start}=\left\{\begin{array}{cc}\mathrm{SIC}\_\mathrm{start}& i=1\\ \mathrm{ICU}\_i-1\_\mathrm{over}& \mathrm{else}\end{array}\right.$ Carry out computing, draw a series of each Interference Cancellation cell parameters:

When i＜=4, then icu_sync_id=sync_id_i, icu_thsig=sic_thsig1, souti_cs=i;

When i＞4, icu_sync_id=sync_id_i-4 then, icu_thsig=sic_thsig2, then souti_cs=i-4;

icu_thnoise＝sic_thnoise；

Wherein: described equation expression implication is:

When i=1, ICU_i_start=SIC_start then;

When i＞1, ICU_i_start=ICU_i-1_over then;

Described ICU_i_start is an i Interference Cancellation unit initial signal data value;

Described SIC_start is a counteracting serial interference initial signal data value;

Described ICU_i-1_over is an i-1 Interference Cancellation unit end signal data value;

Described icu_sync_id is Interference Cancellation units synchronization sign indicating number address;

Described sync_id_i is that sequence number is the Interference Cancellation units synchronization sign indicating number address of i;

Described sync_id_i-4 is that sequence number is the Interference Cancellation units synchronization sign indicating number address of i-4;

Described icu_thsig is an Interference Cancellation cell signal threshold value;

Described sic_thsig1 is an one-level counteracting serial interference signal threshold value;

Described sic_thsig2 is a secondary counteracting serial interference signal threshold value;

Described icu_thnoise is an Interference Cancellation unit Noise Gate value;

Described sic_thnoise is a counteracting serial interference Noise Gate value;

Described souti_cs is the Interference Cancellation unit number.

The system and method for counteracting serial interference in a kind of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) provided by the present invention, owing to adopted the Interference Cancellation cell signal alignment of data after handling through channel estimating, signal reconstruction, carry out accumulating operation, draw the mode of relative clean signal, reduced the time domain serial interference of system, offer the cleaner signal of user, improved the quality of received signal, thereby improve whole system operation efficient.

Description of drawings

Fig. 1 is the secondary counteracting serial interference structure chart of this sub-district of the present invention and adjacent sub-district;

Fig. 2 is Interference Cancellation of the present invention unit cellular construction figure;

Fig. 3 is counteracting serial interference modular structure figure of the present invention;

Fig. 4 is a convolution algorithm flowing water loops composition of the present invention;

Fig. 5 is an Interference Cancellation schematic diagram of the present invention;

Fig. 6 is i of the present invention and i+1 Interference Cancellation cellular construction figure;

Fig. 7 is an adjusted Interference Cancellation cellular construction schematic diagram of the present invention;

Fig. 8 is an ICU_i control flow chart of the present invention;

Fig. 9 is an Interference Cancellation cell channel estimation module structure chart of the present invention;

Figure 10 is the correlator unit structure chart of 16 stage pipeline structure of the present invention;

Figure 11 is correlation computations of the present invention and control timing figure;

Figure 12 is channel estimating power calculation fixed point figure of the present invention;

Figure 13 is that Interference Cancellation cell channel of the present invention is estimated reprocessing thresholding computing module structure chart;

Figure 14 is that channel estimating threshold value of the present invention is calculated sequential chart;

Figure 15 is that channel estimating reprocessing thresholding of the present invention calculates fixed point figure.

Embodiment

Below in conjunction with accompanying drawing each preferred embodiment of the present invention is made a more detailed description.

Core inventive point of the present invention is that the Interference Cancellation cell signal alignment of data after will handling through channel estimating, signal reconstruction carries out accumulating operation, thereby draws the relative clean signal.

Counteracting serial interference know-why of the present invention realizes by the mode of secondary serial iteration, adopts the method for eliminating phase mutual interference between each sub-district step by step, obtains the signal of each sub-district relative clean.Wherein, each counteracting serial interference stage (Stage) comprises four Interference Cancellation unit, each Interference Cancellation unit is handled at a sub-district, each Interference Cancellation unit mainly comprises: channel estimating (being correlated with), signal reconstruction and relevant processing sections such as signal plus-minus, present embodiment is supported 4 sub-districts, i.e. three adjacent sub-districts, this sub-district, as shown in Figure 1.Wherein, each Interference Cancellation unit is handled at a sub-district, as shown in Figure 2 at every turn.Input d _InBe the output signal (initial value is exactly the primary signal that receives) behind the last Interference Cancellation unit Interference Cancellation, that is to say that the signal of having removed each sub-district, front is to the influence when the pre-treatment sub-district, s _InIt is the signal of front one Interference Cancellation unit reconstruct respective cell; d _OutBe the output signal behind the current Interference Cancellation unit Interference Cancellation, s _OutIt is the signal when the pre-treatment sub-district of current Interference Cancellation unit reconstruct.When first order counteracting serial interference begins to handle, each s _InInitial value is set to 0.

Counteracting serial interference module of the present invention comprises: counteracting serial interference control module, downlink synchronous pilot frequency sign indicating number read-only memory module and Interference Cancellation unit module, as shown in Figure 3.

Described counteracting serial interference control module is the secondary serial structure, calls 8 Interference Cancellation unit altogether, by a cover Interference Cancellation unit serial method of calling is realized.Described counteracting serial interference control module, the enabling signal of Interference Cancellation unit is called in control at every turn, and provide the input parameter of Interference Cancellation unit, as current Interference Cancellation unit number i (i=1～8), downlink synchronous pilot frequency sign indicating number address, threshold value parameter or the like.

Described downlink synchronous pilot frequency sign indicating number read-only memory module, its size is 32*64bit, reads a downlink synchronous pilot frequency sign indicating number at every turn, its length is 64bit, be entered into the signal reconstruction module after reading, also it write simultaneously among the sync_buf in the Interference Cancellation unit, be used for channel estimation calculation.

Each Interference Cancellation unit comprises again: Interference Cancellation unit controls module, channel estimation module, signal reconstruction module, and accumulator module.

Described Interference Cancellation unit controls module is used to provide the enabling signal of channel estimating, signal reconstruction, accumulator module, and the parameter of each module input;

Described channel estimation module is calculated the associated window of downlink synchronous pilot frequency sign indicating number power and 144chip length and is carried out related operation by the downlink synchronous pilot frequency yardage, obtain the current area channel estimation value.Carry out the channel estimating reprocessing again, obtain the position that channel estimation window and efficient channel are estimated;

Described signal reconstruction module is carried out convolution algorithm with channel estimation window and downlink synchronous pilot frequency sign indicating number, obtains through the cell signal behind the counteracting serial interference, and its length is 79chip.

Described alignment adds accumulator module, two sequence of complex numbers in the Interference Cancellation unit is alignd add up, and length is respectively 144 and 79.Need provide the positional information of corresponding 144 point sequences of first data of 79 point sequences during calculating, begin from here 79 continuous corresponding additions of plural number.The operation that also has alignment to subtract in the Interference Cancellation unit, the 79 point sequence supplement sign indicating numbers that need will be subtracted are earlier done alignment again and are added computing.

To in the Interference Cancellation unit module, work of treatment flow processs such as channel estimating, signal reconstruction and Interference Cancellation are described in detail below:

1, channel estimating flow process

If r ₀(s k) is the IQ data segment of the original 144 sampling point single-time samplings of sync section of reception, k=0～L _Tim* 2+80-1, i.e. k=0～143, s is a subframe index number, the channel estimation value h of sub-district n (calculating i) is based on the related operation of downlink synchronous pilot frequency sign indicating number for s, n, and its operational formula is as follows:

$h(s,n,i)=\underset{l=0}{\overset{63}{\mathrm{\Σ}}}{r}_0(s,i+l)*\mathrm{conj}(\mathrm{sync}(n,l)\×j^l)---\left(1\right)$

Wherein, each meaning of parameters is as follows:

r ₀(s, i+l): be the downlink synchronous pilot frequency coded signal of the subframe s that receives, the data of input downlink synchronization tracking module are the 8bit signed integers, totally 144 points;

Sync (n, l): be the downlink synchronous pilot frequency sign indicating number of sub-district n, the plural number of 1bit;

(i): be the performance number DP value of each channel estimating, fixed point turns to the 14bit plural number to h for s, n.

N: be cell index number, n=0～N (number of cells of monitoring is 3 at present to the maximum)

I: be channel estimation value h (s, n, i) call number, the i=0～(L of each sub-district _Tim* 2+16)-1, i.e. i=0～79;

L _Tim: be the chip number before the down-going synchronous, the current 32chips that is made as.

Calculate by above-mentioned formula, draw channel estimation value, remove The noise, also need carry out the channel estimating reprocessing,, put 0 less than the channel estimation value of thresholding with channel estimation value result's energy and threshold value comparison, as follows:

When: | h (s, n, i) | ²＜Th_local-----------(2);

Then: h (s, n, i)=0----------------(3);

Wherein, Th_local is a threshold value.

The computational methods of a, threshold T h_local are as follows:

Select effective multi-path threshold value to calculate based on following two standards:

1. based on the maximum multipath power calculation

DP _max＝max(|h(s，n，k)| ²)-------------(4)

Wherein, DPmax is the maximum of channel estimating energy;

${\mathrm{Th}}_{\mathrm{Signal}}={\mathrm{DP}}_{\max }*{10}^{(T_{\max }/10)}---\left(5\right)$

Wherein, at first order counteracting serial interference, preceding 4 Interference Cancellation unit of Fig. 1 just: Interference Cancellation unit 1, Interference Cancellation unit 2, Interference Cancellation unit 3 and Interference Cancellation unit 4, threshold-offset T _Max=-3dB is in 4 Interference Cancellation unit of second level counteracting serial interference: Interference Cancellation unit 5, Interference Cancellation unit 6, Interference Cancellation unit 7 and Interference Cancellation unit 8, threshold-offset T _Max=-6dB, this T _MaxBe worth configurable, thresholding Use the 10bit fixed point.

2. calculate based on noise energy

Calculating noise footpath noiseDP average,

$\mathrm{Noise}=\frac{1}{P}\underset{p=1}{\overset{P}{\mathrm{\Σ}}}\mathrm{noise}{\mathrm{DP}}_p---\left(6\right)$

Wherein, P (P=1,2 ...) expression | h (s, n, k) | ²In the noise path number.NoiseDP is a noise path, i.e. all except that effective diameter footpath, and described noise path is that the thresholding according to a last subframe calculates, current subframe the inside, all then all are noises less than the previous frame threshold value.

${\mathrm{Th}}_{\mathrm{noise}}=\mathrm{Noise}*{10}^{(T_{\mathrm{Noise}}/10)}---\left(7\right)$

Wherein, T _Noise=6dB is a noise offset, and this value is configurable, thresholding Use the 10bit fixed point.

Comprehensive above-mentioned two basises of calculation, the bigger last channel estimating reprocessing threshold value of a conduct in two threshold values selecting to calculate out, as described below;

Th_local＝max(Th _noise，Th _Signal)-------------(8)

The channel estimating reprocessing threshold value of each sub-district is calculated according to the channel estimation value of each sub-district respectively.

It should be noted that when starting the downlink synchronization tracking module for the first time because there is not the threshold value of a last subframe, so can not determine noise, at this moment, threshold value is only got according to maximum, that is:

Th_local＝Th _Signal---------------(9)

Last 4 footpaths choosing at most above thresholding except that article one footpath, are got maximum 3 according to the amplitude size in addition, and the distance in these three footpaths and article one footpath should be within 16chip, because channel estimation window has only 16chip.This numerical value is a configurable parameter.

2, signal reconstruction flow process

An important innovations of the present invention is that described signal reconstruction module adopts the flowing water ring structure that the downlink synchronous pilot frequency sign indicating number and the channel estimation value of this locality are carried out convolution algorithm, as shown in Figure 4, obtains reconstruction signal s _Out, its convolution algorithm formula is as follows:

$s_{\mathrm{out}}=\mathrm{sync}\left(n\right)\⊗h(s,n)---\left(10\right)$

Wherein,

The expression convolution algorithm, sync (n) is the ID sign indicating number of n sub-district, (s n) is s subframe to h, the channel estimation value of n cell downlink synchronizing pilot sign indicating number part.

For representing conveniently, with the address code sync (n) of n sub-district of 64 vector x (i) expression, 16 vectorial h (i), wherein, (M=1,2,3 are arranged at most in 16,4 nonzero values, other values all are 0) the expression channel estimating, launch formula (10) to such an extent that formula (11) is as described below:

$s_{\mathrm{out}}\left(i\right)=\underset{m=0}{\overset{15}{\mathrm{\Σ}}}h\left(m\right)*x(i-m)---\left(11\right)$

s _OutLength be 79.

The channel estimation sequence h that L is ordered (n) imports in the data broadcasting mode, and SYNC_DL sign indicating number sequence adopts L level flowing water ring structure, walks abreast and is written into cyclic shift.Be that L level register is written into L SYNC_DL sequence of points simultaneously, circulation is moved then.The multiply-accumulate unit of every grade of correspondence calculates the h (n) of position at the corresponding levels and the product and the accumulation result of SYNC_DL sequence of points simultaneously.Result points of each clock calculation, the every wheel obtains L point result.Calculated one take turns after, the parallel L point that is written into next round of SYNC_DL sequence, the operation above repeating.The benefit of cyclic shift is: each takes turns each multiply-accumulate arithmetic element is successively to finish the computing of a responsible result points of epicycle oneself.Finish the result that the unit of calculating falls to add up clearly earlier, the result points that next round is responsible for is carried out part and is calculated in advance, has saved the time that empty grade or flowing water inject.(0＜i≤L) level flowing water computing unit can calculate the accumulation result of L-i product of next round to i before epicycle.

Interference Cancellation flow process of the present invention, when carrying out interference-cancellation process, signal data need subtract each other, and at this time needs the signal data alignment is subtracted each other again, and original channel estimation value is 80, and except surpassing maximum 4 footpaths of thresholding, other all are 0.First channel estimation value sequence number of supposing thresholding is ii (ii=1～80), and alignment thereof as shown in Figure 5.

Each Interference Cancellation sequence of unit is by formula: d _Out=d _In+ s _In-s _OutCalculate the result, all finish, obtain the signal of relative clean up to two-stage counteracting serial interference counteracting serial interference.

Interference Cancellation of the present invention unit serial is called 8 times, provides the enabling signal and the current Interference Cancellation unit number i of Interference Cancellation unit when calling, i=1～8 at every turn.The Interference Cancellation unit provides end signal after calculating and finishing, and starts next Interference Cancellation unit operations.It is as follows to call formula:

$\mathrm{ICU}\_i\_\mathrm{start}=\left\{\begin{array}{cc}\mathrm{SIC}\_\mathrm{start}& i=1\\ \mathrm{ICU}\_i-1\_\mathrm{over}& \mathrm{else}\end{array}\right.---\left(12\right)$

And, obtain following Interference Cancellation cell parameters according to Interference Cancellation unit number i:

Down-going synchronous address number sync_id, if i＜=4, icu_sync_id=sync_id_i; Otherwise icu_sync_id=sync_id_i-4;

Signal threshold value icu_thsig, if i＜=4, icu_thsig=sic_thsig1; Otherwise icu_thsig=sic_thsig2;

Noise Gate value icu_thnoise, icu_thnoise=sic_thnoise;

The RAM_Sout sheet selects souti_cs, if i＜=4, souti_cs=i; Otherwise souti_cs=i-4.

Wherein, described ICU_i_start is an i Interference Cancellation unit initial signal data value;

Described SIC_start is a counteracting serial interference initial signal data value;

Described ICU_i-1_over is an i-1 Interference Cancellation unit end signal data value;

Described icu_sync_id is Interference Cancellation units synchronization sign indicating number address;

Described sync_id_i is that sequence number is the Interference Cancellation units synchronization sign indicating number address of i;

Described sync_id_i-4 is that sequence number is the Interference Cancellation units synchronization sign indicating number address of i-4;

Described icu_thsig is an Interference Cancellation cell signal threshold value;

Described sic_thsig1 is an one-level counteracting serial interference signal threshold value;

Described sic_thsig2 is a secondary counteracting serial interference signal threshold value;

Described icu_thnoise is an Interference Cancellation unit Noise Gate value;

Described sic_thnoise is a counteracting serial interference Noise Gate value;

Described souti_cs is the Interference Cancellation unit number.

When producing Interference Cancellation unit end signal icu_8_over, then whole counteracting serial interference counteracting serial interference calculates and finishes, and produces interrupt signal int_sic.

Counteracting serial interference of the present invention adopts the mode of secondary iteration, and wherein each level comprises several Interference Cancellation unit again, and each Interference Cancellation unit is handled at a sub-district, and present embodiment is supported 4 sub-districts.Fig. 2 is launched, and is that example makes a more detailed description with i and i+1 Interference Cancellation unit, and it as shown in Figure 6.

There are 2 signal input value: d each Interference Cancellation unit _InAnd s _In, it is respectively

$d_{\mathrm{in}}\_i=\left\{\begin{array}{cc}{r}_k& i=1\\ d_{\mathrm{out}}\_i-1& \mathrm{else}\end{array}\right.---\left(13\right)$

$s_{\mathrm{in}}\_i=\left\{\begin{array}{cc}0& i=<4\\ s_{\mathrm{out}}\_i-4& \mathrm{else}\end{array}\right.---\left(14\right)$

First Interference Cancellation unit input d _InAnd s _InBe respectively r _kWith 0, realize for ease of hardware, two Interference Cancellation unit of Fig. 6 are taken apart, redefine the structure of Interference Cancellation unit, as shown in Figure 7.

Two parts before and after adjusted i Interference Cancellation unit (ICU_i) is divided into: Channel Processing (ICU_chproc_i) adds (ICU_add_i) with aliging, i=1～8, and concrete steps are as follows:

S1, from RAM_dio reading of data as the input s _Local_ i carries out channel estimating and signal reconstruction and handles, and obtains s _Out_ i writes among the RAM_souti;

S2, calculating d _Out_ i, d _Out_ i=s _Local_ i-s _Out_ i writes the result among the RAM_dio;

S3, calculating s _Local_ i+1, s _Local_ i+1=d _In_ i+1+s _In_ i+1=d _Out_ i+s _In_ i+1 still writes the result among the RAM_dio.

Wherein, step S1 is the Channel Processing part, handles constant when calling at every turn; Step S2 and S3 are the parts that adds up of aliging.

When i=＜4, when promptly the Interference Cancellation unit is in one-level stage stage1, s _InBe 0, s _Local_ i+1=d _Out_ i omits step S3;

When i=8, then counteracting serial interference calculates and finishes, and omits step 3, directly exports d _Out_ 8.

The control flow of i Interference Cancellation unit, as shown in Figure 8.

Channel estimation module of the present invention comprises again: sync correlation module, channel estimating reprocessing two modules, as shown in Figure 9, below to described sync correlation module, and the functional sequence of channel estimating post-processing module makes a more detailed description.

1, sync correlation module

1., sync correlation computing

r ₀(s k) is the IQ data segment of the original 144 sampling point single-time samplings of sync section of reception, k=0～L _Tim* 2+80-1, i.e. k=0～143, s is a subframe index number, the channel estimation value h of sub-district n (calculating i) is based on the related operation of downlink synchronous pilot frequency sign indicating number for s, n, and method is as follows:

$h(s,n,i)=\underset{l=0}{\overset{63}{\mathrm{\&Sigma;}}}{r}_0(s,i+l)*\mathrm{conj}(\mathrm{sync}(n,l)\&times;j^l)---\left(15\right)$

Wherein, r ₀(s, i+l): the downlink synchronous pilot frequency coded signal of the subframe s of reception, the data of input downlink synchronization tracking module are the 8bit signed integers, totally 144 points;

Sync (n, l): the downlink synchronous pilot frequency sign indicating number of sub-district n, the plural number of 1bit;

(i): each DP value, fixed point turns to the 14bit plural number to h for s, n.

N: cell index number, n=0～N (number of cells of monitoring is 3 at present to the maximum)

I: the channel estimation value h of each sub-district (s, n, i) call number, i=0～(L _Tim* 2+16)-1, i.e. i=0～79;

L _Tim: the chip number before the downlink synchronous pilot frequency sign indicating number, the current 32chips that is made as.

2., correlation unit

If r is the IQ data segment of the original W sampling point of downlink synchronous pilot frequency sign indicating number part of reception, W is the slip correlation window length; N is the address number of downlink synchronous pilot frequency sign indicating number, n=0～31; The slip correlated results of downlink synchronous pilot frequency sign indicating number is a sequence of complex numbers, be expressed as CorrSync (n, k), k=0～W-64, computing formula is as follows

$\mathrm{CorrSync}(n,k)=\underset{l=0}{\overset{63}{\mathrm{\&Sigma;}}}r(k+l)*\mathrm{conj}(\mathrm{sync}(n,l)\&times;j^l)---\left(16\right)$

The slip correlated results that obtains is the sequence of complex numbers of W-64+1=W-63 point.Formula 16 is launched, and the input sampling is designated as r (0), r (1), and r (2), r (3) ... ..r (W-1), each sampling all comprises i and q, and the bit wide of 16 bits is deposited i and q in the same field; If the downlink synchronous pilot frequency sign indicating number address number of current calculating is n, downlink synchronous pilot frequency sign indicating number code word is designated as s (0), s (1) ... s (63).Then correlation computations can be decomposed into following calculating.

CorrSync(0)＝r(0)*s(0)+r(1)*s(1)+r(2)*s(2)+......+r(62)*s(62)+r(63)*s(63)--------------(17)

CorrSync(1)＝r(1)*s(0)+r(2)*s(1)+r(3)*s(2)+......+r(63)*s(62)+r(64)*s(63)--------------(18)

CorrSync(2)＝r(2)*s(0)+r(3)*s(1)+r(4)*s(2)+......+r(64)*s(62)+r(65)*s(63)--------------(19)

...

CorrSync(7)＝r(7)*s(0)+r(8)*s(1)+r(9)*s(2)+......+r(69)*s(62)+r(70)*s(63)--------------(20)

...

CorrSync(W-63)＝r(W-63)*s(0)+r(W-62)*s(1)+r(W-61)*s(2)+......+r(W-2)*s(62)+r(W-1)*s(63)--------------(21)

W gets 144 in this module of present embodiment, and the correlated results that then slides is the sequence of complex numbers of 81 points, for ease of calculating, last 1 point is removed, and changes 80 sequence of complex numbers into.

For accelerating arithmetic speed, correlation unit generally adopts 16 level production line workflows, as shown in figure 10.

Point multiplication operation rule wherein is as follows:

If s _l=conj (sync (n, l) * j ^l), because sync (n l) is 1bit,

If sync (n, l)=0, s then _l=0;

(n l)=1, then has as if sync

$s_l=\left\{\begin{array}{cc}1& \mathrm{<figure-callout\; id="4"\; label="l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">l</figure-callout>}\%4=0\\ -\mathrm{<figure-callout\; id="4"\; label="j\; l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">j</figure-callout>}& l\%4=1\\ -1& \mathrm{<figure-callout\; id="4"\; label="l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">l</figure-callout>}\%4=2\\ \mathrm{<figure-callout\; id="4"\; label="j\; l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">j</figure-callout>}& l\%4=3\end{array}\right.---\left(22\right)$

Then $r_k*s_l=\left\{\begin{array}{cc}r\_i+r\_q*\mathrm{<figure-callout\; id="4"\; label="j\; l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">j</figure-callout>}& l\%4=0\\ r\_q-r\_i*\mathrm{<figure-callout\; id="4"\; label="j\; l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">j</figure-callout>}& l\%4=1\\ -r\_i-r\_q*\mathrm{<figure-callout\; id="4"\; label="j\; l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">j</figure-callout>}& l\%4=2\\ -r\_q+r\_i*\mathrm{<figure-callout\; id="4"\; label="j\; l\; \%"\; filenames="A2008101427880026H3.png,A2008101427880029H2.png"\; state="\{\{state\}\}">j</figure-callout>}& l\%4=3\end{array}\right.---\left(23\right)$

Therefore to the downlink synchronous pilot frequency sign indicating number code word of input, only need to judge the low 2bit of its code word sequence number.

Related operation reality has only been carried out the accumulating operation of 64 data as can be seen from the dot product formula, the reception data i/q bit wide of input is 8bit, the output correlated results is 14bit, correlation unit is shared 16*2=32 integrating instrument and 32 registers, and bit wide is 14bit.

Correlation unit calculates the result that once can obtain 16 reference points, needs 64+16-1=79 of input continuously to receive data and 64 downlink synchronous pilot frequency sign indicating numbers, and calculating required time is 64+16=80 clock.

3., relevant control

Among the present invention, finish controlled function to the repetitive operation in related operation of a correlation unit.It is 80/16=5 time that the slip correlation computations of the associated window of a 144chip needs the number of times of correlation unit repetitive operation, and required time is a 80*5=400 clock.

64 each computings of data of downlink synchronous pilot frequency sign indicating number are imported successively, provide corresponding downlink synchronous pilot frequency sign indicating number address number when reading at every turn; For receiving data division, establishing current operation times is i, and i=0～4, then the synchronization caching RAM of the i time computing correspondence: initial address is i*16, and from then on the position is risen and read 79 data continuously.Counter corr_unit_cnt[3:0 is set], 3bit, from 0 to 4, when counter when 4 turn back to 0, provide relevant end signal corr_over.

The address number of reading sheet choosing and downlink synchronous pilot frequency sign indicating number downlink synchronous pilot frequency sign indicating number read-only memory of synchronization caching random access memory is provided by Interference Cancellation unit controls module, and sync correlation calculating and control timing are as shown in figure 11.

2, channel estimating reprocessing

Channel estimating reprocessing part of the present invention, 80 the sequence of complex numbers DP that obtain that at first will be correlated with write RAM_dp, calculate every some performance number simultaneously respectively, result calculated is write among the RAM_dppow, and do thresholding simultaneously and calculate, obtain from RAM_dppow, reading the each point performance number after the threshold value, make comparisons with thresholding respectively, obtain the positional information of active path, and find channel estimation window, from the channel estimation window of RAM_dp, the active path corresponding channel estimation value is taken out successively at last, write in the RAM_dpwin correspondence position.Wherein 3 block RAM sizes are respectively: RAM_dp is 80*2*14bit (I/Q), and RAM_dppow is 80*26bit, and RAM_dpwin is 16*2*14bit (I/Q).

This part is divided into 3 modules, is respectively that power calculation, thresholding are calculated and the active path search, below 3 functions of modules is done more detailed description.

(1) power calculation

The rating formula of present embodiment is:

pow＝|h(s，n，i)| ²＝(Re(s，n，i)) ²+(Im(s，n，i)) ²--------------(24)

Fixed point as shown in figure 12, wherein, U represents unsigned number, down with.

(2), thresholding calculates

The thresholding of present embodiment calculates, and needs to calculate two threshold values and is respectively: Th _SignalAnd Th _Noise, get the two maximum as threshold value, and output current power maximum, as shown in figure 13.

1. Th _SignalCalculate

DP _max＝max(|h(s，n，k)| ²)-----------(25)

Wherein, DPmax is the maximum of channel estimating power;

${\mathrm{Th}}_{\mathrm{Signal}}={\mathrm{DP}}_{\max }*{10}^{(T_{\max }/10)}---\left(26\right)$

Configurable.

It is the maximum power value register that DPmax is set, to each performance number all order make comparisons with the numerical value in the maximum value register, if greater than then this performance number being write in the register, if constant less than the numerical value in the register then.

2. Th _NoiseCalculate

This computational process is divided into three steps, at first look for noise path, each performance number and a last subframe threshold value are compared, if then think noise path less than threshold value, noise path counter p is set, judge that current footpath is p+1 after the noise path, simultaneously the noise path performance number added up, obtain after current subframe is calculated and finished that noise path is counted P (1～80) and noise path adds up and

The inverse of next calculating noise footpath number P; Ask the mean deviation of current subframe noise path finally to calculate Th once more _Noise, formula is

${\mathrm{Th}}_{\mathrm{noise}}={10}^{(T_{\mathrm{noise}}/10)}*\frac{1}{P}*\underset{p=1}{\overset{P}{\mathrm{\&Sigma;}}}\mathrm{noise}{\mathrm{DP}}_p---\left(27\right)$

Ask the inverse of P, adopt look-up table, the scope of P is 1～80 in the present embodiment.

The sequential that threshold value is calculated as shown in figure 14, the fixed point that threshold value is calculated is as shown in figure 15.

(3), active path search

Effective diameter is used for searching for the channel estimation window of 16 points among the present invention, and marks the wherein position of effective diameter, uses dpvalid_flag[15:0] represent.

Before starting, active path search needs to compare earlier maximum and the threshold value that previous step obtains.

Do not have effective diameter if maximum, illustrates the current subframe of current area less than threshold value, then do not start the effective diameter search module, the channel estimation window that obtains is 0 all, and invalid flag nonevalid_flag puts 1;

If maximum more than or equal to threshold value, illustrates that the current subframe of current area has an effective diameter at least, start the effective diameter search module, its search step is as follows:

L1, read the each point performance number successively, make comparisons, find first point, remember that its positional information is first_pos[6:0] greater than threshold value with threshold value from RAM_dppow;

L2,15 data after the first_pos are made comparisons with threshold value, the each point comparative result marks with dpvalid_flag, adds first point totally 16 points, so dpvalid_flag is 16bit, and each bit is point of correspondence in order;

If n point performance number is greater than thresholding, dpvalid_flag[n then] put 1;

Otherwise, put 0, n=0～15, wherein dpvalid_flag[0] constant be 1;

After L3,16 points relatively finish with dpvalid_flag[15:0] addition without carry, obtain total num_valid[3:0 greater than the footpath of threshold value];

If num_valid[3:0] greater than maximum diameter string row Interference Cancellation _ maxpath_num[3:0], then will be greater than the each point power ordering of threshold value, Zui Da counteracting serial interference _ maxpath_num[3:0 wherein] individual footpath is the effective diameter of channel estimating, with all the other dpvalid_flag positions clear 0 greater than the footpath of threshold value;

If num_valid[3:0] less than counteracting serial interference _ maxpath_num[3:0], think that then all footpaths greater than threshold value all are effective diameter.Maximum diameter string row Interference Cancellation _ maxpath_num[3:0] by the DSP configuration, scope is 1～16.

Select by above 3 step active paths, obtain first position first_pos[6:0 of channel estimation window] and window in the interior position dpvalid_flag[15:0 of window of effective diameter].According to first_pos[6:0] in RAM_dp, find channel estimation window, i.e. first_pos[6:0] afterwards 16 points (comprising first point), these 16 points are write RAM_dpwin.

Signal reconstruction of the present invention adopts local downlink synchronous pilot frequency sign indicating number and channel estimation value convolution to obtain:

$s_{\mathrm{out}}=\mathrm{sync}\left(n\right)\&CircleTimes;h(s,n)---\left(28\right)$

Wherein,

The expression convolution algorithm, sync (n) is the ID sign indicating number of n sub-district, h (s, n) be s subframe, the channel estimation window of n cell downlink synchronizing pilot sign indicating number part, totally 16 points, the individual effective diameter of counteracting serial interference _ maxpath_num (3:0) is wherein arranged at most, in addition footpath all is 0, effective diameter dpvalid_flag[15:0] expression, " 1 " is effective diameter.

Formula (28) is launched, then obtains:

$s_{\mathrm{out}}\left(i\right)=\underset{m=0}{\overset{15}{\mathrm{\&Sigma;}}}h\left(m\right)*s(i-m)--\left(29\right)$

$=h\left(0\right)*s\left(i\right)+h\left(1\right)*s(i-1)+h\left(2\right)*s(i-2)+...+h\left(15\right)*s(i-15)$

Sout length is 64+16-1=79, i.e. i=0～78, and every needs at most to calculate to add up for 16 times, adds up at every turn and at first will carry out the judgement of two conditions, and establishing current cumulative number is h (m) * s (i-m):

1., dpvalid_flag[m] whether be 0, if 0 m point is not an effective diameter, this is 0;

2., whether i-m in [0,63] scope, if exceeded this scope, illustrate the downlink synchronous pilot frequency sign indicating number that does not have correspondence, this is 0;

If the satisfied then needs of these two condition neither ones are made the accumulating operation of h (m) * s (i-m).

If complete serial computing, promptly only with 1 accumulator, then the calculating of one 79 Sout needs 64*16=1024 clock.Take all factors into consideration computing time and area, adopt the structure of 10 points of parallel computation, need like this to repeat 8 times.Calculate one time 10 points.10 points were example in the past, and formula (29) is launched, and expansion is as follows:

Sout(0)＝h(0)*s(0)

Sout(1)＝h(0)*s(1)+h(1)*s(0)

Sout(2)＝h(0)*s(2)+h(1)*s(1)+h(2)*s(0)

Sout(3)＝h(0)*s(3)+h(1)*s(2)+h(2)*s(1)+h(3)*s(0)

Sout(9)＝h(0)*s(9)+h(1)*s(8)+h(2)*s(7)+h(3)*s(6)+h(4)*s(5)+h(5)*s(4)+h(6)*s(3)

+h(7)*s(2)+h(8)*s(1)+h(9)*s(10)

From vertically seeing above-mentioned expansion, it is constant to obtain every middle h sequence location that adds up, and every of s sequence changes, if the current iteration number of times is k, k=1～10, sout sequence number i=(k-1) * 10～(k-1) * 10+9 that calculate for the k time then, each sout accumulation calculating needs 16 clocks.The h sequence data that at every turn adds up when judging is identical, therefore Rule of judgment 1 at first, if effective diameter, the parallel again condition 2 of judging 10 sout is then calculated h*s if all satisfy.Adopting this structure to need computing time altogether is 10*16=160 clock.

Accumulator module of the present invention is divided two kinds of alignment accumulation calculating modes in the Interference Cancellation unit, its computing formula is

$\left\{\begin{array}{c}{d}_{\mathrm{out}}\_i=s_{\mathrm{local}}\_i-s_{\mathrm{out}}\_i\\ s_{\mathrm{local}}\_i+1=d_{\mathrm{out}}\_i+s_{\mathrm{in}}\_i+1\end{array}\right.---\left(30\right)$

Wherein the subtraction of first formula can be done addition by first supplement sign indicating number again, only calculates first formula as i=1,2,3,8 the time.

The object that alignment adds is two sequence of complex numbers, one 144 point, another is 79 points, first first effective diameter position that obtains according to channel estimating of alignment added-time needs is with two sequence alignments, read 79 point data of two sequences continuously from positions aligning, correspondence adds 79 times, and the sequence of complex numbers that obtains is 144 points, and alignment procedure is seen Fig. 5.

Two sections sequence of complex numbers all are stored among the RAM, are respectively RAM_dio and RAM_sout, and the choosing of RAM_sout sheet is provided by Interference Cancellation unit controls module.Two block RAMs simultaneously read 79 data continuously, and the RAM_dio data address is first_pos[6:0]～first_pos[6:0]+78, the address 0～78 of RAM_sout, corresponding addition, the result who obtains writes among the RAM_dio again, and the address is with to read the address identical.Therefore doing once alignment adds computing and needs 79*2=158 clock.

The system and method for counteracting serial interference in a kind of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) provided by the present invention, because having adopted will be through channel estimating, Interference Cancellation cell signal alignment of data after signal reconstruction is handled, carry out accumulating operation, draw the mode of relative clean signal, reduced the time domain serial interference of system, offer the cleaner signal of user, the quality and the whole system operation efficient of received signal have been improved, user's enthusiasm and job enthusiasm have been increased simultaneously, the user can be put in the work whole-heartedly go, thereby further improved user's operating efficiency.

Should be understood that the description of above-mentioned specific embodiment is comparatively detailed, can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.

Claims (10)

1, the system of counteracting serial interference in a kind of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) is characterized in that described system comprises: counteracting serial interference control module, descending synchronous code read-only memory module, Interference Cancellation unit module; Described counteracting serial interference control module is connected with described descending synchronous code read-only memory module, described Interference Cancellation unit module respectively;

Described counteracting serial interference control module is used for calling the enabling signal of Interference Cancellation unit, and provides the input parameter of Interference Cancellation unit;

Described descending synchronous code read-only memory module is used to read descending synchronous code;

Described Interference Cancellation unit module is used to offset the interference signal of sub-district.

2, system according to claim 1, it is characterized in that, described Interference Cancellation unit module also comprises: an Interference Cancellation unit controls module, a channel estimation module, a signal reconstruction module and an accumulator module, described Interference Cancellation unit controls module respectively with described channel estimation module, signal reconstruction module, and accumulator module is connected;

Described Interference Cancellation unit controls module is used to provide the enabling signal of channel estimating, signal reconstruction, accumulator module and the input parameter of each module;

Described channel estimation module is used for estimating by the computing of descending synchronous code power and associated window being carried out cell channel;

Described signal reconstruction module is used for channel estimation window and descending synchronous code are carried out convolution algorithm;

Described accumulator module is used for the Interference Cancellation unit sequence of complex numbers accumulating operation that aligns.

3, system according to claim 2 is characterized in that, described accumulator module also is used for Interference Cancellation unit sequence of complex numbers alignd and subtracts computing.

4, system according to claim 1 is characterized in that, described counteracting serial interference system is divided into the secondary serial structure, and each level comprises some Interference Cancellations unit.

5, a kind of counteracting serial interference method according to claim 1, it comprises the steps:

A, the interference signal in the Interference Cancellation unit module is carried out data processing, obtain this Interference Cancellation cell signal data;

B, with described Interference Cancellation cell signal alignment of data, carry out plus and minus calculation, draw the relative clean signal;

C, described counteracting serial interference control module are called last Interference Cancellation cell signal data, and start next Interference Cancellation unit operations, obtain next Interference Cancellation cell signal data;

D, repeat above-mentioned steps C, dispose, show that then the Interference Cancellation unit finishes signal, and produce interrupt signal up to all Interference Cancellation blocking interferers.

6, method according to claim 5 is characterized in that, described steps A may further comprise the steps:

A1, interference signal in the described Interference Cancellation unit is carried out channel estimation process:

A2, interference signal in the described Interference Cancellation unit is carried out signal reconstruction handle.

7, method according to claim 6 is characterized in that, described steps A 1 may further comprise the steps:

A11, interference signal in the described Interference Cancellation unit carried out successively sync correlation computing, relevant control, power calculation, thresholding are calculated, the active path search is handled, obtain channel estimation value.

8, method according to claim 6 is characterized in that, described steps A 2 may further comprise the steps:

A21, employing flowing water ring structure carry out convolution algorithm with the descending synchronous code and the described channel estimation value of described Interference Cancellation unit.

9, method according to claim 5 is characterized in that, the plus-minus among the described step B by formula: d _Out=d _In+ s _In-s _OutCarry out computing; Wherein:

d _OutBe the signal behind the current Interference Cancellation unit Interference Cancellation;

d _InBe the signal behind the last Interference Cancellation unit Interference Cancellation;

s _InSignal for last Interference Cancellation unit reconstruct respective cell;

s _OutSignal for current Interference Cancellation unit reconstruct current area;

When the Interference Cancellation unit is the first Interference Cancellation unit, s _InBe set to 0.

10, method according to claim 5 is characterized in that, calling by formula among the described step C: $\mathrm{ICU}\_i\_\mathrm{start}=\left\{\begin{array}{cc}\mathrm{SIC}\_\mathrm{start}& i=1\\ \mathrm{ICU}\_i-1\_\mathrm{ouer}& \mathrm{else}\end{array}\right.$ Carry out computing, draw a series of each Interference Cancellation cell parameters:

When i＜=4, then icu_sync_id=sync_id_i, icu_thsig=sic_thsig1, souti_cs=i;

When i＞4, icu_sync_id=sync_id_i-4 then, icu_thsig=sic_thsig2, then souti_cs=i-4;

icu_thnoise＝sic_thnoise；

Wherein: described equation expression implication is:

When i=1, ICU_i_start=SIC_start then;

When i＞1, ICU_i_start=ICU_i-1_over then;

Described ICU_i_start is an i Interference Cancellation unit initial signal data value;

Described SIC_start is a counteracting serial interference initial signal data value;

Described ICU_i-1_over is an i-1 Interference Cancellation unit end signal data value;

Described icu_sync_id is Interference Cancellation units synchronization sign indicating number address;

Described sync_id_i is that sequence number is the Interference Cancellation units synchronization sign indicating number address of i;

Described sync_id_i-4 is that sequence number is the Interference Cancellation units synchronization sign indicating number address of i-4;

Described icu_thsig is an Interference Cancellation cell signal threshold value;

Described sic_thsig1 is an one-level counteracting serial interference signal threshold value;

Described sic_thsig2 is a secondary counteracting serial interference signal threshold value;

Described icu_thnoise is an Interference Cancellation unit Noise Gate value;

Described sic_thnoise is a counteracting serial interference Noise Gate value;

Described souti_cs is the Interference Cancellation unit number.

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