CN101640805A - Video decoding method and video decoder - Google Patents
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Abstract
The invention discloses a video decoding method and a video decoder, which are used for receiving video code streams sequentially and decoding and outputting the video code streams. The video decodingmethod comprises the following steps: marking errors; recording error codes in the process of decoding according to the decoding situation; concealing the errors; generating error concealment parameters according to the error codes recorded in the step of marking the errors; and outputting the error concealment parameters and decoded video code stream data according to a receiving sequence.
Description
Technical field
The present invention relates to the coding and decoding video field, especially a kind of video encoding/decoding method and Video Decoder.
Background technology
In the coding and decoding video field, the video code flow after how can be decoding compressed efficiently is the unremitting power that the technical staff makes great efforts to explore always.
Releasing the MPEG-2 compression standard with 1994 is example, Moving Picture Experts Group-2 is the compression scheme under various application and the specified in more detail of system layer at Standard Digital Television and high definition TV, encoder bit rate is from per second 3 megabits～100 megabits, and the formal standard of standard is in ISO/IEC13818.MPEG-2 is specially adapted to the coding and the transmission of the Digital Television of broadcast level, is identified as the coding standard of SDTV and HDTV.The principle of MPEG-2 image compression is to have utilized two specific characters in the image: spatial coherence and temporal correlation.These two kinds of correlations make and have a large amount of redundant informations in the image.If we can remove these redundant informations, only keep a small amount of irrelevant information and transmit, just can save transmission band greatly.And the recipient utilizes these irrelevant information, according to certain decoding algorithm, can recover original image under the prerequisite that guarantees certain picture quality.
Equally, in other video encoding and decoding standards such as AVS standard, H.264 equally also exist two specific characters in the image in the standard: spatial coherence and temporal correlation.This two specific character makes and has a large amount of redundant informations in the image.Need a kind of analytic method and device, should save transmission band greatly, guarantee again to recover original image under the prerequisite of certain picture quality.
In November calendar year 2001 south China Polytechnics journal the 29th volume o. 11th disclosed " design of the variable word length decoder of a MPEG-2 video decode " literary composition, a kind of video parser is disclosed, as shown in Figure 1.Bit stream A is by the ordering of big end order, and it is sent into 16 grades through the PIC bus and firmly gets first-in first-out FIFO buffer memory, and the data among the FIFO are sent into register B and register A successively then, and both form 64 output as parallel shift unit input.Parallel shift unit selects 32 outputs to be used for identification and decoding according to the displacement figure place from 64 bit data of input.Whether see behind the initial code with there being video to resolve its structural extended sign indicating number, be embodied as comparator according to its corresponding hardware such as level identification of sequence head, sequence extension, figure group (GOP) head, image head, image encoding expansion, head, macro block, piece.
In existing video codes resolver and video codes decoder,, only write down the error code in the resolving, and described error code is not done any processing according to the parsing situation.Error code behind record and the mark and correct sign indicating number export next module together to like this, are decoded by next module.Easy like this causing to the end, follow-up module has been abandoned the error code behind record and the mark and has only been exported correct sign indicating number, has reduced part display frame after vision signal is shown, and the continuity of picture has been subjected to great influence.
Summary of the invention
An object of the present invention is to provide successional video encoding/decoding method of a kind of reservation raw frames and decoder.
For addressing the above problem, the present invention by the following technical solutions:
First aspect, the invention provides a kind of video encoding/decoding method, order receiver, video code stream is decoded and is exported, described video encoding/decoding method comprises the error identification step, according to the decoding situation, the error code in the carrying recorded decoding process, its special character is: described video encoding/decoding method also comprises the error concealment step, cover parameter according to the error code generation error that writes down in the error identification step, described error concealment parameter and decoded video codeword data stream are exported in proper order by reception.
Above-mentioned error concealment parameter obtains according to the average of error code adjacent block.
Above-mentioned video encoding/decoding method also comprises the decoding length changeable code step, the variable length code that decoding receives; Described decoding length changeable code step comprises two-stage pipeline step at least, and the clock in the first order pipeline step adopts the method for prefix identification, draws the length of described variable length code; Clock in the pipeline step of the second level is used for decoding the Run-Length Coding of described variable length code correspondence, and will carry out the error code record in the decoded variable length code input error error identification step.
Above-mentioned video encoding/decoding method also comprises code stream analyzing step, code stream buffer memory step, described code stream buffer memory step is used for asking and the receiver, video bit stream data, described code stream analyzing step receives and resolves the video code flow from code stream buffer memory step, and the generation control signal, be used for controlling the decoding that the decoding length changeable code step is finished variable length code.
The inner ping-pong operation pattern that adopts of above-mentioned code stream buffer memory step comprises having two storing steps at least in the code stream buffer memory step, when one of them storing step was resolved the data of its inside, another storing step loaded the data of its inside.
Above-mentioned video encoding/decoding method comprises: major state step and sub-state step, and described major state step comprises the initial code identification step, judges and the identification initial code; Described major state step is controlled the startup of sub-state step by the parsing of initial code, monitors the result that finishes that sub-state step returns simultaneously; The parameter input parameter that described sub-state step obtains parsing is deposited step and is preserved, and returns and finish the result to the major state step.
Above-mentioned sub-state step comprises: sequence head/sequence extension decoding step, judge and recognition sequence head and/or sequence extension that described sequence head and sequence can in proper order or be judged and discern simultaneously; Figure head/image spreading decoding step judges and identification figure head and/or image spreading that described figure head and image can in proper order or be judged and discern simultaneously; The fragment decoding step is judged and the identification fragment; The macroblock/block decoding step is judged and identification macro block and/or piece, and simultaneously to decoding length changeable code step output control signal, described macro block and piece can in proper order or be judged and discern simultaneously.
Second aspect, the invention provides a kind of Video Decoder, order receiver, video code stream is decoded and is exported, comprise the error identification device, be used for according to the decoding situation, the error code in the carrying recorded decoding process, its special character is: described Video Decoder also comprises the error concealment device, be used for covering parameter according to the error code generation error that writes down in the error identification device, the video codeword data stream after described error concealment parameter and the parsing is exported in proper order by reception.
Above-mentioned error concealment device obtains the error concealment parameter according to the average of error code adjacent block.
Above-mentioned Video Decoder also comprises the decoding length changeable code device, the variable length code that decoding receives; Described decoding length changeable code device comprises at least two level production lines, and the clock of first order streamline adopts the method for prefix identification, draws the length of described variable length code; The clock of second level streamline is used for decoding the Run-Length Coding of described variable length code correspondence, and will carry out the error code record in the decoded variable length code input error error identification device.
The present invention makes the erroneous macroblock parameter carried out valuation by having increased the error concealment device of covering parameter according to the error code generation error of identification record in original video codes resolver, the picture that obtains being similar to these parameters.The continuity that keeps original picture.Thereby also reach the purpose of saving transmission band and can guarantee certain picture quality.The present invention is described in detail below in conjunction with accompanying drawing, and these and other purpose of the present invention, feature, aspect and advantage will become more obvious.
Description of drawings
Fig. 1 is the principle schematic of the video parser of background technology;
Fig. 2 is the schematic flow sheet of video encoding/decoding method embodiment 1 of the present invention;
Fig. 3 is the schematic flow sheet of video encoding/decoding method embodiment 2 of the present invention;
Fig. 4 is the structural representation of Video Decoder embodiment of the present invention.
Embodiment
In order to make those skilled in the art person understand the present invention program better, and above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with embodiment and embodiment accompanying drawing.
With reference to figure 2, schematic flow sheet for video encoding/decoding method embodiment of the present invention, video encoding/decoding method of the present invention comprises: at first carry out order receiver, video sign indicating number step 1, carry out decoding step 2 then, carry out order at last and export step 5, error identification step 3 is in the process of decoding step 2, according to the decoding situation, error code in the carrying recorded decoding process, error concealment step 4, error code generation error according to record in the error identification step 3 is covered parameter, and described error concealment parameter is input to order and exports in the step 5 and decoded video codeword data stream is exported in proper order.Described error code can be organized for macro block.The generation of described error concealment parameter mainly utilized on time, space of code block adjoining like relation, handle according to different situations, the different characteristic of adjacent code block and to select parameter.Code block both can be the video code flow of particular segment here, also can be meant macro block or be the fritter under the macro block.Concrete can try to achieve the error concealment parameter according to the average of error code adjacent block.The purpose of doing like this is exactly the error code success error concealment that will write down in the error identification device, and then obtains the approximate or correct video image of class, guarantees the continuity of original picture.Other follow-up modules receive the code stream of resolving through the video codes resolver according to normal workflow, and then decoding and displaying.
With reference to figure 3, schematic flow sheet for video encoding/decoding method embodiment 2 of the present invention, compare with Fig. 2, decoding step 2 comprises: code stream buffer memory step 6, code stream analyzing step 15, decoding length changeable code step 7, the selection of displacement figure place and accumulation step 13, parameter are deposited step 14.
Code stream buffer memory step 6 is used for asking, receives and the preservation video codeword data stream, and exports described video codeword data stream.The inner ping-pong operation pattern that adopts of described code stream buffer memory step 6 comprises having two storing steps at least in the code stream buffer memory step 6, when one of them storing step was resolved the data of its inside, another storing step loaded the data of its inside.Use this mode of operation, can guarantee each clock new data of can decoding.When receiving the carry information indicating that the displacement figure place is selected and accumulation step 13 produces, code stream buffer memory step 6 needs to switch the data of using the another one storing step, and the start bit of the next decoded data of displacement information indicating that the displacement figure place is selected and accumulation step 13 produces is corresponding to the side-play amount of memory highest order in the storing step in the code stream buffer memory step 6 that is used.
Code stream analyzing step 15 is used for receiving the video code flow from code stream buffer memory step 6, and it is resolved, and signal is sent to decoding length changeable code step 7, the selection of displacement figure place and accumulation step 13 respectively after will resolving, parameter is deposited step 14 and carried out decoding processing.Described code stream analyzing step 15 also comprises following substep:
Initial code identification step 9 is judged and the identification initial code initial code signal after the output identification.
Sequence head/sequence extension decoding step 10 is judged and recognition sequence head and/or sequence extension, sequence head and/or sequence extension signal after the output identification.Can in proper order or judge simultaneously and discern.
Figure head/image spreading decoding step 11 is judged and identification figure head and/or image spreading the figure head/image spreading signal after the output identification.Can in proper order or judge simultaneously and discern.
Macroblock/block decoding step 8 is judged and identification macro block and/or piece, macro block and/or block signal after the output identification, and simultaneously to decoding length changeable code step 7 output control signal.Described macro block and piece can in proper order or be judged and discern simultaneously.
The concrete setting of above-described initial code identification step 9, sequence head/sequence extension decoding step 10, figure head/image spreading decoding step 11, fragment decoding step 12, macroblock/block decoding step 8 these class steps is according to standard time-frequency code stream such as MPEG2, AVS, H.264 the taxeme of video code flow, from top to bottom, adopt master slave mode machine nested configuration.Wherein initial code identification step 9 is major state steps, controls the startup of sub-state step by the parsing of initial code, monitors the result that finishes that sub-state step returns simultaneously; More than each decoding step except that the initial code identification step all is sub-state step, described each sub-state step is finished the parsing of corresponding level syntactic element, the parameter that parsing is obtained deposits parameter in and deposits to finish in the step and deposit, and returns and finish the result and give the major state step.
Decoding length changeable code step 7 is used for finishing the decoding of video data variable length code, and the output decoder signal.Its control signal is obtained by macroblock/block decoding step 8.Concrete, the Run-Length Coding of described decoding length changeable code step 7 output video coefficient.In the specific implementation of decoding length changeable code step 7, with the MPEG2 standard is example, what the MPEG2 video data adopted is Huffman encoding, the data that probability of occurrence is bigger are represented with short code word, the less data of probability of occurrence are represented with long code word, to reduce the effect that mean code length reaches compressed video data.By characteristics of Huffman encoding in the coefficient table B.14 and B.15 in analysis of MPEG 2 standards, can adopt following two kinds of methods for designing: one, in view of coefficient table B.14 and B.15 some coding identical, so identical coding item is merged, reduced total coding item; Two, the design of two level production lines is adopted in the decoding of variable length code, first clock adopts the method for prefix identification according to the characteristics of variable length code, only draws the length of this variable length code; Second clock decodes the Run-Length Coding of this variable length code correspondence.The advantage that adopts above technical scheme is to reduce to design the gate quantity of realization and improve the speed that design realizes.Can also in each clock cycle, parse a fixed length code or variable length code, and have the function of error flag and error concealment parameter generating.Allowing to exist under the situation of error code, the present invention can provide high-quality image.
The displacement figure place is selected and accumulation step 13, from the displacement figure place output of each sub-steps of code stream analyzing step 15 and decoding length changeable code step 7, select a current effective value, and this effective value added up, add up and resolve into carry and displacement information, feed back to code stream buffer memory step 6.
Parameter is deposited step 14, receives the signal from code stream analyzing step 15 and decoding length changeable code step 7, and preserves the parameter output in the decode procedure of these two steps.Afterwards described parameter being exported to order exports step 5 and carries out order and export.
In the present embodiment, error identification step 3 is according to the error code in the decoding situation record code stream decode procedure of code stream analyzing step 15 and/or decoding length changeable code step 7.
Based on above thought, the invention allows for a kind of Video Decoder, order receiver, video code stream is decoded and is exported, as shown in Figure 4, comprise error identification device 200, be used for according to the decoding situation, error code in the carrying recorded decoding process, described error concealment device 300 is used for covering parameter according to the error code generation error of record in the error identification device 200, and the video codeword data stream after described error concealment parameter and the parsing is exported in proper order.Described error concealment device 300 obtains the error concealment parameter according to the average of error code adjacent block.Described error code can be organized for macro block.The generation of described error concealment parameter mainly utilized on time, space of code block adjoining like relation, handle according to different situations, the different characteristic of adjacent code block and to select parameter.Code block both can be the video code flow of particular segment here, also can be meant macro block or be the fritter under the macro block.Concrete can try to achieve the error concealment parameter according to the average of error code adjacent block.The purpose of doing like this is exactly the error code success error concealment that will write down in the error identification device, and then obtains the approximate or correct video image of class, guarantees the continuity of original picture.Other follow-up modules such as IDCT device 600, motion compensation unit 700 etc. receive the code stream of resolving through code stream analyzing device 500 according to normal workflow, and then decoding output.
Described Video Decoder also comprises the decoding length changeable code device, the variable length code that decoding receives; Described decoding length changeable code device comprises at least two level production lines, and the clock of first order streamline adopts the method for prefix identification, draws the length of described variable length code; The clock of second level streamline is used for decoding the Run-Length Coding of described variable length code correspondence, and will carry out the error code record in the decoded variable length code input error error identification device 200.The control signal of decoding length changeable code device is by obtaining in the code stream analyzing device 500.Concrete, the Run-Length Coding of described decoding length changeable code device output video coefficient.In the specific implementation of decoding length changeable code device, with the MPEG2 standard is example, what the MPEG2 video data adopted is Huffman encoding, the data that probability of occurrence is bigger are represented with short code word, the less data of probability of occurrence are represented with long code word, to reduce the effect that mean code length reaches compressed video data.By characteristics of Huffman encoding in the coefficient table B.14 and B.15 in analysis of MPEG 2 standards, can adopt following two kinds of methods for designing: one, in view of coefficient table B.14 and B.15 some coding identical, so identical coding item is merged, reduced total coding item; Two, the design of two level production lines is adopted in the decoding of variable length code, first clock adopts the method for prefix identification according to the characteristics of variable length code, only draws the length of this variable length code; Second clock decodes the Run-Length Coding of this variable length code correspondence.The advantage that adopts above technical scheme is to reduce to design the gate quantity of realization and improve the speed that design realizes.
Described code stream buffer storage 100 is used for asking, receives and preserves video codeword data stream.The ping-pong operation pattern can be adopted in code stream buffer storage 100 inside, has two quantum memories in code stream buffer storage 100 at least, and when the data in one of them quantum memory were resolved, another quantum memory can carry out data and load.Use this mode of operation, can guarantee that each clock can resolve new data.
Described error identification device 200, according to the parsing situation of code stream analyzing device 500 and/or decoding length changeable code device, the error code in the record code stream decode procedure.The decoding correctness situation of each macro block can output to external memory storage and preserve.In order to cooperate the work of error identification device 200, all be provided with the error detector device in code stream analyzing device 500 and the decoding length changeable code device, described error detector device is specifically as follows logical circuit or logic coding.After the mistake that occurs in the code stream discerning, error identification device 200 stores these error messages according to current sheet sector address and macroblock address.
The video code flow that code stream analyzing device 500 receives from the buffer memory in the code stream buffer storage 100.And the video code flow of the buffer memory that receives resolved, the back signal be will resolve and decoding length changeable code device, error identification device 200 sent to respectively.Described code stream analyzing device 500 also comprises following sub-device:
The initial code recognition device is judged and the identification initial code initial code after the output identification.
Sequence head/sequence extension decoding device is judged and recognition sequence head and/or sequence extension, the sequence head/sequence extension sign indicating number after the output identification.Can in proper order or judge simultaneously and discern.
Figure head/image spreading decoding device is judged and identification figure head and/or image spreading the figure head/image spreading sign indicating number after the output identification.Can in proper order or judge simultaneously and discern.
The fragment decoding device is judged and the identification fragment.Sheet segment encode after the output identification.
The macroblock/block decoding device is judged and identification macro block and/or piece, macro block and/or piece after the output identification, and simultaneously to decoding length changeable code device output control signal.Described macro block and piece can in proper order or be judged and discern simultaneously.
The setting of above-described initial code recognition device, sequence head/sequence extension decoding device, figure head/image spreading decoding device, fragment decoding device, this class device of macroblock/block decoding device is according to standard time-frequency code stream such as MPEG2, AVS, H.264 the taxeme of video code flow, from top to bottom, adopt master slave mode machine nested configuration.Wherein initial code recognition device 7 is host state machines, controls the startup of sub-state machine by the parsing of initial code, monitors the result that finishes that sub-state machine returns simultaneously; More than each decoding device except that the initial code recognition device all is sub-state machine, and described each sub-state machine is finished the parsing of corresponding level syntactic element, and the parameter that parsing is obtained deposits the parameter LD device in, and returns and finish the result to host state machine.
IDCT (Inverse Discrete Cosine Transform) device 12, receive the Run-Length Coding and relevant macroblock layer and the following synchronizing signal of macroblock layer of the video coefficients of code stream resolver and/or decoding length changeable code device 3, finish the idct transform of video coefficients, described idct transform comprises inverse quantization, counter-scanning, inverse transformation etc.
Described decoder also comprises command register 14, and peripheral control unit can be finished specific function by writing register controlled order control stream resolver.
The above only is the specific embodiment of the present invention, and the present invention can also be applied in other video encoding and decoding standard, as MPEG2, AVS, standard or the like H.264.Protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses, and the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claim was defined.
Claims (10)
1, a kind of video encoding/decoding method, order receiver, video code stream is decoded and is exported, described video encoding/decoding method comprises the error identification step, according to the decoding situation, error code in the carrying recorded decoding process, it is characterized in that: described video encoding/decoding method also comprises the error concealment step, covers parameter according to the error code generation error that writes down in the error identification step, and described error concealment parameter and decoded video codeword data stream are exported in proper order by reception.
2, video encoding/decoding method according to claim 1 is characterized in that: described error concealment parameter obtains according to the average of error code adjacent block.
3, video encoding/decoding method according to claim 1 and 2 is characterized in that: described video encoding/decoding method also comprises the decoding length changeable code step, the variable length code that decoding receives;
Described decoding length changeable code step comprises two-stage pipeline step at least, and the clock in the first order pipeline step adopts the method for prefix identification, draws the length of described variable length code; Clock in the pipeline step of the second level is used for decoding the Run-Length Coding of described variable length code correspondence, and will carry out the error code record in the decoded variable length code input error error identification step.
4, video encoding/decoding method according to claim 3, it is characterized in that: described video encoding/decoding method also comprises code stream analyzing step, code stream buffer memory step, described code stream buffer memory step is used for asking and the receiver, video bit stream data, described code stream analyzing step receives and resolves the video code flow from code stream buffer memory step, and the generation control signal, be used for controlling the decoding that the decoding length changeable code step is finished variable length code.
5, video encoding/decoding method according to claim 4, it is characterized in that: the inner ping-pong operation pattern that adopts of described code stream buffer memory step, comprise in the code stream buffer memory step and have two storing steps at least, when one of them storing step was resolved the data of its inside, another storing step loaded the data of its inside.
6, video encoding/decoding method according to claim 5 is characterized in that: described video encoding/decoding method comprises: major state step and sub-state step, and described major state step comprises the initial code identification step, judges and the identification initial code; Described major state step is controlled the startup of sub-state step by the parsing of initial code, monitors the result that finishes that sub-state step returns simultaneously; The parameter input parameter that described sub-state step obtains parsing is deposited step and is preserved, and returns and finish the result to the major state step.
7, video encoding/decoding method according to claim 6, it is characterized in that: described sub-state step comprises: sequence head/sequence extension decoding step, judge and recognition sequence head and/or sequence extension that described sequence head and sequence can in proper order or be judged and discern simultaneously;
Figure head/image spreading decoding step judges and identification figure head and/or image spreading that described figure head and image can in proper order or be judged and discern simultaneously;
The fragment decoding step is judged and the identification fragment;
The macroblock/block decoding step is judged and identification macro block and/or piece, and simultaneously to decoding length changeable code step output control signal, described macro block and piece can in proper order or be judged and discern simultaneously.
8, a kind of Video Decoder, order receiver, video code stream is decoded and is exported, comprise the error identification device, be used for according to the decoding situation, error code in the carrying recorded decoding process, it is characterized in that: described Video Decoder also comprises the error concealment device, is used for covering parameter according to the error code generation error that writes down in the error identification device, and the video codeword data stream after described error concealment parameter and the parsing is exported in proper order by reception.
9, Video Decoder according to claim 8 is characterized in that: described error concealment device obtains the error concealment parameter according to the average of error code adjacent block.
10, according to Claim 8 or 9 described Video Decoders, it is characterized in that: described Video Decoder also comprises the decoding length changeable code device, the variable length code that decoding receives;
Described decoding length changeable code device comprises at least two level production lines, and the clock of first order streamline adopts the method for prefix identification, draws the length of described variable length code; The clock of second level streamline is used for decoding the Run-Length Coding of described variable length code correspondence, and will carry out the error code record in the decoded variable length code input error error identification device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102469307A (en) * | 2010-11-12 | 2012-05-23 | 珠海全志科技股份有限公司 | Decoder and code stream analyzing device |
| CN102802023A (en) * | 2012-08-29 | 2012-11-28 | 上海国茂数字技术有限公司 | Method and device for rapidly preventing false start code |
| CN103297401A (en) * | 2012-03-01 | 2013-09-11 | 腾讯科技（深圳）有限公司 | Error code returning method and device |
| CN106454352A (en) * | 2010-04-05 | 2017-02-22 | 三星电子株式会社 | Low complexity entropy-encoding/decoding method and apparatus |
| CN108093258A (en) * | 2018-01-11 | 2018-05-29 | 珠海全志科技股份有限公司 | Coding/decoding method, computer installation and the computer readable storage medium of bit stream data |
| CN113645448A (en) * | 2021-08-09 | 2021-11-12 | 北京凌壹世纪科技有限公司 | Video decoding method and device suitable for command scheduling |
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2008
- 2008-07-28 CN CN 200810138814 patent/CN101640805A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106454352A (en) * | 2010-04-05 | 2017-02-22 | 三星电子株式会社 | Low complexity entropy-encoding/decoding method and apparatus |
| CN106454352B (en) * | 2010-04-05 | 2019-09-06 | 三星电子株式会社 | Low complex degree entropy coding/decoding method and apparatus |
| CN102469307A (en) * | 2010-11-12 | 2012-05-23 | 珠海全志科技股份有限公司 | Decoder and code stream analyzing device |
| CN102469307B (en) * | 2010-11-12 | 2014-04-16 | 珠海全志科技股份有限公司 | Decoder and code stream analyzing device |
| CN103297401A (en) * | 2012-03-01 | 2013-09-11 | 腾讯科技（深圳）有限公司 | Error code returning method and device |
| CN102802023A (en) * | 2012-08-29 | 2012-11-28 | 上海国茂数字技术有限公司 | Method and device for rapidly preventing false start code |
| CN102802023B (en) * | 2012-08-29 | 2014-08-27 | 上海国茂数字技术有限公司 | Method and device for rapidly preventing false start code |
| CN108093258A (en) * | 2018-01-11 | 2018-05-29 | 珠海全志科技股份有限公司 | Coding/decoding method, computer installation and the computer readable storage medium of bit stream data |
| CN108093258B (en) * | 2018-01-11 | 2020-06-16 | 珠海全志科技股份有限公司 | Code stream data decoding method, computer device and computer readable storage medium |
| CN113645448A (en) * | 2021-08-09 | 2021-11-12 | 北京凌壹世纪科技有限公司 | Video decoding method and device suitable for command scheduling |
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