CN101640522B - A kind of data pick-up method and device being applicable to decimation filter - Google Patents
A kind of data pick-up method and device being applicable to decimation filter Download PDFInfo
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Abstract
The invention discloses a kind of the data pick-up method and the device that are applicable to decimation filter, its device comprises: an input data buffer unit for storing sampled data, one, for carrying out the filter computing unit of predetermined filtering operation to sampled data and filter coefficient, arranges a data coefficient selected cell between described input data buffer unit and described filter computing unit.The inventive method and device are owing to carrying out predetermined reading from described input data buffer unit to sampled data by described data coefficient selected cell and choosing corresponding filter coefficient, realize often inputting M sampled data, described filter computing unit produces a filtering and exports; Doubly extract for M like this, the amount of calculation of filter is just reduced to original 1/M; Correspond to when using hardware implementing, just save the hardware resource such as multiplier and adder, thus reduce product cost, especially when M is larger, effect can be more obvious.
Description
Technical field
The present invention relates to a kind of data pick-up method and the device in digital processing field and integrated circuit (IC) design field; In particular be applicable to data pick-up method and the device of decimation filter in a kind of digital processing field and integrated circuit (IC) design field.
Background technology
Prior art, in digital processing field and integrated circuit (IC) design field, has and carries out conversion process requirement to the sample rate of digital signal; Such as: in digital communication systems, need the signal obtained high-speed sampling to do and reduce sample rate process and so-called down-sampling, to reduce the workload of operation of subsequent treatment.
For reducing the intractability of down-sampling, usually integral multiple extraction is carried out to the sampled data of input, such as: from three input sample signals, extract one of them signal as useful signal, and lose other two signals.But before input sampling data is extracted, need the restriction considering frequency, to guarantee to meet sampling theorem, the generation of prevention aliasing.Limit available decimation filter (being also frequency overlapped-resistable filter) to frequency to realize.
If the sample data sequence of input is: x (n), wherein n=0,1,2 ..., sample frequency is F
s, after M doubly samples, export y (Mn), M is positive integer, and sample frequency is F
s/ M; On frequency domain, its effect is equivalent to the cut-off frequency ω of input sampling data
celongate as M ω
c, for meeting sampling thheorem, then have M ω
c< π, i.e. ω
c< π/M, therefore must filter part more than π/M to reach anti-aliasing object by the sample frequency of input signal by decimation filter.Be illustrated in figure 1 decimation filter extraction process; As can be seen from Figure 1, extraction process is carried out after the filtering, and it is F that decimation filter is operated in sample rate
sfrequency domain in, and then take out one by every for filtered data M, thus realize down-sampling process.
Described above is the data pick-up method of decimation filter in prior art, but the method has following shortcoming: filtered every M data, one is only had to be used in follow-up process, and other M-1 to be all dropped need not, like this filtering operation that this M-1 data are done just has been wasted; Correspond to when using hardware implementing, waste filtering operation wastes the hardware resource such as multiplier and adder exactly, and this waste can increase product cost.
Thus, prior art needs to improve.
Summary of the invention
The object of the present invention is to provide a kind of the data pick-up method and the device that are applicable to decimation filter, by reducing the amount of calculation of filter, after making filtering, all data are all used in follow-up process and go, and reach the object of saving the hardware resource such as multiplier and adder.
Technical scheme of the present invention comprises:
A kind of data pick-up device being applicable to decimation filter, comprise: an input data buffer unit for storing sampled data, one, for carrying out the filter computing unit of predetermined filtering operation to sampled data and filter coefficient, wherein arranges a data coefficient selected cell between described input data buffer unit and described filter computing unit;
Described data coefficient selected cell is used for reading described sampled data from described input data buffer unit and choosing corresponding filter coefficient, and send to described filter computing unit, for to often inputting M sampled data, described filter computing unit produces a filtering and exports, and wherein M is extracting multiple.
Wherein said filter computing unit comprises: the multiplicaton addition unit of the parallel processing of setting number and an accumulator; Described multiplicaton addition unit is used for carrying out arithmetic operation to described sampled data and the respective filter coefficient chosen, and described arithmetic operation is multiply operation and add operation; Described accumulator is used for that the Output rusults of all multiplicaton addition units is carried out serial in chronological order and adds up.
Wherein this device is a finite impulse response filter.
Wherein said extracting multiple is positive integer and meets sampling theorem.
Be applicable to a data pick-up method for decimation filter, it comprises the following steps:
A, described data coefficient selected cell read sampled data and selecting filter coefficient, and send to described filter computing unit;
B, often input M sampled data, described filter computing unit produces filtering output, and M is extracting multiple, meets sampling theorem for positive integer.
Wherein said step B also comprises:
B1, the described filter computing unit described filter coefficient to the described sampled data received and correspondence makes predetermined filtering operation;
B2, often input M sampled data, described filter computing unit makes N multiply-add operation to the described sampled data received and corresponding filter coefficient, and N is the tap number of described decimation filter, is the integral multiple of M.
Wherein said steps A also comprises:
A1, described data coefficient selected cell read predetermined sampled data from described input data buffer unit;
A2, described data coefficient selected cell choose the filter coefficient corresponding with described sampled data;
Described sampled data and described filter coefficient are sent to described filter computing unit by A3, data coefficient selected cell.
Wherein said steps A 1 also comprises:
A11, to input described sampled data, carry out in a predetermined order in the buffering area of described input data buffer unit buffering preservation;
A12, described data coefficient selected cell read described sampled data from the predetermined memory address of described buffering area.
Wherein said steps A 12 also comprises: often input N number of sampled data, and the predetermined memory address of described input data buffer unit is stored in circulation, and N is the tap number of described decimation filter, is the integral multiple of M.
Wherein said steps A 2 also comprises:
A21, M sampled data is set to one group, successively when inputting first sampled data often organized, by corresponding with first filter factor for this first sampled data, upper one group of last sampled data is corresponding with second filter factor, until the sampled data inputted the earliest is corresponding with last filter factor;
A22, often input M sampled data, data coefficient selected cell completes to be selected filter coefficient one circulation.
A kind of data pick-up method and device being applicable to decimation filter provided by the present invention, by the reading of sampled data and the selection of respective filter coefficient, before realizing that data extraction process is placed on filtering, thus decreases filtering amount of calculation; In other words, doubly extract for M, filtering amount of calculation is just reduced to original 1/M; Correspond to when using hardware implementing, just save the hardware resource such as multiplier and adder, thus reduce product cost, especially when M is larger, effect can be more obvious.
Accompanying drawing explanation
Fig. 1 is decimation filter course of work schematic diagram of the prior art;
Fig. 2 is the structured flowchart of the filtering extraction apparatus of a preferred embodiment of the present invention;
Fig. 3 is the computing unit structure chart of 3 times of decimation filters of a preferred embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, will be described in detail preferred embodiment of the present invention.
The invention provides a kind of the data pick-up method and the device that are applicable to decimation filter, from input data buffer unit by data coefficient selected cell predetermined reading is carried out to sampled data and chooses corresponding filter coefficient; Realize often inputting M sampled data, filter computing unit produces a filtering and exports, and wherein M is extracting multiple, is positive integer; Thus decrease the amount of calculation of filter, reach and save the hardware resource such as multiplier and adder object.
The structured flowchart of the filtering extraction apparatus of a preferred embodiment of the present invention as shown in Figure 2, this device is a FIR (Finite Impulse Response-finite impulse response) filter, comprising: input data buffer unit, data coefficient selected cell, filter computing unit.The input sampling data that described device is used to high-speed sampling obtains carries out data pick-up and filtering operation, thus realizes predetermined down-sampling.
Described input data buffer unit is used to carry out buffering to input data and preserves.Described input data buffer unit comprises a buffering area, and the degree of depth of described buffering area is determined by the tap number of FIR filter; Such as: if FIR filter has 30 taps, then the degree of depth of this buffering area is 30.
Described data coefficient selected cell is used to read described sampled data from described input data buffer unit and choose corresponding filter coefficient, and sends to described filter computing unit.Be the decimation filter of N for a tap number, do not consider the symmetry of coefficient, then need after N multiply-add operation, just can obtain a filtering and export, wherein N is the integral multiple of M.In the prior art, for M extraction process doubly, filter will obtain M filtering output just can complete a complete filtering operation; But the present invention considers that M-1 filter output is wherein invalid, described data coefficient selected cell reads predetermined sampled data in input data buffer unit, and choose corresponding filter coefficient, therefore filter just completes a filtering operation after only need completing N multiply-add operation, like this, filtering operation amount is just reduced to original 1/M; In other words, calculating an output valve by often inputting a sampled data correspondence in the past exactly, making every M input into and only producing an output valve.
Filtering extraction processing procedure of the present invention is: according to the convolution process of filter, launched, then according to the sampling period of each input, take out data from the discrete cell input data buffer unit, deliver in filter computing unit and go, also will select corresponding coefficient simultaneously, so just can complete the multiply-add operation of N/M time, then input M data, just complete the multiply-add operation of N time, obtain a complete output valve.
Described filter computing unit comprises: the multiplicaton addition unit of setting number parallel processing and an accumulator.The filter coefficient that described multiplicaton addition unit exports described data coefficient selected cell and sampled data carry out multiply operation and add operation, and the output of the multiplicaton addition unit of these concurrent workings serially accumulates together by described accumulator in chronological order.
Below with one more specifically embodiment describe the implementation process of the present invention in detail.
Such as: extracting multiple is 3, the tap number of filter is 24, and the sample rate of input data is 30MHz, and the clock frequency of described plant running is 60MH; Like this, after 3 times are extracted, exporting the sample rate of data is 10MHz, and that is, every two clock cycle input a sampled data, and every 6 clock cycle export the sampled data of a computing after filtering.
Filter at the convolution process of time domain is:
Expand into:
y(n)＝x(n)×h(0)+x(n-1)×h(1)+x(n-2)×h(2)+...+x(n-23)×h(23)(2)
M sampled data is set to one group, successively when inputting first sampled data often organized, by corresponding with first filter factor for this first sampled data, upper one group of last sampled data is corresponding with second filter factor, until the sampled data inputted the earliest is corresponding with last filter factor; In other words, the data X (n) of up-to-date input is multiplied with h (0), and data X (n-23) is multiplied with h (23) the earliest, needs calculating 24 multiply-add operations altogether.
If output only gets y (n) after extracting, wherein n=3m (m=0,1,2 ...), so as n=3m+1 and n=3m+2, these inputs are not processed, but utilize this time period to complete in above formula the computing of remainder.Input 3 sampled datas and need 6 clock cycle, therefore each clock cycle will process 4 multiplyings, with 4 MAC (Multiplication Add Cell-multiplicaton addition unit) parallel processing, these four MAC unit are numbered MAC1, MAC2, MAC3, MAC4 respectively, as shown in Figure 3.
The buffer depth of described input data buffer unit is 24, preserves with register; First data is written to address 0, and data are below written to address 1,2... respectively, circulate from address 0 again after being written to address 23, the data therefore inputted can be numbered x (24n), x (24n+1) always, x (24n+2), ..., x (24n+23), corresponding address number is A0, A1, A2 ..., A23; The data of described buffering area are read by 4 described MAC simultaneously, and each clock cycle reads once.
In described data coefficient selected cell, coefficient number is respectively H0, H1 ..., H23, coefficient of correspondence h (0) is to h (23) respectively; When inputting data x (24n), after data are written to address A0, regulation MAC1 completes the computing of A0 ~ A5 address, MAC2 completes the computing of A6 ~ A11 address, MAC3 completes the computing of A12 ~ A17 address, MAC4 completes the computing of A18 ~ A23 address, then in the adjacent next clock cycle (because every two clock cycle input data) in this cycle and this cycle, have:
MAC1：A0*H0+A1*H23
MAC2：A6*H18+A7*H17
MAC3：A12*H12+A13*H11
MAC4：A18*H6+A19*H5
Wherein H0 is exactly coefficient h (0), and H23 is exactly coefficient h (23), and other is analogized, and the data now in A1 are 24n-23, and the corresponding relation of input sampling data and filter coefficient will meet above-mentioned formula (2).
After input data x (24n+1) is written to A1, MAC1 peeks from A2, thus avoids the data in the A1 after by renewal get into participation computing and lead to errors, because the data in A1 participated in computing in the last cycle, then has:
MAC1：A2*H22+A3*H21
MAC2：A8*H16+A9*H15
MAC3：A14*H10+A15*H19
MAC4：A20*H4+A21*H3
In like manner can analogize, after input data x (24n+2) is written to A2, have
MAC1：A4*H20+A5*H19
MAC2：A10*H14+A11*H13
MAC3：A16*H8+A17*H7
MAC4：A22*H2+A23*H1
Like this, input data are x (24n), x (24n+1), x (24n+2) respectively, after correspondence is written to A0, A1, A2, just complete all 24 multiplyings in formula (2) and the add operation except accumulating operation, then each MAC Output rusults is carried out accumulating operation, just obtain a filtering and export; In other words, every 3 sampled datas only export a sampled data after filtering extraction, thus complete a complete filtering extraction process.
When inputting data x (24n+3), after being written to A3, the data of up-to-date input are multiplied at A3 and h (0), and the data inputted the earliest are multiplied at A4 and h (23), correspondingly obtain following formula:
MAC1：A3*H0+A4*H23
MAC2：A9*H18+A10*H17
MAC3：A15*H12+A16*H11
MAC4：A21*H6+A22*H5
In like manner can analogize, after input data x (24n+4) is written to A4, have:
MAC1：A5*H22+A6*H21
MAC2：A11*H16+A12*H15
MAC3：A17*H10+A18*H19
MAC4：A23*H4+A0*H3
In like manner can analogize, after input data x (24n+5) is written to A5, have:
MAC1：A7*H20+A8*H19
MAC2：A13*H14+A14*H13
MAC3：A19*H8+A20*H7
MAC4：A1*H2+A2*H1
Like this, other 3 sampled datas export again a sampled data after filtering extraction.
Drawing analogous conclusions down, after being written to A21 when inputting data x (24n+21), having:
MAC1：A21*H0+A22*H23
MAC2：A3*H18+A4*H17
MAC3：A9*H12+A10*H11
MAC4：A5*H6+A6*H5
In like manner can analogize, after input data x (24n+22) is written to A22, have:
MAC1：A23*H22+A0*H21
MAC2：A5*H16+A6*H15
MAC3：A11*H10+A12*H19
MAC4：A17*H4+A18*H3
In like manner can analogize, after input data x (24n+23) is written to A23, have
MAC1：A1*H20+A2*H19
MAC2：A7*H14+A8*H13
MAC3：A13*H8+A14*H7
MAC4：A19*H2+A20*H1
So just have input 24 data, shared 48 clock cycle, obtain 8 filtering and export, thus complete a large period circulation; When input the 25th data, will restart to perform said process.
The input sampling data of each MAC in the different clocks cycle and the corresponding relation of filter coefficient as can be seen from the above; Each MAC inputs every 48 the clock cycle circulation primary of data, and coefficient is every 6 clock cycle circulation primary then.
In sum, the present invention is carried out predetermined reading to sampled data by data coefficient selected cell from input data buffer unit and chooses corresponding filter coefficient; Realize often inputting M sampled data, filter computing unit produces a filtering and exports; Doubly extract for M like this, filtering amount of calculation is just reduced to original 1/M; Correspond to when using hardware implementing, just save the hardware resource such as multiplier and adder, thus reduce product cost, especially when M is larger, effect can be more obvious.
Should be understood that, the above-mentioned description for specific embodiment is comparatively detailed, and therefore can not think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (9)
1. be applicable to a data pick-up device for decimation filter, comprise: an input data buffer unit for storing sampled data, one, for carrying out the filter computing unit of predetermined filtering operation to sampled data and filter coefficient, is characterized in that,
One data coefficient selected cell is set between described input data buffer unit and described filter computing unit;
Described data coefficient selected cell is used for reading described sampled data from the discrete cell described input data buffer unit and choosing corresponding filter coefficient, and send to described filter computing unit, described filter computing unit is used for carrying out N/M multiply-add operation to this sampled data, then often input M sampled data and carry out N multiply-add operation, produce a filtering to export, wherein M is extracting multiple, described N is the tap coefficient of decimation filter, and described data coefficient selected cell is also for reading predetermined sampled data from described input data buffer unit; Described data coefficient selected cell chooses the filter coefficient corresponding with described sampled data; Described sampled data and described filter coefficient are sent to described filter computing unit by data coefficient selected cell, and described filter computing unit is used for making predetermined filtering operation to the described sampled data received and corresponding described filter coefficient; Often input M sampled data, described filter computing unit makes N multiply-add operation to the described sampled data received and corresponding filter coefficient, N is the tap number of described decimation filter, for the integral multiple of M, wherein, described filter computing unit comprises: the multiplicaton addition unit of the parallel processing of setting number and an accumulator; Described multiplicaton addition unit is used for carrying out arithmetic operation to described sampled data and the respective filter coefficient chosen, and described arithmetic operation is multiply operation and add operation; Described accumulator is used for that the Output rusults of all multiplicaton addition units is carried out serial in chronological order and adds up.
2. device according to claim 1, is characterized in that, this device is a finite impulse response filter.
3. device according to claim 1, is characterized in that, described extracting multiple is positive integer and meets sampling theorem.
4. a data pick-up method for device as claimed in claim 1, it comprises the following steps:
A, described data coefficient selected cell read sampled data and selecting filter coefficient, and send to described filter computing unit;
B, often input M sampled data, described filter computing unit produces filtering output, and M is extracting multiple, meets sampling theorem for positive integer.
5. data pick-up method according to claim 4, is characterized in that, described step B also comprises:
B1, the described filter computing unit described filter coefficient to the described sampled data received and correspondence makes predetermined filtering operation;
B2, often input M sampled data, described filter computing unit makes N multiply-add operation to the described sampled data received and corresponding filter coefficient, and N is the tap number of described decimation filter, is the integral multiple of M.
6. data pick-up method according to claim 4, is characterized in that, described steps A also comprises:
A1, described data coefficient selected cell read predetermined sampled data from described input data buffer unit;
A2, described data coefficient selected cell choose the filter coefficient corresponding with described sampled data;
Described sampled data and described filter coefficient are sent to described filter computing unit by A3, data coefficient selected cell.
7. data pick-up method according to claim 6, is characterized in that, described steps A 1 also comprises:
A11, to input described sampled data, carry out in a predetermined order in the buffering area of described input data buffer unit buffering preservation;
A12, described data coefficient selected cell read described sampled data from the predetermined memory address of described buffering area.
8. data pick-up method according to claim 7, it is characterized in that, described steps A 12 also comprises: often input N number of sampled data, and the predetermined memory address of described input data buffer unit is stored in circulation, N is the tap number of described decimation filter, is the integral multiple of M.
9. data pick-up method according to claim 6, is characterized in that, described steps A 2 also comprises:
A21, M sampled data is set to one group, successively when inputting first sampled data often organized, by corresponding with first filter factor for this first sampled data, upper one group of last sampled data is corresponding with second filter factor, until the sampled data inputted the earliest is corresponding with last filter factor;
A22, often input M sampled data, data coefficient selected cell completes to be selected filter coefficient one circulation.
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| CN102891662B (en) * | 2011-07-22 | 2017-09-12 | 中兴通讯股份有限公司 | A kind of general rate down-conversion, up conversion device and method |
| CN102403986B (en) * | 2011-11-25 | 2015-05-06 | 京信通信系统（中国）有限公司 | Multi-channel CIC (Cascade Integrator Comb) decimation filter and method for realizing same |
| CN102412808B (en) * | 2011-11-25 | 2015-01-21 | 南京中新赛克科技有限责任公司 | FPGA (Field-Programmable Gate Array)-based high-performance multipath FIR (Finite Impulse Response) digital extraction filter and reading method thereof |
| CN109802691A (en) * | 2019-01-24 | 2019-05-24 | 中科驭数（北京）科技有限公司 | The filtering method and device of sequence data |
| CN110247642B (en) * | 2019-06-13 | 2023-07-11 | 江苏卓胜微电子股份有限公司 | FIR filtering method and filter |
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| CN1494211A (en) * | 2002-09-25 | 2004-05-05 | 三洋电机株式会社 | Sampling extracting filter and internally inserted filter |
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