CN101639799B - Integrated circuit characterization system and method - Google Patents
Integrated circuit characterization system and method Download PDFInfo
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- CN101639799B CN101639799B CN 200810144441 CN200810144441A CN101639799B CN 101639799 B CN101639799 B CN 101639799B CN 200810144441 CN200810144441 CN 200810144441 CN 200810144441 A CN200810144441 A CN 200810144441A CN 101639799 B CN101639799 B CN 101639799B
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Abstract
The invention provides a system and a method for characterizing an integrated circuit to compare with the predefined system features related to features of the integrated circuit operation, wherein a test program is executed on the integrated circuit causing the feature, and meanwhile at least one operation bottleneck limiting the integrated circuit operation is introduced so as to show the system level operation related to the feature, the data responded to and generated by the bottleneck through the test program is collected, thus the uniformity of the shown system level operation and the predefined system level feature is compared.
Description
Technical field
The present invention relates to integrated circuit, particularly a kind of integrated circuit characterization system and method.
Background technology
Various features, structure and/or the attribute of integrated circuit (IC) carry out textual description by multiple file types usually.For example, advantage and/or the benefit of multiple description document in order to represent that a kind of integrated circuit has with respect to version or rival's product before it arranged.This describes document and can include, but are not limited to, marketing material, advertising campaign, user manual and technical manual, purchase and (or) make agreement, Recent Progresses In The Development report, intellecture property document, like that.
In some cases, the validity of assessing these statements is useful or necessary, whether also has like attribute otherwise need to again investigate competing product.For example, manufacturer may one or more performance standards or the product qualification whether followed under a cloud about the statement of certain specific properties of integrated circuit, and itself or again verification in the scope of Quality Control Procedure are perhaps detected in the research of with it competition.Or these characteristics can be the theme of lawsuit, for example relate in the event that is associated with certain given product know-how property right at one.For example, firstly have any one party who has by the right of the integrated circuit of defined some feature of one or more Patent right requirement, may seek to investigate a rival product, whether have infringement to these claims with the commercialization of assessing this product.In this example, usually need to use the evidence of subject content required for protection, this type of evidence is usually collected from one or more products that obtain of opening the markets and is obtained.
Be right after example, the patent (or aforesaid other description document) of the microelectronic that requires to support may claimed uniqueness circuit and/or structure.Just as the skilled person will be apparent, usually use traditional reverse engineering method can obtain support to these claims, therefrom " extraction " go out the circuit of IC and/or the details of structure.
Extracting the technology of circuit from integrated circuit will easily see for those of ordinary skill.Usually, interested circuit generally is less than 10,000.In the case; from the product of finishing, (for example extract circuit; obtain circuit from the physical layout that is arranged in the circuit component of integrated circuit on one or more layers), obtain a schematic diagram, and whether provide circuit required for protection to judge to this schematic diagram.
When the circuit of discussing had the door number that surpasses above-mentioned quantity, the method for layering and extraction circuit became more difficult.Yet it can fully provide the special characteristic of the operation of integrated circuit in the situation that circuit has this quantity door.Namely, the existence of the circuit of this in integrated circuit provides the specific function of this integrated circuit.
Therefore this just exists the classic method of using reverse engineering to carry out circuit extraction to be difficult for acquisition to the situation of the support of claimed theme.A specific examples that belongs to this situation comprises the system-level characteristic of so-called integrated circuit operation, but is not limited only to this.That is, use conventional method to the system level operation of the integrated circuit that is in completion status determine it is very difficult, if not impossible words.In addition, although existing multiple benchmark can be used for the performance of integrated circuit under different condition like the comparing class, this test can only detect the overall performance of integrated circuit under different running loads, and can't detect its system-level operation.Therefore, work in a similar fashion under varying environment although can determine two integrated circuit, these test procedures can not detect the system-level operation of the integrated circuit of these work of execution.In addition, traditional operating system is adopted in the realization of traditional performance test program usually, wherein, under multiple situation, its original operation of this operating system (OS) maskable, and then hide interested original system level operation.
Therefore need a kind of new integrated circuit characterization system and method to overcome some defectives of prior art.
The material that this background information provides the applicant to think that possibility is related to the present invention.Need not to refer in particular to what also needn't explain is that the material before any has all consisted of the prior art with the present invention's contrast.
Summary of the invention
One of purpose of the present invention is, a kind of integrated circuit characterization system and method are provided.
According to an aspect of the present invention, provide a kind of sign integrated circuit (IC) to be used for the method that compares with the predefined system-level feature relevant with the characteristic (aspect) of integrated circuit operation, said method comprising the steps of: carry out test procedure at the described integrated circuit that causes described characteristic; During this execution in step, quote at least one operation bottleneck (operational bottleneck), limiting the operation of described integrated circuit, thereby present the system level operation that it is relevant to described characteristic; Respond described bottleneck and collect the data that produce by described test procedure; And relatively by this system level operation of this presentation of data and the consistance of the system-level feature of described predefine.
According to another aspect of the present invention, provide a kind of sign integrated circuit (IC) to be used for the system that compares with the predefined feature relevant with the characteristic of integrated circuit operation, described system comprises: computer-readable medium, comprise statement and the instruction carried out at described integrated circuit by described system, so that operation is configured to cause the test procedure of described characteristic, quote simultaneously at least one operation bottleneck limiting the operation of described integrated circuit, thereby present the system level operation relevant with the described characteristic of described integrated circuit; Data storage device is used for this bottleneck of response and collects the data that produce by this test procedure; And output, be used for this system level operation and the predefine feature that are presented by these data are carried out comparison of coherence.
According to a further aspect of the invention, a kind of statement carried out by integrated circuit (IC) and computer-readable medium of instruction of comprising is provided, characterizes described integrated circuit to compare with the predefine feature relevant with a characteristic of integrated circuit operation according to following steps: be configured to cause that the described integrated circuit of described characteristic carries out test procedure; During this execution in step, quote at least one operation bottleneck, limiting the operation of described integrated circuit, thereby show that it is relevant to the system level operation of described characteristic; Respond this bottleneck and collect the data that produce by this test procedure; And access this data, carry out comparison of coherence with system level operation and the predefined operating characteristics that will be presented.
For the person of ordinary skill of the art, obviously can understand other aspects of the present invention and advantage by reference to the accompanying drawings and with reference to following description of the invention, and the structure of different embodiments of the invention and operation.
Description of drawings
The present invention will be further described below in conjunction with accompanying drawing, wherein:
Fig. 1 is the process flow diagram of integrated circuit characterization method according to an embodiment of the invention;
Fig. 2 is the process flow diagram of integrated circuit characterization method according to another embodiment of the present invention, and wherein the running environment of this integrated circuit is through adjusting to disclose its original operation;
Fig. 3 is the process flow diagram that is used for according to an embodiment of the invention supporting the integrated circuit characterization method of Patent right requirement;
Fig. 4 is the schematic block diagram that is used for according to an embodiment of the invention characterizing a kind of system of integrated circuit;
Fig. 5 A is the schematic block diagram that is used in accordance with another embodiment of the present invention characterizing a kind of system of integrated circuit;
Fig. 5 B is used for revising open source operating system according to an embodiment of the invention to carry out a kind of method flow diagram of integrated circuit characterization method;
Fig. 6 is according to one embodiment of the invention, the curve map of the data of when carrying out the integrated circuit characterization method, collecting, and this integrated circuit characterization method is for assessment of a system level operation, and this operation relates to the accessing operation of the high-speed cache of a multi-core microprocessor; And
Fig. 7 is the process flow diagram of test procedure according to an embodiment of the invention, and test procedure is carried out at each nuclear of a multi-core microprocessor simultaneously, and to assess a system level operation, this operation relates to the accessing operation of parallel storage.
Embodiment
For illustrative purposes, enumerated exemplary specific embodiment so that thoroughly understand the present invention.Yet those of ordinary skill as can be known, does not have these detailed details the present invention can implement from content of the present disclosure yet.In addition, well-known element, device, treatment step and similar content are not described in detail, in order to avoid fuzzy scope described in the invention.
Such as non-specified otherwise, all technology used herein and scientific terminology are all identical with the common understanding of a those of ordinary skill in its technical field under the present invention.
Generally speaking, the invention provides a kind of integrated circuit characterization method and system, such as, can be used for extracting one or more system level operation of (for example reverse engineering) integrated circuit, in certain embodiments, be used for propose, state and/or advocate that the relevant operating characteristics of the therewith adhesive integrated circuit of right makes comparisons.For example, according to an embodiment, method and system described herein can be used for determining to the system level operation of integrated circuit, its objective is with its with integrated circuit is relevant therewith description document in those operations of describing in detail compare.For example, these features can describe in detail in the Patent right requirement that is authorized to protect, and wherein the patentee may wish to assess some system level operation of a kind of commercially available integrated circuit, and the feature of protecting with these claims compares.Therefore, in one embodiment, show the controlled infringer of substantially the same or similar operation for those integrated circuit of selling in market, the method and system can be used for allowing or helping the obligee to advocate it in one or more integrated circuit (IC) design or the right of one or more operating characteristicses.
Generally speaking, the operating characteristics in this design is relevant with one or more features of integrated circuit (IC) system level operation.Such as, just as one of ordinary skill in the understanding, " system-level " feature has generally included the feature more complicated than simple logical function, such as be the known feature relevant with standard logic element that can find of those of ordinary skills in integrated circuit.For example, in one embodiment, this system level operation can be obtained by the large functional block of circuit, or by rudimentary firmware or similarly in this integrated circuit operation and provide one or more therewith the relevant functional block of total characteristic of integrated circuit operation obtain (such as power management, memory management and access etc.).Just as the skilled person easily understood, the example of low-level system functions including, but not limited to: such as the cache management algorithm, translation look aside buffer (TLB) algorithm, bus request arbitration process, memory request queue, the power management of unit and suchlike operation.Be noted that and in the file relevant with given integrated circuit, usually do not put down in writing this function.Thereby method and system of the present invention make people can have access to this function that obtains from integrated circuit supplier or manufacturer of being difficult for.Similarly, even supplier or manufacturer provide this class file, method and system of the present invention can make people can verify the statement of these functions to verify that this file is made.
In certain embodiments, also can consider or consider alternatively higher system-level function.For example, higher system level function can comprise operation and the microprocessor-based control register of instruction set.Hold intelligiblely as those of ordinary skill, do not breaking away under current disclosed total scope and spirit also admissible other examples including, but not limited to the operation of instruction set, memory control unit, register, control register, bus specification etc.Although this type of high system level function can be put down in writing hereof, and therefore therefrom compare analysis, method and system described here still can be used as replenishing of comparison document analysis, and perhaps the another kind of file analysis is selected as a comparison.
As to be described in detail below, various embodiments of the present invention is as the description of the original operation of integrated circuit, and namely the original system level of the original imagination of integrated circuit and design operates.For the purpose of these embodiment, the operating characteristics relevant with original operation is considered to those operating characteristicses that the low-level characteristics of integrated circuit operation determines, comprises any firmware of circuit and upper operation thereof, perhaps their combination.
Usually can hide original operation of integrated circuit in the more high-level software that integrated circuit moves.Can hide the example of software of original operation including, but not limited to, operating system (OS), basic input/output (BIOS) or can be in the more high-level software that this integrated circuit moves.Especially, for original operation of integrated circuit, above-mentioned software can apply similar function or to its covering.Except the original operation that may hide integrated circuit, operating system can forbid testing the ability of this integrated circuit operation.Particularly, this operating system can limit the program capability to even lower level operation, and if this integrated circuit tested can cause the unstable of integrated circuit operation.
Thereby some embodiment can hide by one or more layers software that the system-level characteristic that is configured to relax integrated circuit operation is carried out at integrated circuit.In this type of embodiment, by a kind of suitable running environment is provided, the system and method that provides is used for observing directly or indirectly the system level operation of needed integrated circuit.
Referring to Fig. 1, and according to one embodiment of the invention, will a kind of method 100 that characterizes integrated circuit be described.Generally speaking, method 100 provides the sign integrated circuit to detect wherein one or more system level operation, is used for comparing with the predefined system-level feature relevant with the same or similar characteristic of integrated circuit operation.As discussed above, this predefined feature can be in the context of description document or one skilled in the relevant art's other scope of easily seeing in define.Describe such as Fig. 1, at first determine the system-level feature (step 102) relevant with a characteristic of integrated circuit operation.Carry out afterwards the test procedure (step 104) that causes this characteristic thereon, quote simultaneously at least one operation bottleneck (operational bottleneck) (step 106) limiting the operation of this integrated circuit, thereby present its system level operation relevant with this characteristic.Collect afterwards the data (step 108) that this bottleneck of response produces by test procedure, and the consistance of the system level operation (step 110) that relatively therefore presents and predefine feature.
With reference to figure 2, and according to another embodiment of the invention, provide a kind of similar characterizing method 200, wherein original operation of integrated circuit operating environment of being integrated circuit shields or hides.For example, can think that " environment " comprised the condition that integrated circuit operates therein, such as by operation thereon operating system and/or those of ordinary skill in the art the condition that provides of other these type of softwares easy to know, firmware.Thereby this environment can be hidden some interested system level operation (such as relevant with it or tested by its offset behavior that affects).Under this situation, the environment of integrated circuit operation need be done change to collect desired data.Therefore, once in step 202, determining predefined system-level feature, the running environment of system can (for example the adjusting operation system be to provide the operation that is not subjected to or substantially not affected by operating system step 203 adjustment, forbid peripherals, driving, interruption etc.), under the running environment of adjusting, carry out like this operation (step 204) of test procedure.Therefore, under these conditions referencing operation bottleneck (step 206), and collection responds the data (step 208) that this bottleneck produces by test procedure, thereby is convenient to system level operation and the predefined feature of this integrated circuit of comparison.
Referring to Fig. 3, and according to a further embodiment of the invention, a kind of integrated circuit characterization method 300 be used to supporting one or more Patent right requirements is proposed.Generally speaking, the analyst who analyzes a specific patent and interested integrated circuit can application process 300 assesses system-level feature required for protection whether by the clearly expression of system level operation institute of the integrated circuit of discussing.In step 302, determined the system-level feature by the Patent right requirement definition.In step 304, carry out test procedure to cause the characteristic of the integrated circuit operation that patent is conceived at integrated circuit, simultaneously, in step 306, quote the operation bottleneck that limits this integrated circuit operation, to present the system level operation of this integrated circuit.In step 308, collect data and the system level operation that presents thus and claimed feature and compare in step 310.
As above with reference to figure 2 described embodiment, whether the present embodiment can also comprise the judgement about following aspect: whether interested system level operation (for example original operation) can directly be measured and/or be caused (for example under normal operating condition/environment), perhaps need to provide adjustment to running environment with further outstanding interested operation.
When selection and/or execution test procedure, must make different considerations, this is obvious to those skilled in the art.Such as, although the characteristic that is configured to cause the integrated circuit operation relevant with the predefine feature that test procedure is total, it also can be configured or be optimized for to trigger performance measurement, this measurement might be given prominence to interested system level operation better, thereby is easier to compare with predefined feature.In addition, configurable test procedure is to produce wing passage information/data (side-channel information/data) with the observation integrated circuit operation.The example of this type of wing passage information including but not limited to signal, power consumption, rf frequency, regularly, temperature (for example running temperature, Temperature Distribution etc.) and like that.
Referring to Fig. 4, and according to one embodiment of the invention, a kind of system 400 for characterizing integrated circuit 402 will be described now, in order to assess its system level operation.In this embodiment, system 400 is configured to move not affected in the environment of (or not affected by operating system) by operating system.What integrated circuit 402 was total can comprise any integrated circuit that moves an operating system.Yet in current embodiment, integrated circuit 402 includes the microprocessor of a plurality of processing nuclear and at these internuclear shared cache memories.Other features of processor core, buffer memory and microprocessor are not described in Fig. 4, and this is apparent to those of ordinary skills.Integrated circuit 402 is operation system 404 thereon.Although the operating system 404 of Fig. 4 mark is positioned at integrated circuit 402, it more may be physically located in the nonvolatile memory, and including but not limited to hard drive or suitable solid-state memory, this is apparent to those of ordinary skills.In the present embodiment, integrated circuit 402 is positioned within computing equipment or the system 406, understands such as those of ordinary skill in the art, and this system can comprise the different types of equipment that can carry out at this integrated circuit multiple test procedure.In this specific embodiment, system 406 comprises personal computer and operating system 404, and this operating system 404 comprises the operating system based on Linux, and it is customized to collect wing passage information, such as the timing of fc-specific test FC.The operation of test macro 408 monitoring ics 402.This test macro 408 is suitable for monitoring the operational measure of integrated circuit 402.It should be noted that integrated circuit 402 and being connected to of test macro 408 only done simple schematically mark among Fig. 4, can not inevitable therefrom infer the actual form that both connect.For example, test macro 408 can integral body be implemented in disposal system 406, perhaps an other part as an autonomous device.For it should be appreciated by those skilled in the art, can carry out within the scope of the invention these and other this class and change.
According to one embodiment of present invention, Fig. 5 A further provides about the details of the method for adjusting operation system 504 where necessary.As above introduce, the operation that can not revise in such a way integrated circuit that operating system 504 is total that is: is covered and/or is changed interested system level operation in the observation.Therefore, operating system 504 can have code unit 502, can revise and/or hide the operation of the integrated circuit that is removed in the time of suitably.By increasing further retouching operation system 504 of code unit 506.Unit 506 can comprise the test procedure that for example can give prominence to interested integrated circuit operation feature.
Referring to Fig. 5 B, and according to one embodiment of the invention, provide a kind of and prepared or adjust a kind of operating system to be used for the method 510 of different embodiments of the invention, this adjustment is essential or preferred, in order to the shielding that reduces or avoid integrated circuit (IC) system level interested is operated.Provide a kind of open source operating system in step 512, it can be comprised of a kind of (SuSE) Linux OS in this embodiment.In step 514, this operating system is modified to remove the unit of the original operation of integrated circuit that may the cache test.In step 516, in operating system, insert special instruction to cause the operating characteristic relevant with interested system level operation.In this embodiment, the instruction introduced by further change be suitable for quoting limit this integrated circuit operation the operation bottleneck to present these system level operation.
In this specific embodiment, revised the function start_kernel () of Linux2.6.x kernel, in order to before initiating hardware, device driver and operating system scheduling parts, insert calling the program of operation test procedure.The output of test procedure is finished by function printk ().This test procedure is designed to integrated circuit to be measured is back to the test premode, and allows the normal start-up routine of Linux.When initialization hard disk drive, controller equiment driving, file system, scheduler and log recording are machine-processed, the output that Linux will line up the printk () of formation writes the kernel log document, the document can be accessed, and the system level operation that will present thus compares with the system-level feature of predefine of discussing.
Referring now to concrete example the present invention is described.Be appreciated that following example purpose is to describe embodiments of the invention and be not to limit by any way the present invention.
In first example, and according to one embodiment of the invention, provide a kind of method, with determine with at the relevant system level function of the management of the predictive storage resource request that the multinuclear of integrated circuit is inner between reaching.For example, provide a kind of method with judge dual core processor second process nuclear producing high-speed cache not in the time, its first process to examine and whether can stop from shared cache the predictive of instruction and look ahead.For realizing the method, in open source operating system, insert following exemplary test procedure, it is configured to move in the environment that not affected by operating system or not affected by operating system:
For (I=0; I＜50,000,000/* is greatly to not being contained in the high-speed cache/*; ++ I)
{
Access I storage page
for(j＝0；j＜N；++j)NOP；
}
Just as known to persons of ordinary skill in the art, top test procedure obtains huge speed advantage by the predictive prefetch mechanisms, and this mechanism allows to obtain I+1 memory page when carrying out without operation (NOP) order.By carrying out simultaneously this program with different parameters N in multinuclear, people can give prominence to microprocessor and how process the storer that conflict is arranged that produces obtain and prefetch request in different IPs.
For example, under a kind of situation, in the patent claims that relate to the management of dual core processor high speed cache access or description document, provide following operating characteristics.In this case, when first processor core L1 produce high-speed cache not in the time, L1 is to the L2 Forward-reques.Then 2 sector row requests (sector line request) are sent to the FSB interface and begin stage casing not from memory transfer to L2.When second processor core L1 produce high-speed cache not in, L1 is sent to the FSB interface with 2 sector row requests simultaneously again to the L2 Forward-reques.If first affairs are endowed high priority (directly not in), that will initiate the capable transmission of proximity caching.Otherwise, if having this FSB as second processor request of second FSB agency, will stop first affairs so, begin simultaneously the processing of second affairs.
For the operation of limit ic to present this system level operation, test procedure is carried out under the environment that not affected by operating system, disabled interrupt and most of peripherals no initializtion.In addition, all other data pre-fetching mechanism (for example data pre-fetching logic DPL etc.) have been turned off.In this specific example, test procedure is always carried out in first nuclear, second nuclear or a) free time or b) read continuously independently 64MB data array, therefore continue to produce high-speed cache not in.Therefore, produce a bottleneck and move with limiting processor so that present the mode of interested system level operation, be i.e. the mode of utilizing different high-speed caches that the handling capacity that monitoring facilities carries out is set as described below.
Fig. 6 demonstrates the data that the bottleneck that is cited by the test procedure response in the cache access between management core of collection produces.That is, for different situations, draw the figure as the execution time of the test of the function of NOP (N) quantity." graticule line " is to open the situation that adjacent row is looked ahead and suspended second nuclear." triangle line " is to close the situation that adjacent row is looked ahead and suspended second nuclear." circular lines " is to open the situation that adjacent row is looked ahead and second is examined in producing not.At last, " lineae trapezoidea " is to close the situation that adjacent row is looked ahead and second is examined in producing not.
As follows to top test result assessment.(the grid of opening about prefetcher, test case 1) and close (triangle, test case 2) the monokaryon test result the time can be inferred when prefetcher is opened, and the request that produces for a plurality of application heaps that comprise two (2) adjacent sectors responds first high-speed cache not.In addition, allow to finish the transmission (being about 150 NOP) of two (2) adjacent sectors if the quantity of NOP is abundant, the finishing of this transmission can provide obvious performance improve (when the quantity of NOP greater than 150 the time, graticule line is positioned under the triangle line).
In the test situation in second nuclear constantly produces not, because Front Side Bus (FSB) needs the transmission of service high priority, required transmission impacts to test procedure in these transmission, and the performance of test procedure is degenerated comprehensively.Yet if the adjacent lines prefetcher is opened, the performance graph of test procedure (circular lines) is consistent with the performance graph of the test of monokaryon when prefetcher is closed; And by closing capable prefetcher, performance graph can not change (being circular lines and lineae trapezoidea coupling) by internal.Therefore, the conclusion that obtains from test data is, when test 3 is carried out (circular lines), respond first not in, caused the transmission of (comprising two adjacent cache line sectors) of a plurality of application heaps, and respond produce on second nuclear second not in and stop; Then, by transmitting a cache line sector (i.e. more than second application heap), L2 cache (L2) serve this not in.
Refer now to Fig. 7, and according to another embodiment of the invention, propose polycaryon processor of a kind of evaluation and whether be arranged to allow a plurality of processing nuclears in a given clock period, to obtain the method for instruction from storer.Can be used for determining in much scopes, to realize concurrent access to cache memory based on sequential access such as, the method for the present embodiment.Adopt traditional reference test method, can realize that different test situation is with evaluation processor performance under these conditions.Yet which system-level operating characteristics determines the performance measurement that observes at least in part, and this is still unclear.Adopt following method, although performance measurement can be used for interpreter operation efficient, carry out an operation bottleneck that is configured to limit this integrated circuit operation to present interested system level operation, can realize or have at least being beneficial to the operation that observes and a kind of comparison of predefined feature.
In this specific embodiment, to have revised an open source operating system and moved at this integrated circuit being used for, the test procedure of describing among Fig. 7 like this can move under the environment that not affected by operating system.That is to say, for this specific examples, operating system is configured to not for figure, driver etc. provides interruption, the program operation that does not also allow other to hinder high-speed cache to use.
Concerning this example, on each nuclear of dual core processor, carry out simultaneously test procedure (if applicable words), to present the parallel work-flow corresponding to the high-speed cache of each nuclear.In this specific examples, the first order buffer memory (L1) of 32Kb is associated with each nuclear, and the shared L2 cache (L2) of 2Mb is shared internuclear.For the operation that limits this integrated circuit to present the system level operation of this integrated circuit of wanting, test procedure is configured to the referencing operation bottleneck, wherein the execution of this test procedure depends critically upon the access to L2 cache.As describing among Fig. 7, test procedure has recorded the processing time of S circulation carrying out the test of N piece, and wherein each piece comprises rear Jump (redirect) (+62 bit) with 62 NOP.By carrying out this test procedure for different N values, can present the system level operation of the integrated circuit of wanting, be used for comparing with the predefine operation characteristic of discussing.Such as, for N＜500, given nuclear access cache will be subject to the L1 buffer memory, but for N=16000, will take approximately half L2 buffer memory.For each N, cycle index S can adjust, and this depends on required precision grade.Therefore, utilize different data block settings, carry out the data that handling capacity is associated by collecting with program, can present the system level operation of this integrated circuit of pursuing, this will be obvious for those skilled in the art.
More than provided various exemplary embodiment of the present invention.In the situation that does not break away from total scope and spirit of the present invention, other this type of exemplary sequence also can be taken into account, and this will be obvious for those of ordinary skill in the art.Such as, can realize a similar method, can predictive ground carry out the instruction on the return address of current subroutine to assess a microprocessor.Quote the operation bottleneck that can present this system level operation, carry out test procedure to have side effects, wherein data at first are loaded into buffer memory, and use an inquiry " data have entered buffer memory " as the agency, with decision instruction whether by the execution of predictive (such as, buffer memory deposits in advance).
Another embodiment comprises and estimates how graphic process unit (GPU) manages or dispatch request (namely, for expected results in time relatively ignore regularly require fast as much as possible), such as, in order to make power consumption optimum.In a specific examples, carry out test procedure, the figure benchmark of its Plays is used to load GPU, change simultaneously to reproduce and ask to adjust (deadline adjustment) as acting on behalf of to be used for limitting absolutely, therefore between the exhausted limit of using, produced an operation bottleneck, thus the operation by suppressing GPU so that desirable system level operation presented.For further outstanding observation to system level operation, also adopt a radio-frequency probe (such as, in order further to obtain the wing passage data) load of monitoring and the GPU of the reproduction parameter synchronization that changes.
Yet in another example, can test the system level operation of a microprocessor, whether this test is to be " bound " in the individual pulse string in zonule of internal memory (such as 1 byte) about several requests.In order to observe this system level operation, respond a test procedure, monitoring and the performance of this processor relatively, this test procedure is configured to quote an operation bottleneck by sending continuous little request and burst request, presents this operation.
It should be appreciated by those skilled in the art, in the situation that does not break away from total scope and spirit disclosed by the invention, can consider above example and other this class testing program.
Although the most practical with preferred embodiment in detail the present invention has been described in detail according to what think at present, yet has should be appreciated that the embodiment that the present invention is not limited to disclose.Will be understood by those skilled in the art that, in the situation that does not break away from the scope of the invention that defines in claims and spirit, can make multiple modification and structure and function of equal value.Therefore, the present invention who defines in claims must be consistent with the most wide in range possible explanation, in order to comprise all this modifications and structure and function of equal value.
Claims (19)
1. one kind characterizes integrated circuit (IC) and is used for the method that compares with the predefined system-level feature relevant with the characteristic of integrated circuit operation, said method comprising the steps of:
Carry out test procedure at the described integrated circuit that causes described characteristic;
Described the term of execution, quote at least one operation bottleneck, limiting the operation of described integrated circuit, thereby present the system level operation that it is relevant to described characteristic;
Collect the data that the described bottleneck of response produces by described test procedure; And
Relatively by the described system level operation of described presentation of data and the consistance of the system-level feature of described predefine.
2. method according to claim 1, wherein said data comprise the wing passage data.
3. method according to claim 1, wherein the operation integrated circuit is carried out described test procedure in being conducive to present the environment of its original operation.
4. method according to claim 1, wherein the predefine feature is by the definition of the key element of the Patent right requirement relevant with integrated circuit operation, and the consistance of the key element of the wherein said operation that relatively comprises more described integrated circuit and described Patent right requirement.
5. method according to claim 1 wherein operates integrated circuit and carries out described test procedure under the environment that not affected by operating system.
6. method according to claim 5, wherein the described integrated circuit of operation may further comprise the steps under the environment that not affected by operating system:
Open source operating system is provided;
Adjust described open source operating system, the parameter of hiding in operation the original operation of described integrated circuit to remove at least one; And
Carry out the open source operating system of revising at described integrated circuit.
7. method according to claim 1, wherein said characteristic is selected from memory management and power management.
8. method according to claim 1, wherein said bottleneck is quoted by described test procedure.
9. method according to claim 1, wherein said bottleneck is quoted from described test procedure clearly.
10. method according to claim 1, wherein said feature comprises by the defined functional characteristic of descriptive document.
11. method according to claim 1, wherein said test procedure comprises benchmark test.
12. one kind characterizes integrated circuit (IC) and is used for the system that compares with the predefined system-level feature relevant with the characteristic of integrated circuit operation, this system comprises:
Be used for the device at the described integrated circuit execution test procedure that causes described characteristic;
Be used for described the term of execution, quoting at least one operation bottleneck limiting the operation of described integrated circuit, thereby present the device that it is relevant to the system level operation of described characteristic;
Be used for collecting the described bottleneck of response by the device of the data of described test procedure generation; With
Be used for relatively the described system level operation that presented by described data and the conforming device of the system-level feature of predefine.
13. system according to claim 12 also comprises the device that stores operating system (OS), described operating system (OS) is configured to make described test procedure to carry out at described integrated circuit.
14. system according to claim 13, wherein said operating system are configured to make described test procedure to carry out under the environment that not affected by operating system.
15. system according to claim 13, wherein said operating system comprises the operating system based on Linux.
16. system according to claim 13, wherein said operating system comprises forbidden interruption.
17. system according to claim 13 also comprises the peripherals of at least one no initializtion.
18. system according to claim 12, wherein said data comprise the wing passage data.
19. system according to claim 12, wherein said test procedure comprises benchmark test.
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| CN1890635A (en) * | 2003-10-02 | 2007-01-03 | 英特尔公司 | Methods and apparatus for reducing memory latency in a software application |
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