CN101635136A - Method and system for controlling low-speed display screen - Google Patents
Method and system for controlling low-speed display screen Download PDFInfo
- Publication number
- CN101635136A CN101635136A CN200910303215A CN200910303215A CN101635136A CN 101635136 A CN101635136 A CN 101635136A CN 200910303215 A CN200910303215 A CN 200910303215A CN 200910303215 A CN200910303215 A CN 200910303215A CN 101635136 A CN101635136 A CN 101635136A
- Authority
- CN
- China
- Prior art keywords
- display screen
- programmable logic
- pld
- control
- logic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 230000003993 interaction Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 210000000352 storage cell Anatomy 0.000 abstract 1
- IUQJDHJVPLLKFL-UHFFFAOYSA-N 2-(2,4-dichlorophenoxy)acetate;dimethylazanium Chemical compound CNC.OC(=O)COC1=CC=C(Cl)C=C1Cl IUQJDHJVPLLKFL-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a method for controlling a low-speed display screen, relating to the field of a low-speed display screen accessed by a high-speed processor. The method comprises the following steps: sending control command information of a display screen to a programmable logic part by a processor; receiving and reconstructing the control command information by the programmable logic part; controlling the display screen by the control command information reconstructed by the programmable logic part; and setting the data transmission rate of the display screen. The invention also discloses a system for controlling the access to a display screen. The invention ensures that the high-speed processor accesses the low-speed display screen without damaging the performance of the processor in data transmission, has no need to increase additional low-speed processors or select programmable logic parts with large numbers of registers/storage cells for preventing a large amount of gush data, reduces production cost, and adjusts the data transmission rate of a serial port according to the need of an LCD display screen to meet the requirement of flexible application.
Description
Technical field
The present invention relates to high speed processor visit low-speed display screen field, relate in particular to a kind of control method and control system of low-speed display screen.
Background technology
Frequency of operation owing to processor is improving constantly at present, the also corresponding raising of the message transmission rate of processor and interface device, usually cause the data transmission rate between low speed LCD display and the high speed processor not match, thereby cause LCD display correctly to work.Conventional art adopts following dual mode to solve at the problems referred to above: the mode that, reduces the data transmission rate of processor and interface device; Two, provide data buffer unit by programmable logic device (PLD).First kind of mode deals with comparatively directly with simple, but it has sacrificed the performance of system, crossing low data transmission rate and clock frequency makes the advantage of high speed processor all gone, simultaneously, usually outside high speed processor, be processor that processing speed is lower of the independent configuration of the LCD display of low speed, this has increased the cost of product virtually again.Data buffer unit limits the selection of programmable logic device (PLD) in the second way, if use image processing programs such as GUI, the output of graph data may be gush-type at short notice, this just requires that a large amount of register/memory unit must be arranged in the programmable logic device (PLD), such device often cost is very high, can increase the cost of product equally.
Summary of the invention
In order to solve above-mentioned deficiency of the prior art, the invention provides a kind of control method of low-speed display screen, solved high speed processor and the unmatched problem of low-speed display screen data transmission rate.
The present invention is achieved by the following technical solutions: design a kind of control method of low-speed display screen, comprise the steps,
The S1 processor sends the control command information of display screen to programmable logic device (PLD);
This programmable logic device (PLD) of S2 receives and the described control command information of reconstruct;
The control command information of this programmable logic device (PLD) reconstruct of S3 is controlled described display screen, sets the data transmission rate of display screen.
The present invention is further improved to be: described control command information comprises control signal, address and data message.
The present invention is further improved to be: among the described step S1, described processor is sent to programmable logic device (PLD) by will control the required control command information of described display screen with serial data mode.
The present invention is further improved to be: among the described step S2, described programmable logic device (PLD) is recombinated the control command information that receives and reconstitute by string and conversion and can control described display screen time sequence control information.
The present invention is further improved to be: the serial ports clock on the described processor and the sequential cycle of described display screen are carried out correspondence and energy adjusted in concert.
The present invention is further improved to be: described processor is provided with DMA, the serial output of described DMA control data; Described DMA provides spatial cache for described programmable logic device (PLD).
In order to apply the present invention to practice, the ad hoc control system of counting a kind of low-speed display screen comprises the processor that is provided with serial ports, programmable logic device (PLD) and display screen; Described processor, described programmable logic device (PLD) and described display screen carry out data interaction; Described processor transmitting control commands information is to described programmable logic device (PLD); Described programmable logic device (PLD) conversion and the described control command information of reconstruct.
The present invention is further improved to be: described control command information comprises control signal, address and data message.
The present invention is further improved to be: described processor is connected by serial ports with described programmable logic device (PLD); Described programmable logic device (PLD) with this control command information by the string and the conversion and be reconstructed into control described display screen time sequence control information.
The present invention is further improved to be: described processor is provided with DMA, the serial output of described DMA control data; Described DMA provides spatial cache for described programmable logic device (PLD).
The invention has the beneficial effects as follows: serial ports peripheral hardware and DMA and programmable logic device (PLD) that the present invention all possesses by adopting most processors, realize high speed processor visit low-speed display screen, make data transmission not sacrifice processor performance; Need not to increase extra low speed processor, also needn't select to have the programmable logic device (PLD) of a large amount of register/memory unit, save production cost for preventing a large amount of " gush " data; Can adjust the data transmission rate of serial ports according to the speed of LCD display needs, reach the requirement of flexible Application.
Description of drawings
Fig. 1 is the process flow diagram of the control method of low-speed display screen of the present invention.
Fig. 2 is the connection diagram of the control system of low-speed display screen of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention is further described.
As Fig. 1, a kind of control method of low-speed display screen comprises the steps:
The S1 processor sends the control command information of display screen to programmable logic device (PLD); This programmable logic device (PLD) of S2 receives and the described control command information of reconstruct; The control command information of this programmable logic device (PLD) reconstruct of S3 is controlled described display screen; Set the data transmission rate of display screen.The control command information that the control command information replacement of this programmable logic device (PLD) reconstruct is sent by processor is originally finished the control to display screen, thereby controls this display.
Described control command information comprises control signal, address and data message.
Among the described step S1, described processor is sent to programmable logic device (PLD) by will control the required control command information of described display screen with serial data mode.Among the described step S2, described programmable logic device (PLD) is recombinated the control command information that receives and reconstitute by string and conversion and can control described display screen time sequence control information.The serial ports clock on the described processor and the sequential cycle of described display screen are carried out correspondence and energy adjusted in concert.Described processor is provided with DMA (being Direct MemoryAccess direct memory access (DMA)), the serial output of described DMA control data; Described DMA provides spatial cache for described programmable logic device (PLD).
This processor is sent to programmable logic device (PLD) with the needed control command information of display screen with serial data mode by serial ports, programmable logic device (PLD) is recombinated data according to this information by string and conversion and reconstruct is satisfied LCD time sequence control signal and finished control to LCD display, realizes different transfer rate between processor and LCD screen by the sequential cycle of regulating the LCD screen.
For this method being applied to practice, the ad hoc control system of counting a kind of low-speed display screen as Fig. 2, comprises the processor 1 that is provided with serial ports, programmable logic device (PLD) 2 and display screen 3; Described processor 1, described programmable logic device (PLD) 2 are carried out data interaction with described display screen 3; Described processor 1 transmitting control commands information is to described programmable logic device (PLD) 2; Described programmable logic device (PLD) 2 conversion and the described control command information of reconstruct.
Described control command information comprises control signal, address and data message.Described processor 1 and described programmable logic device (PLD) 2 are connected by serial ports; Described programmable logic device (PLD) 1 with this control command information by the string and the conversion and be reconstructed into control described display screen 3 time sequence control information.Described processor is provided with DMA 4, the serial output of described DMA 4 control datas; Described DMA 4 provides spatial cache to realize the purpose of metadata cache for described programmable logic device (PLD) 2.
In a kind of preferred embodiment, a kind of mode of brand-new control LCD display solves the speed mismatch problem of high speed processor and low speed LCD.Serial ports (SPI, SPORT etc.) by processor 1 control signal, address and data message that LCD 3 is required is sent to programmable logic device (PLD) 2 in the mode of serial data, utilizes programmable logic device (PLD) 2 according to information data to be recombinated by string and conversion then and reconstruct is satisfied LCD time sequence control signal and finished control to LCD screen 3.The sequential cycle of LCD can have been satisfied the polytrope in LCD cycle by the configuration of serial ports clock is regulated, and the use of DMA 4 makes us not need to make this scheme can adapt to different applied environments at the special buffer memory of programmable logic device (PLD) 2 internal build again; And the serial of data output can be transferred to the DMA 4 of processor and controls, thereby can not impact performance of processors.
The present invention not only can be applicable to the control to the LCD screen, also be applicable to general slow storage visit, slow storage is replaced with LCD display, adopt identical control method and control system can realize data transmission, reached the optimum condition of data transmission it.
Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. the control method of a low-speed display screen is characterized in that: comprises the steps,
(S1) processor sends the control command information of display screen to programmable logic device (PLD);
(S2) this programmable logic device (PLD) receives and the described control command information of reconstruct;
(S3) control command information of this programmable logic device (PLD) reconstruct is controlled described display screen, sets the data transmission rate of display screen.
2. according to the control method of the described low-speed display screen of claim 1, it is characterized in that: described control command information comprises control signal, address and data message.
3. according to the control method of the described low-speed display screen of claim 2, it is characterized in that: in the described step (S1), described processor is sent to programmable logic device (PLD) by will control the required control command information of described display screen with serial data mode.
4. according to the control method of the described low-speed display screen of claim 3, it is characterized in that: in the described step (S2), described programmable logic device (PLD) is recombinated the control command information that receives and reconstitute by string and conversion and can control described display screen time sequence control information.
5. according to the control method of the described low-speed display screen of claim 4, it is characterized in that: the serial ports clock on the described processor and the sequential cycle of described display screen are carried out correspondence and energy adjusted in concert.
6. according to the control method of the described low-speed display screen of claim 5, it is characterized in that: described processor is provided with DMA, the serial output of described DMA control data; Described DMA provides spatial cache for described programmable logic device (PLD).
7. the control system of a low-speed display screen is characterized in that: comprise the processor that is provided with serial ports, programmable logic device (PLD) and can be external or the display screen of built-in controller; Described processor, described programmable logic device (PLD) and described display screen carry out data interaction; Described processor transmitting control commands information is to described programmable logic device (PLD); Described programmable logic device (PLD) conversion and the described control command information of reconstruct.
8. according to the control system of the described low-speed display screen of claim 7, it is characterized in that: described control command information comprises control signal, address and data message.
9. the control system of described low-speed display screen according to Claim 8, it is characterized in that: described processor is connected by serial ports with described programmable logic device (PLD); Described programmable logic device (PLD) with this control command information by the string and the conversion and be reconstructed into control described display screen time sequence control information.
10. according to the control system of the described low-speed display screen of claim 9, it is characterized in that: described processor is provided with DMA, the serial output of described DMA control data; Described DMA provides spatial cache for described programmable logic device (PLD).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910303215A CN101635136A (en) | 2009-06-12 | 2009-06-12 | Method and system for controlling low-speed display screen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910303215A CN101635136A (en) | 2009-06-12 | 2009-06-12 | Method and system for controlling low-speed display screen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101635136A true CN101635136A (en) | 2010-01-27 |
Family
ID=41594306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910303215A Pending CN101635136A (en) | 2009-06-12 | 2009-06-12 | Method and system for controlling low-speed display screen |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101635136A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012034523A1 (en) * | 2010-09-16 | 2012-03-22 | 深圳市明微电子股份有限公司 | Data transmission method and data receiving device |
| CN112346679A (en) * | 2019-08-07 | 2021-02-09 | 西安诺瓦星云科技股份有限公司 | Multi-display screen control system, display system and multi-display screen control method |
-
2009
- 2009-06-12 CN CN200910303215A patent/CN101635136A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012034523A1 (en) * | 2010-09-16 | 2012-03-22 | 深圳市明微电子股份有限公司 | Data transmission method and data receiving device |
| CN112346679A (en) * | 2019-08-07 | 2021-02-09 | 西安诺瓦星云科技股份有限公司 | Multi-display screen control system, display system and multi-display screen control method |
| CN112346679B (en) * | 2019-08-07 | 2024-01-09 | 西安诺瓦星云科技股份有限公司 | Multi-display control system, display system and multi-display control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11789892B2 (en) | Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface | |
| US8773328B2 (en) | Intelligent DMA in a mobile multimedia processor supporting multiple display formats | |
| US20140232731A1 (en) | Display power management | |
| CN109189716A (en) | A kind of data transmission system and transmission method based on FPGA | |
| US20140040512A1 (en) | Data transfer manager | |
| CN104714918B (en) | The reception of high speed FC bus datas and way to play for time under hosted environment | |
| CN105049781A (en) | Image processing system based on Field Programmable Gate Array (FPGA) | |
| CN105096877B (en) | A kind of display control method of display panel, device and its circuit | |
| EP2207101A1 (en) | Method and device for parallel interfacing | |
| CN105116975A (en) | Computer onboard hard disk and implementation method thereof | |
| CN104038719A (en) | Video frame-based ultrahigh-definition video display system and method | |
| CN107682655A (en) | A kind of fast conversion method of video data to AXI_Stream bus data streams | |
| US20060182149A1 (en) | Method and system for mobile multimedia processor supporting rate adaptation and mode selection | |
| CN101635136A (en) | Method and system for controlling low-speed display screen | |
| TW201403605A (en) | Method and apparatus for reading NAND flash memory | |
| CN100343778C (en) | Transferring data between differently clocked busses | |
| US20060182150A1 (en) | Method and system for deglitching in a mobile multimedia processor | |
| KR100489719B1 (en) | A specialized memory device | |
| CN110633233A (en) | DMA data transmission processing method based on assembly line | |
| US10013046B2 (en) | Power management techniques | |
| CN107948747A (en) | Method for managing power supply and unit, television set | |
| US20150123977A1 (en) | Low latency and high performance synchronization mechanism amongst pixel pipe units | |
| CN203206392U (en) | High-definition video signal processing circuit structure | |
| CN204652526U (en) | A kind of video acquisition memory circuit based on FPGA | |
| CN205068363U (en) | Conversion IC who shows signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20100127 |