CN101630008A - Beam former based on field programmable gate array (FPGA) and sparse energy converter planar array - Google Patents

Abstract

The invention discloses a beam former based on a field programmable gate array (FPGA) and a sparse energy converter planar array, comprising a sparse energy converter planar array, an analog adjusting circuit, an analog-to-digital conversion chip and an FPGA chip, wherein the sparse energy converter planar array is used for converting a seabed sonar echo signal into a weak electric signal; the analog adjusting circuit is used for carrying out the signal adjustment of fixed gain magnification, time varying gain control, bandpass filtration and the like on the weak electric signal; and the analog-to-digital conversion chip is used for synchronously sampling the analog electric signal after signal adjustment and converting the analog electric signal into a digital signal; and the FPGA chip carries out beam forming calculation, carries out L point discrete Fourier transform on all sampling passages of the analog-to-digital conversion chip to obtain S<m, n>(1) and carries out multiplication accumulation operation on the discrete Fourier transform result S<m, n>(1). The invention can be applied to a phased array three-dimensional sonar image system with high resolution ratio, optimizes a beam forming algorithm and greatly reduces the multiplication accumulation calculation needed by a system and the system cost.

Description

Beam-former based on FPGA and sparse energy converter planar battle array

Technical field

The present invention relates to FPGA technology, seabed 3-D view sonar technique, is a kind of Beam-former based on FPGA and sparse energy converter planar battle array specifically.

Background technology

Wave beam forms and calculates is the signal processing mode a kind of commonly used in signal Processing field, handle at sonar signal, Radar Signal Processing, fields such as ultrasonic listening have very widely uses, but, often be difficult in actual applications large-scale wave beam is calculated owing to need the data volume of processing very big.Beamforming algorithm need be done takes advantage of that to add number of times more, and the ability that Beam-former carries out multiply-add operation directly has influence on the overall performance of system.

The energy converter planar battle array that satisfies a certain size be high resolving power phased array 3-D view sonar system must possess: produce in order to stop big secondary lobe, it is the essential condition that satisfies that the half-wavelength spacing is structured the formation; In order to obtain certain longitudinal frame, then need one than larger area face battle array.The half-wavelength of high-resolution phased array 3-D view sonar system structure the formation require and the requirement of high longitudinal frame make construct the required two dimensional surface transducer array of this type systematic by several thousand in addition up to ten thousand transducers form.

Beam-former in the past uses general processor and digital signal processor usually, and (DigitalSignal Processor DSP) realizes.Advantages such as that general processor and DSP possess skills is comparatively ripe, implementation tool is perfect, programming is simple, but owing to the restriction of its inner structure the buffer memory phenomenons such as (Cache Miss) of failing to get or achieve what one wants occurs through regular meeting when calculating, influence the system-computed performance.10%～33% of its peak value calculated performance can only be maintained based on the lasting usually calculated performance of the design of general processor and DSP technology, very high calculated performance can't be obtained.

The FPGA technology has obtained develop rapidly in recent years, can be towards the compute-intensive applications of complexity from changing into towards the application that pure logic substitutes at first.In the FPGA device of up-to-date release, not only be integrated with abundant configurable logic block resource (Configurable Logic Block, CLB), (BlockRAM is BRAM) with the RocketIO GTP transceiver unit that is used for high-speed serial communication also to comprise a large amount of DSP unit towards the computation-intensive application, block RAM.For making things convenient for the debugging of FPGA, each FPGA manufacturer has also released logic analysis testing tool (as the ChipScope of Xilinx company) in the sheet, in the feasibility that has guaranteed to realize high-performance calculation on the software and hardware on FPGA simultaneously.

Using FPGA to realize that wave beam forms this field of calculating and also is in the starting stage at present, some achievements that had also are that the wave beam based on FPGA is formed the pilot study of calculating, same at present to the framework of sparse battle array in the high-resolution 3-D view sonar system with adopt the pilot study stage that also is in, for large-scale wave beam form calculate not one can the actual scheme of using.

Summary of the invention

The invention provides a kind of Beam-former based on FPGA and sparse energy converter planar battle array.

A kind of Beam-former based on FPGA and sparse transducer array, this Beam-former comprises sparse transducer array, simulated modulation circuit, modulus conversion chip (ADC) and fpga chip;

The transducer planar array that described sparse energy converter planar battle array is a circular edge is used for the bottom mounted sonar echoed signal is changed, and is faint electric signal with the sonar echo conversion of signals;

Described modulus modulate circuit is faint electric signal to be carried out signal conditions such as fixed gain amplification, time-varying gain (Time Variant Gain) control and bandpass filtering;

Described modulus conversion chip (ADC) is that the analog electrical signal behind the signal condition is carried out synchronized sampling, and is translated into digital signal;

Digital signal after described fpga chip is changed ADC is carried out beamforming algorithm.

A kind of Beam-former based on FPGA and sparse transducer array, the processing procedure of this Beam-former is:

(a). the energy converter planar battle array converts the bottom mounted sonar echoed signal that receives to faint electric signal;

(b). modulate circuit carries out signal conditions such as fixed gain amplification, time-varying gain (TVG) control and bandpass filtering to the transducer electrical signal converted;

(c). the analog electrical signal after multi-disc ADC chip is nursed one's health signal conditioning circuit carries out synchronized sampling.FPGA controls simultaneously to multi-disc ADC chip, and multi-disc ADC chip carries out synchronous acquisition to a plurality of data channel, and is translated into digital signal;

(d) digital signal after the .FPGA chip is changed ADC is carried out wave beam by beamforming algorithm and is formed calculating.

Digital signal after described fpga chip is changed modulus conversion chip is carried out wave beam formation calculating by beamforming algorithm and be may further comprise the steps:

Respectively all sampling channels of modulus conversion chip are tried to achieve S with the conversion of L point discrete Fourier _{M, n}(l); S _{M, n}(l) frequency-domain expression of expression sampled data, l is a frequency indices number, and L is counting of discrete Fourier transform (DFT), and 24 DFT in the specific embodiment are exactly L=24.Wherein, S _{M, n}(t) the time domain expression formula of expression sampled data.

Described S _{M, n}(l) by the sampled data stream S of echoed signal _{M, n}(k) try to achieve through following discrete Fourier transform (DFT) formula (1):

$S_{m,n}\left(l\right)=\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}{S}_{m,n}\left(k\right)\exp (-j\frac{2\mathrm{\&pi;}}{L}k\&times;l)......\left(1\right)$

F in the formula _sBe the sample frequency of system, m and n represent the row of transducer in sparse battle array number and row number, f respectively _kBe the centre frequency of echoed signal, l is a frequency indices number, is calculated by formula (2);

l＝(f _k×L)/f _s......(2)

(c). to discrete Fourier transform (DFT) as a result through type (3) carry out the multiply accumulating computing;

$B(l,p)=\underset{m=1}{\overset{M}{\mathrm{\&Sigma;}}}\underset{n=1}{\overset{N}{\mathrm{\&Sigma;}}}{S}_{m,n}\left(l\right)\exp (-j({\mathrm{\&psi;}}_x(m,n,p)+{\mathrm{\&psi;}}_y(m,n,p)))......\left(3\right)$

Phase shift parameters (ψ wherein _x(m, n, p) and ψ _y(m, n, p)) can pass through call number m respectively, n and p read from the internal memory of fpga chip, and wherein m and n represent the row of transducer in sparse matrix number and row number respectively, and M and N represent the line number and the columns of sparse matrix respectively, 1≤m≤, 1≤n≤N, p represent beam direction number.

The present invention adopts sparse energy converter planar battle array, the calculated amount of the beamforming algorithm of Jiang Diing can be applied to high-resolution phased array three-dimensional sonar picture system greatly, and beamforming algorithm is optimized, significantly reduce the calculated amount of the required multiply accumulating of system, reduced system cost.

Description of drawings

Fig. 1 is the synoptic diagram of the sparse transducer array that adopts in the preferred embodiment of the present invention;

Fig. 2 is the inner structure schematic block diagram that the present invention is based on the Beam-former of FPGA and sparse transducer array;

Fig. 3 is a FPGA inner function module synoptic diagram of the present invention;

Fig. 4 is the schematic process flow diagram of Beam-former of the present invention.

Embodiment

Preferred embodiment of the present invention is executed in the example, adopts the echoed signal centre frequency of 300kHz, the sample frequency of the analog to digital converter of 900kHz, and the Fourier transform of FPGA the inside adopts 24 DFT computings.

As shown in Figure 1, preferred embodiment of the present invention is executed the synoptic diagram of the sparse transducer array that adopts in the example, adopt 317 array elements, each array element is a transducer, the position of each some expression transducer among Fig. 1, x axle and y axle are represented the seat label of transducer: to the 12nd row, the transducer number is 60 from the 1st row; To 24 row, the transducer number is 100 from the 13rd row; To the 36th row, the transducer number is 108 from the 25th row; To the 48th row, the transducer number is 49 from the 37th row.The energy converter planar battle array that satisfies a certain size be high resolving power phased array 3-D view sonar system must possess, if structure the formation by complete matrix, the product by the greatest measure of x among Fig. 1 and y can obtain 2304 transducer array elements of these specific embodiment needs.By formula (3) as can be known, the calculated amount of beamforming algorithm is directly proportional with the quantity of array element.The sparse employing of structuring the formation of 317 array elements, the calculated amount of the beamforming algorithm that significantly reduces.

As shown in Figure 2, a kind of inner structure schematic block diagram of the Beam-former based on FPGA and sparse transducer array, concrete steps comprise:

I. transducer 210 converts the bottom mounted sonar echoed signal that receives to faint electric signal;

Ii. 220 pairs of transducer electrical signal converted of modulate circuit are carried out signal conditions such as fixed gain amplification 221, time-varying gain (TVG) control 222 and two rank bandpass filterings 223, wherein the gain of time-varying gain control 222 is that this magnitude of voltage is to export to analog-digital chip (DAC) 224 by numerical value in the fpga chip 240 to be converted to by the magnitude of voltage decision of an analog level;

Iii. multi-disc ADC chip 230 is that the analog electrical signal behind the signal condition is carried out synchronized sampling, is converted into digital signal;

Digital signal after 230 conversions of 240 couples of multi-disc ADC of iv.FPGA chip chip is carried out beamforming algorithm.

As shown in Figure 3, FPGA inner function module synoptic diagram, its step of carrying out beamforming algorithm is:

(1) in the Ad_ctrl module, the signal that 40 ADC driver modules are 310 pairs 317 tunnel carries out synchronized sampling, wherein per 8 the tunnel selects 1 shunt 311 by 4, and sampled result is stored in 40 dual port RAMs 312;

(2) in the Dft module, 4 10 sampled datas of selecting 1 shunt 320 will be stored in the dual port RAM 312 are read, and give 4 24 DFT computing modules 321 respectively, and result of calculation is stored in the dual port RAM 322;

(3) in the Beamforming module, fixed point Complex multiplication totalizer 330 reads the result from storage DFT result's dual port RAMs 322, and reads phase shift parameters from the ROM module 331 of FPGA inside, and DFT result and the phase shift parameters Complex multiplication of fixing a point is added up;

(4) in the Tx module, Data Receiving also transforms format module 340 and receives 330 multiply accumulating result, and the result after will transforming is stored in the dual port RAM 341, and sending module 342 is read the result in the dual port RAM 341, and sends host computer to the form of differential clocks, differential data.

As shown in Figure 4, the flow process of Beam-former operation is as follows:

1) Beam-former powers on or resets, and this moment, Beam-former was in idle condition.

2) after Beam-former receives the order of " beginning to calculate ", the fpga chip of Beam-former is to built-in variable (the call number m of phase shift parameters, n and p) carry out initialization, with the scratchpad zero clearing, and the TVG parameter is set, and (FPGA will be stored in the initial TVG value of FPGA memory headroom and issue DAC224, DAC224 is converted into analog level with this initial value, control TVG222).

3) after the Beam-former initialization was finished, the signal of FPGA control multi-disc ADC chip after to the conditioning processing of circuit sampled, and sampled data is carried out beamforming algorithm.

4) result to beamforming algorithm carries out data transmission, sends to host computer, receives the control signal of host computer simultaneously.Be " finishing calculating " order if received the control signal of host computer this moment, then Beam-former enters idle condition, " finish calculating " as if the control signal of also confiscating host computer and order, then proceed signal sampling and wave beam computing, until receiving " finishing calculating " order.

Claims (5)

1. the Beam-former based on FPGA and sparse energy converter planar battle array is characterized in that: comprise sparse transducer planar array (210), simulated modulation circuit (220), modulus conversion chip (230) and fpga chip (240);

Described sparse energy converter planar battle array (210) is used for the bottom mounted sonar echoed signal is changed, and is faint electric signal with the sonar echo conversion of signals;

Described modulus modulate circuit (220) is used for faint electric signal is carried out fixed gain amplification, time-varying gain control and bandpass filtered signal conditioning;

Described modulus conversion chip (230) is used for the analog electrical signal behind the signal condition is carried out synchronized sampling, and is translated into digital signal;

Digital signal after described fpga chip (240) is changed modulus conversion chip (230) is carried out wave beam by beamforming algorithm and is formed calculating.

2. Beam-former as claimed in claim 1 is characterized in that, described sparse energy converter planar battle array (210) is the transducer planar array of a circular edge.

3. Beam-former as claimed in claim 1 is characterized in that, the digital signal after fpga chip (240) is changed modulus conversion chip is carried out wave beam formation calculating by beamforming algorithm and be may further comprise the steps:

(a). respectively all sampling channels of modulus conversion chip are tried to achieve S with the conversion of L point discrete Fourier _{M, n}(l);

Described S _{M, n}(l) by the sampled data stream S of echoed signal _{M, n}(k), try to achieve through following discrete Fourier transform (DFT) formula (1):

$S_{m,n}\left(l\right)=\underset{k=0}{\overset{L-1}{\mathrm{\&Sigma;}}}{S}_{m,n}\left(k\right)\exp (-j\frac{2\mathrm{\&pi;}}{L}k\&times;l)...\left(1\right)$

F in the formula _sBe the sample frequency of system, m and n represent the row of transducer in sparse battle array number and row number, f respectively _kBe the centre frequency of echoed signal, l is a frequency indices number, is calculated by formula (2);

l＝(f _k×L)/f _s?……(2)

(b). to discrete Fourier transform (DFT) as a result through type (3) carry out the multiply accumulating computing;

$B(l,p)=\underset{m=1}{\overset{M}{\mathrm{\&Sigma;}}}\underset{n=1}{\overset{N}{\mathrm{\&Sigma;}}}{S}_{m,n}\left(l\right)\exp (-j({\mathrm{\&psi;}}_x(m,n,p)+{\mathrm{\&psi;}}_y(m,n,p)))...\left(3\right)$

Phase shift parameters (ψ wherein _x(m, n, p) and ψ _y(m, n, p)) can pass through call number m respectively, n and p read from the internal memory of fpga chip inside, and wherein m and n represent the row of transducer in sparse matrix number and row number respectively, and M and N represent the line number and the columns of sparse matrix respectively, 1≤m≤, 1≤n≤N, p represent beam direction number.

4. Beam-former as claimed in claim 1 is characterized in that: multiplying adopts the DSP unit of FPGA inside to realize in the described beamforming algorithm.

5. Beam-former as claimed in claim 1 is characterized in that: described sparse energy converter planar battle array is 317 array elements, and each array element is a transducer, and wherein the 1st row is to the 12nd row, and the transducer number is 60; To 24 row, the transducer number is 100 from the 13rd row; To the 36th row, the transducer number is 108 from the 25th row; To the 48th row, the transducer number is 49 from the 37th row.

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