CN101621083B - Semiconductor solar cells having front surface electrodes and method for manufacturing the same - Google Patents

Semiconductor solar cells having front surface electrodes and method for manufacturing the same Download PDF

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CN101621083B
CN101621083B CN2009101393825A CN200910139382A CN101621083B CN 101621083 B CN101621083 B CN 101621083B CN 2009101393825 A CN2009101393825 A CN 2009101393825A CN 200910139382 A CN200910139382 A CN 200910139382A CN 101621083 B CN101621083 B CN 101621083B
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electrode
layer
conductivity type
groove
solar cell
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CN101621083A (en
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金允基
金相澔
李斗烈
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from US12/437,583 external-priority patent/US20090283145A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
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Abstract

The invention provides semiconductor solar cells having front surface electrodes and method for manufacturing the same. Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench.

Description

Has semiconductor solar cell of front surface electrode and forming method thereof
Technical field
The present invention relates to solar cell and forming method thereof, more specifically, relate to semiconductor solar cell and forming method thereof.
Background technology
Solar cell is solar energy (for example sunlight) to be converted to the device of electricity.Solar cell has many application.Single battery can be used for to the midget plant energy supply, and the battery (for example, photovoltaic array) of large array can be for generation of a kind of renewable energy, and this renewable energy is in the situation that can not obtain being particularly useful from the electric energy of electrical network (power grid).Solar battery array is also developed the electric power system (grid-based electrical system) that is used for based on grid now.
Solar cell incides the photon of substrate by response the middle electron-hole pair that produces of substrate (for example semiconductor substrate) that is absorbed in comes work.When photon was absorbed, its energy was passed to the electronics in the lattice of substrate.Usually, this electronics is in the valence band of lattice and be strapped in tightly in covalent bond between adjacent atom.The energy of being passed to electronics by photon can enough be used for exciting electronic in the conduction band of lattice, and then this electronics becomes and moves freely in substrate in conduction band.Electronics is that its a part of covalent bond has lacked an electronics now before, and it is called as " hole ".The existence of the covalent bond that lacks allows to be somebody's turn to do " hole " from the bound electron immigration of adjacent atom, and the back stays another hole, and the hole can be moved at whole lattice by this way.Then this in substrate of electronics and hole moves the direct voltage that can be used for setting up through the load that be connected to solar cell.
Particularly, be created in internal electric field in p-n junction and can cause enough that the electronics of electron-hole centering and hole move to N-shaped semiconductor region and p-type semiconductor region respectively.Use p-n junction and disclosed in United States Patent(USP) Nos. 4726850 and 4748130 in an example of the solar cell of the electrode pair on the apparent surface of semiconductor substrate.Another example of solar cell is called in the U.S. Patent No. 7335555 of " Buried-Contact Solar Cell With Self-Doping Contacts (contact solar cell of burying with autodoping contact) " disclosed in the people such as Gee, name.
Summary of the invention
Comprise substrate according to the solar cell of the embodiment of the present invention, the light that this substrate has is thereon collected surface and the P-N rectifying junction in substrate.The P-N rectifying junction comprises: the base of the first conductivity type (for example p-type) and the semiconductor layer of collecting the second conductivity type that extends between the surface at base and light.Also arrange and extend through semiconductor layer and to enter groove in the base.The first electrode and the second electrode adjacent light are collected the surface and are arranged.The first electrode is conductively coupled to semiconductor layer, and the second electrode is conductively coupled to the base in the position of adjacent trenches bottom.
According to additional embodiment of the present invention, solar cell can also comprise the electric insulation trench sidewall spacer thing on trenched side-wall, and it extends between the semiconductor layer of the second electrode and the second conductivity type and provides electricity between the two to isolate.In addition, the semiconductor layer of the second conductivity type can be to have the amorphous silicon layer of different band gap with respect to monocrystalline silicon.Particularly, the semiconductor layer of the second conductivity type can be the amorphous silicon layer that forms heterojunction in substrate.The boundary layer that can also comprise the second conductivity type according to the solar cell of these embodiment, it extends between the semiconductor layer of the second conductivity type and base.The boundary layer of the second conductivity type can form with the semiconductor layer of the second conductivity type non-rectification heterojunction and form the P-N rectifying junction with the base.
Embodiments of the invention also are included in light and collect lip-deep anti-reflecting layer.Light is collected the surface and can be configured to have with the peak of localization and the heterogeneous surface profile of paddy.Particularly, non-rectification heterojunction can have the non-planar junction profile, and light is collected the surperficial heterogeneous surface profile that can have close to the non-planar junction profile of non-rectification heterojunction.And non-rectification heterojunction can have the first non-planar junction profile, and the rectifying junction between boundary layer and base can have the second non-planar junction profile close to the shape of the first non-planar junction profile.
Additional embodiment of the present invention comprises the method that forms solar cell.Some in these methods are included in the upper semiconductor layer that forms the second conductivity type (for example N-shaped) of semiconductor substrate (base that wherein has the first conductivity type (for example p-type)).Also form the first groove, it extends through the semiconductor layer of the second conductivity type and enters in the base.The step that forms the first groove can form the step of anti-reflecting layer on the semiconductor layer of the second conductivity type after.The trench sidewall spacer thing is formed on the sidewall of the first groove.Also form the second groove, it extends through the stepping of going forward side by side of the first channel bottom and enters in the base.The first groove and the second groove can be the strip-shaped grooves that extends past substrate.The second groove is filled with the first electrode, and the first electrode is conductively coupled to the base.Fill the step of the second groove can be in the bottom that the first type conductivity dopant is injected into the second groove and sidewall after.The second electrode can also form with the semiconductor layer of the second conductivity type and contact.The second electrode can be formed on the outside and/or inner of the first groove.
According to some in these embodiments of the method, the step that forms the first groove can form the step in boundary layer of the second conductivity type in the base after.Thereby the boundary layer can be transformed into clean the second conductivity type from the first conductivity type by the part that will be diffused into from the second type conductivity dopant of the q.s of semiconductor layer in the base the base.The boundary layer can form non-rectification heterojunction with semiconductor layer, and this semiconductor layer can comprise amorphous silicon.Semiconductor layer can form by the in-situ doped amorphous silicon layer of deposition on the surface of substrate.This surface can have the surface profile heterogeneous Feng Hegu of localization (wherein with).
The method of the formation solar cell of additional embodiment comprises that the surface texturizing (texturize) of the silicon wafer that makes the base with first conductivity type is to produce the Feng Hegu of localization in the surface according to the present invention.After veining of surface, the in-situ doped amorphous silicon layer of the second conductivity type can deposit on the surface of veining, thereby definition has the non-rectification heterojunction of this surperficial veining.Amorphous silicon layer can have therein approximately 1 * 10 19cm -3To approximately 1 * 10 21cm -3Doping content in scope.Then, thereby be transformed into clean the second conductivity type by the part that will be diffused into from the second type conductivity dopant of the q.s of amorphous silicon layer in the base the base from clean the first conductivity type, the boundary layer of the second conductivity type is formed in the base.Then form groove, this groove extends through amorphous silicon layer and boundary layer and enters in the base.Also form the first electrode and the second electrode.The first electrode is conductively coupled to amorphous silicon layer, and the second electrode adjacent trenches bottom electrical is couple to the base.Some in these embodiment of the present invention, the step that forms the first electrode and the second electrode is included in bottom deposition second electrode of groove and adjacent trenches top deposition the first electrode after the electricity consumption dielectric spacer layer covers the second electrode.
Some according to the embodiments of the invention, the step of veining comprise that being exposed to by the surface with silicon wafer the etchant that causes on this surface forming residue comes the etching should the surface, and it is as further etched localization etching mask.Particularly, the step of surface texturizing can be comprised the surface is exposed to the dry ecthing agent that contains chlorine and fluorine.Particularly, the dry ecthing agent can be passed through chlorine (Cl 2), oxygen (O 2) and SF 6Source gas mixes in low pressure process chamber and forms.
According to additional embodiment of the present invention, the step that forms the boundary layer comprises by the amorphous silicon layer of the second conductivity type is formed at about 500 ℃ of annealing temperatures in the about scope between 900 ℃ having from approximately
Figure G2009101393825D00031
Arrive approximately
Figure G2009101393825D00032
The boundary layer of the preferred thickness in scope.And the step that forms groove can comprise by form a plurality of right-angled intersections (criss-crossing) groove in the surface of silicon wafer and forms latticed groove.Latticed groove can also comprise the outermost annular groove of adjacent silicon wafer periphery.Can also be after forming the step of the first electrode, the part of the part of the first electrode and following electric insulation wall in the selective removal ring-shaped groove, thus expose the second electrode.
Description of drawings
Fig. 1 is the sectional view according to the integrated circuit solar cell of the embodiment of the present invention;
Fig. 2 is the amplification sectional view of ledge of the solar cell of Fig. 1;
Fig. 3-9th, the sectional view of structure between two parties, it is combined the method that forms according to the integrated circuit solar cell of the embodiment of the present invention that illustrates with Fig. 1;
Figure 10 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 10 B is that the integrated circuit solar cell I-I ' along the line of Figure 10 A cuts open the sectional view of getting;
Figure 11 is the amplification sectional view of ledge of the solar cell of Figure 10 B;
Figure 12 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 12 B is that the I-I ' along the line of the integrated circuit solar cell of Figure 12 A cuts open the sectional view of getting;
Figure 12 C is the alternative cross sections figure of I-I ' along the line of the integrated circuit solar cell of Figure 12 A;
Figure 13 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 13 B is that the I-I ' along the line of the integrated circuit solar cell of Figure 13 A cuts open the sectional view of getting;
Figure 14 A-20A is the plane graph of structure between two parties, and it illustrates the method that forms according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 14 B-20B is that the I-I ' along the line of the structure between two parties of Figure 14 A-20A cuts open the sectional view of getting;
Figure 21 A-23A is the plane graph of structure between two parties, and it illustrates each method by the integrated circuit solar cell shown in Figure 12 A and 12C that forms according to the embodiment of the present invention;
Figure 21 B-23B is that the I-I ' along the line of the structure between two parties of Figure 21 A-23A cuts open the sectional view of getting;
Figure 24 A-25A is the plane graph of structure between two parties, and it illustrates each method that forms according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 24 B-25B is that the I-I ' along the line of the structure between two parties of Figure 24 A-25A cuts open the sectional view of getting;
Figure 26 is the block diagram that can use according to the photovoltaic system of the integrated circuit solar cell of the embodiment of the present invention;
Figure 27 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 27 B is that the I-I ' along the line of the solar cell embodiment of Figure 27 A cuts open the sectional view of getting.
Figure 28 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 28 B is that the I-I ' along the line of the solar cell embodiment of Figure 28 A cuts open the sectional view of getting;
Figure 29 A is the sectional view according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 29 B is that the I-I ' along the line of the solar cell embodiment of Figure 29 A cuts open the sectional view of getting;
Figure 30 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 30 B is that the I-I ' along the line of the solar cell embodiment of Figure 30 A cuts open the sectional view of getting;
Figure 31 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 31 B is that the I-I ' along the line of the solar cell embodiment of Figure 31 A cuts open the sectional view of getting;
Figure 32 A is the plane according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 32 B is that the I-I ' along the line of the solar cell embodiment of Figure 32 A cuts open the sectional view of getting;
Figure 33 is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 34 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 34 B is that the I-I ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting;
Figure 34 C is that the II-II ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting;
Figure 35 is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 36 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 36 B is that the I-I ' along the line of the solar cell embodiment of Figure 36 A cuts open the sectional view of getting;
Figure 37 A is the plane graph according to the integrated circuit solar cell of the embodiment of the present invention;
Figure 37 B is that the I-I ' along the line of the solar cell embodiment of Figure 37 A cuts open the sectional view of getting.
Embodiment
Now with reference to accompanying drawing, the present invention is described more fully, shown in the drawings of the preferred embodiments of the present invention.Yet the present invention can should not be construed as limited to example embodiment described herein with multiple different forms enforcement; On the contrary, it is in order to make the disclosure thoroughly and complete that these embodiment are provided, and scope of the present invention is fully conveyed to those skilled in the art.Identical Reference numeral refers to identical element all the time, holding wire with and on signal can represent with identical reference symbol.
Should be understood that, in specification when claim layer (or a film) " " another layer or substrate " on " time, can directly on another layer or substrate, perhaps can also there be the layer of insertion in it.And in the accompanying drawings, in order to be shown clearly in, the size in layer and zone can be exaggerated.In addition, be used for describing the different zone of different embodiments of the invention and layer as the word of " first ", " second " and " the 3rd ", these zones and layer are not limited to these words.These words only are used for a zone or layer and another zone or layer differentiate.Therefore, the layer that is called as in one embodiment " ground floor " can be called " second layer " in another embodiment.
Referring now to Fig. 1-2, can comprise the substrate with upper surface and basal surface according to the solar cell of the embodiment of the present invention, upper surface represents that light collects the surface, basal surface and upper surface relatively extend.Substrate is depicted as and comprises semiconductor substrate region 110, and it can adulterate with the first type conductivity dopant (for example p-type dopant).Particularly, substrate zone 110 can be initially the p-type silicon single crystal wafer, and it can stand by the semiconductor processes step shown in the Fig. 3 that will be described below-9.Substrate can also be included in the semiconductor layer 120 of the second conductivity type (for example N-shaped) that extends on substrate zone 110.The upper surface of the semiconductor layer 120 of the second conductivity type can be collected the surface as light, and anti-reflecting layer 131 can be formed on light and collect on the surface.The purpose of anti-reflecting layer 131 can be that the light collection efficiency etc. of increase is provided by reducing reflection that incident light collects the surface away from light.
Specifically illustrate as Fig. 2 (it has been given prominence to by the zone shown in Fig. 1 " A "), substrate zone 110 comprises base (base region) 110b of clean the first conductivity type (for example p-type) and the boundary layer 110a of clean the second conductivity type, and boundary layer 110a and base 110b form the P-N rectifying junction.Describe more fully as following, this boundary layer 110a can form by the dopant (for example N-shaped dopant) of q.s is diffused into base 110b from the semiconductor layer 120 of the second conductivity type, thereby the part of base 110b is transformed into clean the second conductivity type from the first conductivity type.
The semiconductor layer 120 of boundary layer 110a and the second conductivity type can form the conduction region 122 of the second conductivity type jointly.In addition, the semiconductor layer 120 of the second conductivity type can form amorphous silicon layer, and itself and boundary layer 110a form non-rectification heterojunction.Thereby can be captured by increasing near the wave-length coverage that produces electron-hole pair the P-N knot, can be conducive to support higher light collection efficiency with respect to this heterojunction of homojunction.Semiconductor layer 120 can be relatively high doped layer, and for example it can form have the second conductivity type in-situ doped semiconductor layer of (for example phosphorus), and wherein doping content is approximately 10 19cm -3To approximately 10 21cm -3In scope.The thickness of boundary layer 110a is chosen as the compound solar battery efficiency that increases of electron-hole of not expecting by reducing near the P-N knot.Although do not wish by any theory constraint, but thick not boundary layer 110a can with the electron-hole multiple correlation of relative elevation degree, the compound boundary defect by the heterojunction place between the semiconductor layer 120 of boundary layer 110a and the second conductivity type of this electron-hole causes.Alternatively, blocked up boundary layer 110a can be by relatively high electron-hole Mixed Circumscription, and this electron-hole is compound to be caused through the wide depletion region around the P-N knot by excessive charge carrier drift (namely migration).Consider for given semi-conducting material, to have from approximately based on these Arrive approximately
Figure G2009101393825D00062
The boundary layer 110a of the thickness in scope can be by reducing the compound light collection efficiency of supporting high level of electron-hole wherein.
Anti-emission layer 131 (it can be deposited on the semiconductor layer 120 of the second conductivity type) thus the thickness that can have about λ/4 increases efficiency of light absorption, wherein λ will be incident on light during solar cell working to collect lip-deep expectation light wavelength.And anti-reflecting layer 131 can form sandwich construction, for example comprises the layer of silicon oxide layer and silicon-nitride layer.Except increasing the light collection efficiency of solar cell, anti-reflecting layer 131 can also for the protection of and provide electric passivation (electrical passivation) to collect the surface to the following light of solar cell.
Also with reference to Fig. 2, light is collected surface (its be depicted as the semiconductor layer 120 of the second conductivity type and the interface between anti-reflecting layer 131) can be configured to have surface profile heterogeneous, has the Feng Hegu of localization in surface profile.This heterogeneous surface profile can show as the projection at a plurality of isolated Pyramids shown in the surface of anti-reflecting layer 131.Particularly, can have the non-planar junction profile at the semiconductor layer 120 of the second conductivity type and the non-rectification heterojunction between the 110a of boundary layer, light is collected the surperficial heterogeneous surface profile that can have close to the non-planar junction profile of non-rectification heterojunction.And non-rectification heterojunction can have the first non-planar junction profile, and the rectifying junction between boundary layer 110a and base 110b can have the second non-planar junction profile close to the shape of the first non-planar junction profile.
The solar cell of Fig. 1 comprises that also being arranged on light collects lip-deep electrode pair.This electrode pair is depicted as the first electrode 141 (it is conductively coupled to base 110b) and the second electrode 143 (it is conductively coupled to the semiconductor layer 120 of the second conductivity type).These electrodes can be the strip shaped electric poles with relatively narrow width, and it has reduced shade (shading) loss of collecting the surface at light.The first electrode 141 and the second electrode 143 can be formed by at least a metal of the group of selecting free aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) to form.Electrode 141 and 143 can also comprise metal silicide layer and/or multi-layer conductive for example Ti/TiN/Al or Ti/TiN/W.
Groove 116 can also be set, and it extends through the semiconductor layer 120 of the second conductivity type and enters base 110b.Explain more fully as following, groove 116 can be formed by upper strip-shaped grooves 113 and lower strip-shaped grooves 114, and this time strip groove 114 extends through the bottom of groove 113.Lower groove 114 for example can have from about 0.3 micron width in about 1 micrometer range, and has strip or the analogous shape that extends past substrate.The sidewall of upper groove 113 can fitted lining have electric insulation sidewall spacer 115, and it can for example form oxide and/or insulating nitride layer.These sidewall spacers 115 play the effect that the first electrode 141 is electrically insulated from the semiconductor layer 120 of the second conductivity type.And the relatively highly doped impurity range 117 of the first conductivity type can be formed in the sidewall of lower groove 114 and bottom to reduce the series resistance between the first interior electrode 141 of base 110b and lower groove 114.Impurity range 117 can for example have the approximately thickness of 0.3 micron.As shown in the figure, relatively shallow groove/recess 118 can also be formed in semiconductor layer 120 and with the second electrode 143 and fill.
Fig. 3-9 show other embodiments of the invention, and it comprises the method for the solar cell that forms Fig. 1-2.As shown in Figure 3, these methods can be included in the optional step in back of the body surface field (BSF) district 111 that forms the first conductivity type (for example P type) in the semiconductor substrate 110 of the first conductivity type (for example P type wafer), the formation in the back of the body surface field (BSF) of the first conductivity type district 111 is by the relative front surface that the first type conductivity dopant (for example boron (B)) is injected substrate 110 and back of the body surface, thereby then heat treatment substrate 110 advances the dopant that injects.After this, as shown in Figure 4, the front surface of substrate 110 can become uneven by producing therein a plurality of peaks and paddy.These peaks in front surface are shown as has pyramid or similar structures 112, and can use conventional art to form, for example plasma etching, mechanical scribing (mechanical scribing), photoetching and chemical etching.For example, the oxide layer (not shown) can form the sacrifice layer on the front surface of substrate 110, and then the photoresist layer (not shown) with patterning comes lithographic patterning as etching mask.Then the front surface of substrate 110 can come etched as etching mask with the sacrifice layer of patterning.During this technique, any BSF district 111 on the front surface of substrate 110 typically is removed.
Referring now to Fig. 5, noncrystal semiconductor layer 120 is formed on the front surface of injustice of substrate 110.This noncrystal semiconductor layer 120 can be clean the second conductivity type (for example N-type) highly doped (for example in-situ doped) layer.Particularly, the second conductivity type doping content in noncrystal semiconductor layer 120 can be from approximately 1 * 10 19cm -3To approximately 1 * 10 21cm -3In scope.(it can have from about hundreds of dust to approximately noncrystal semiconductor layer 120 Thickness in scope typically is approximately
Figure G2009101393825D00082
) can use various technology to be deposited.These technology comprise plasma enhanced chemical vapor deposition (PECVD) or the low pressure chemical vapor deposition that uses silane and hydrogen.Particularly, in-situ doped noncrystal semiconductor layer 120 can use silane (SiH by chemical vapour deposition (CVD) 4), hydrogen phosphide (PH 3) and hydrogen formation.
Also with reference to Fig. 5, the boundary layer 110a of the second conductivity type forms by the second type conductivity dopant is diffused into substrate 110 from noncrystal semiconductor layer 120, thus definition boundary layer 110a, and the base 110b of boundary layer 110a and the first conductivity type forms the P-N rectifying junction.This diffusion of the second type conductivity dopant can be undertaken by substrate 110 is annealed.For by reducing the compound solar battery efficiency that increases of electron-hole do not expect near the P-N rectifying junction, annealing can be carried out enough duration in enough temperature and have from approximately with generation
Figure G2009101393825D00083
Arrive approximately
Figure G2009101393825D00084
The boundary layer 110a of the thickness in scope.According to some embodiment of the present invention, the unevenness on the surface of noncrystal semiconductor layer 120 can also increase by hemispherical silicon grain (HSG) layer of growing on noncrystal semiconductor layer 120, thereby increases the light collection efficiency of solar cell.Alternatively, the conductive euphotic zone (for example ZnO layer) that has a rough surface structure can be deposited on noncrystal semiconductor layer 120.
As shown in Fig. 6-7, then, anti-reflecting layer 131 is formed on noncrystal semiconductor layer 120.Anti-reflecting layer 131 can form by using conventional deposition processes (for example plasma activated chemical vapour deposition (PECVD)) one or more electric insulation layers (for example silicon dioxide, silicon nitride) to be deposited on the upper surface of noncrystal semiconductor layer 120.In order to increase efficiency of light absorption, anti-reflecting layer 131 can have the approximately thickness of λ/4, and wherein λ is incident on light to collect lip-deep expectation light wavelength during solar cell working.Then, can carry out lithographic definition etching step (for example dry etching) extends through noncrystal semiconductor layer 120 and boundary layer 110a and enters base 110b to define relatively narrow strip the first groove 113, the first grooves 113.In these embodiment of part of the present invention, strip the first groove 113 can have approximately 1 μ m or less width.For example, strip-shaped grooves can have the approximately width of 0.3 μ m.
Lateral wall insulation sept 115 is formed on the sidewall of the first groove 113.These lateral wall insulation septs 115 can form silicon dioxide layer or silicon-nitride layer or form the compound of a plurality of insulating barriers.Lateral wall insulation sept 115 can by with the electric insulation layer conformal deposited in the first groove 113 then anisotropy eat-back layer that (etch back) deposit until the bottom of the first groove 113 is exposed to form.This step of conformal deposited electric insulation layer can be included in deposition protection insulating barrier 132 on the basal surface of substrate 110.
Referring now to Fig. 8, use the first mask (not shown) and lateral wall insulation sept 115 as the bottom of further etching the first groove 113 of etching mask.This etching step causes the formation of extension groove 114, and extension groove 114 can extend in fact in base 110b.The common multistage groove 116 with the upper side wall that is covered by lateral wall insulation sept 115 that forms of the first groove and extension groove 114.Form the step of extension groove 114 and can be then form the step of relative highly doped impurity range 117 by Selective implantation the first type conductivity dopant (for example P type dopant) in the bottom of extension groove 114 and the sidewall.As shown in Figure 9, then carry out selective etch step with etching relatively shallow second groove 118, the second grooves 118 extend through anti-reflecting layer 131 and enter amorphous silicon layer 120 thereafter.The second groove 118 forms more shallow than P-N rectifying junction.Then, multistage groove 116 and the second groove 118 are filled with the first electrode 141 and the second electrode 143 respectively, as shown in Figure 1.These first electrodes 141 and the second electrode 143 can patterned metal layer forms by depositing then.At least a metal of selecting the group that metal level can be comprised of the silicide from aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and these metals forms.Particularly, according to some embodiment of the present invention, metal level can be Ti/TiN/Al or Ti/TiN/W layer.After forming these first electrodes 141 and the second electrode 143, can carry out the step of in hydrogeneous atmosphere, electrode being annealed.This hydrogen annealing can play the effect that activates N-type dopant in substrate, thereby improves electron mobility, can also eliminate the defective in substrate surface, thereby reduces the Leakage Current of duration of work.
Referring now to Figure 10 A-10B and Figure 11, the solar cell of additional embodiment is depicted as and is formed in semiconductor substrate 1110 (for example single crystal semiconductor (for example silicon) wafer) according to the present invention, and semiconductor substrate 1110 has the base 1111 of the first conductivity type (for example P type) therein.Highlight as the zone in Figure 10 B and Figure 11 " A ", substrate 1110 can comprise texturizing surfaces, and it is constructed to reflect to strengthen by reducing the incident light of collecting the surface away from the glazing of substrate 1110 light collection efficiency of solar cell.P-N rectifying junction with uneven profile is arranged between the boundary layer 1113 of base 1111 and the second conductivity type (for example N-type).(it can have therein from approximately 1 * 10 in boundary layer 1113 19cm -3To approximately 1 * 10 21cm -3Clean N-type doping content in scope) can be formed in base 1111 by making the second type conductivity dopant (for example phosphorus (the P)) diffusion from relatively highly doped semiconductor layer 1114 (for example N+ amorphous silicon layer).The thickness in boundary layer 1113 can be chosen as near the compound solar battery efficiency that increases of electron-hole of not expecting the P-N knot by reducing.
Although do not wish to be subject to any theory constraint, thick not boundary layer 1113 can and the electron-hole multiple correlation of relative elevation degree, the compound boundary defect by the heterojunction place between the semiconductor layer 1114 of boundary layer 1113 and the second conductivity type of this electron-hole causes.Alternatively, blocked up boundary layer 1113 can be by relatively high electron-hole Mixed Circumscription, and this electron-hole is compound to be caused by the excessive charge carrier drift (namely migration) of process around the wide depletion region of P-N knot.Based on these considerations, have from approximately
Figure G2009101393825D00101
Arrive approximately The boundary layer 1113 of the thickness in scope can be by reducing the compound light collection efficiency of supporting high level of electron-hole wherein.
And, thereby can be captured by increasing near the scope that produces the wavelength of electron-hole pair the P-N knot, the heterojunction between the semiconductor layer 1114 of boundary layer 1113 and the second conductivity type can be conducive to support higher light collection efficiency with respect to homojunction.Figure 10 A-10B and Figure 11 also show on the semiconductor layer 1114 of the second conductivity type and comprise anti-reflecting layer 1141.As explained above, anti-reflecting layer 1141 can have and the proportional thickness of incident light wavelength.For example, the thickness of λ/4 increases efficiency of light absorption thereby anti-reflecting layer 1141 can have approximately, and wherein λ is that the light that will be incident on solar cell is collected lip-deep expectation light wavelength.Anti-reflecting layer 1141 (anti-reflecting layer 1141 can form silicon oxide layer, silicon nitride layer or its multilayer) can also provide electricity for solar cell with passivation and the protection of physics.
Groove 1120 (it comprise two-dimensional array right-angled intersection groove 1121 and 1123 and outer ring-like " edge " groove 1125) be formed in substrate 1110.As shown in Figure 10 B (the solar cell I-I ' along the line of its presentation graphs 10A cuts open the sectional view of getting), groove 1120 extends semiconductor layer 1114 and the boundary layer 1113 of passing through anti-reflecting layer 1141, the second conductivity type fully.Groove 1121 and 1123 can have the width " W " of about 1 μ m or less (for example 0.3 μ m) to reduce the shadow loss of incident light, " but edge " groove 1125 enough wide (as shown in the figure, for example " Wa "＞" W ") to support low resistance contact and wire- bonded.Groove 1121 and 1123 should be slightly darker than the P-N rectifying junction between boundary layer 1113 and base 1111, thereby enough the contact of low resistance can be produced between trench electrode 1131,1131a and base 1111.
Illustrate best as Figure 10 B, the first conductivity type impurity region 1115 can use and select inject and the combination of dopant propelling (drive-in) technology and be arranged on bottom and the lower wall place of groove 1120.Impurity range 1115 typically has clean the first conductivity type doping content over the first conductivity type doping content in base 1111 therein.It will be understood by those skilled in the art that impurity range 1115 can play the effect that enhancing is distinguished from the back of the body surface field (BSF) of the electric current collection of base 1111.
Figure 10 A-10B also is illustrated on the front surface (namely light collect surface) of solar cell and comprises the first electrode and the second electrode.The first electrode 1131,1131a are depicted as the bottom of adjacent trenches 1120 and extend, and with impurity range 1115 and/or base 1111 ohmic contact.As shown in the figure, electric insulation layer 1135 (for example silicon dioxide) is arranged on the first electrode 1131,1131a is upper and in groove 1120, the second electrode 1133,1133a are arranged on electric insulation layer 1135.The second electrode 1133,1133a can form semiconductor layer 1114 ohmic contact with the second conductivity type, and can extend on the upper surface of anti-reflecting layer 1141.The width W 2 of the second electrode 1133 can be greater than groove 1121,1123 width " W ".The upper surface of electric insulation layer 1135 is below the interface between the semiconductor layer 1114 of boundary layer 1113 and the second conductivity type, as shown in figure 11.
As shown in Figure 10 A, can be fabricated into electrically contact (for example the passing through wire-bonded) of the first electrode 1131a in the periphery at rim openings 1119 places of contiguous semiconductor substrate 1110, and can be fabricated into electrically contacting of the second electrode 1133a (extending to the segmental arc around the periphery).Particularly, arc opening can be formed in the second electrode 1133a and following electric insulation layer 1135, thereby exposes the adjacent upper surface in the bottom with annular " edge " groove 1125 of the first electrode 1131a.
According to some embodiment of the present invention, the material of selecting the group that the first electrode 1131,1131a and the second electrode 1133,1133a can be comprised of the combination from aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal silicide and these electric conducting materials forms.For example, in certain embodiments of the present invention, the first electrode 1131,1131a and the second electrode 1133,1133a can form the compound of Ti/TiN/Al or Ti/TiN/W.Alternatively, the first electrode 1131,1131a can form the P type semiconductor electrode, and the second electrode 1133,1133a can form the N type semiconductor electrode.
The solar cell of further embodiment is illustrated by Figure 12 A-12C according to the present invention.Particularly, the solar cell embodiment of Figure 12 A-12B is similar to the solar cell embodiment of Figure 10 A-10B, but has revised the anti-reflecting layer 1141 of Figure 10 A-10B with respect to the position of the second electrode 1133.Particularly, as shown in Figure 12 A-12B, anti-reflecting layer 1141 can form blanket formula layer (blanket layer) with cover the second electrode 1133 (with boundary layer 1113) with respect to the peripheral edge of substrate 1110 part in inside.Alternatively, Figure 12 C illustrates embodiments of the invention, and it has the light transmission conductive layer 1137 that is arranged between anti-reflecting layer 1141 and boundary layer 1113, and light transmission conductive layer 1137 is arranged on semiconductor layer 1114.In this embodiment, the second electrode 1133 is patterned as on the upper surface that directly extends in light transmission conductive layer 1137.In this way, light transmission conductive layer 1137 can be as promoting the evenly conductive formation of expansion of electric current wherein, this electric current flow through (via the semiconductor layer 1114 of the second conductivity type, not shown) between the second electrode 1133 and boundary layer 1113.Light transmission conductive layer 1137 can form indium tin oxide (ITO) layer or zinc oxide (ZnO) layer, yet can also use other light transmissive material.The superficial makings of light transmission conductive layer 1137 can also be relatively coarse, thereby improves the light collection efficiency of solar cell.
According to other embodiments of the invention, the solar cell embodiment of Figure 10 A-10C can further be revised, as shown in the solar cell embodiment of Figure 13 A-13B.Particularly, the solar cell embodiment of Figure 13 A-13B comprises the second electrode 1133 of revising patterning, makes the upper surface of the second electrode 1133 and anti-reflecting layer 1141 at grade.This plane surface profile can realize itself and anti-reflecting layer 1141 coplines by planarization the second electrode 1133.And the marginal portion of the second electrode 1133 is set to annular and extends 1133b.Extend 1133b and defined circle the second marginal zone 1119b that locates in the periphery of semiconductor substrate 1110, the surface of the first electrode 1131b below circular the second marginal zone 1119b exposes.Circular the second marginal zone 1119b has the width less than width " Wa ".The exposed surface that annular is extended 1133b and following the first electrode 1131b is outer electrode (wire-bonded for example, not shown) contact point is provided, this outer electrode is fed to load (not shown) or photovoltaic system (seeing, for example Figure 26) with the electric current that the sun produces.
The method of the solar cell of formation additional embodiment according to the present invention is illustrated by Figure 14 A-20A and Figure 14 B-20B, and Figure 14 B-20B illustrates the sectional view that I-I ' along the line cuts open the structure between two parties of Figure 14 A-20A that gets.Particularly, Figure 14 A-14B illustrates on the base 1111 that boundary layer 1113 is formed on the first conductivity type (for example P type) and being combined to form on the base 1111 of the first conductivity type (for example P type) of semiconductor layer 1114 (for example highly doped amorphous silicon layer, not shown) of the boundary layer 1113 of the second conductivity type (for example N-type) and the second conductivity type in certain embodiments.The semiconductor layer 1114 of boundary layer 1113 and the second conductivity type can be with respect to Figure 10 A-10B and Figure 11 such as above-mentioned formation, thus definition P-N rectifying junction.As shown in figure 11, the first type surface of semiconductor substrate 1110 can have the surface profile of veining.
Referring now to Figure 15 A-15B, anti-reflecting layer 1141 is formed on boundary layer 1113, thereby increases the light collection efficiency of solar cell.Anti-reflecting layer 1141 (it can be silicon oxide layer, silicon nitride layer or their combination) for example can use, and the treatment process of plasma enhanced chemical vapor deposition (PECVD) forms.Anti-reflecting layer 1141 can also use conventional antireflection coating (ARC) layer to form.Figure 16 A-16B illustrates photoresist layer 1143 and is deposited on anti-reflecting layer 1141.Photoresist layer 1143 can be by lithographic patterning with definition opening 1143a and 1143b wherein.These openings can define the cross grid of intersection opening (intersecting opening), as shown in Figure 16 A.Photoresist layer 1143 can also be patterned to define ring edge opening 1119.
Referring now to Figure 17 A-17B, use patterning photoresist layer 1143 to select etching step to define groove array and the ring edge groove 1125 in semiconductor substrate 1110 as etching mask.These grooves are depicted as two-dimensional grid groove 1120 jointly.Particularly, a plurality of the first grooves 1121 and a plurality of the second groove 1123 (it forms the cross array (namely two-dimensional grid) of groove jointly) form and extend through anti-reflecting layer 1141 and boundary layer 1113 fully, and further extend in the base 1111 of the first conductivity type.According to some embodiment of the present invention, the degree of depth of groove can be approximately 2/3rds of the thickness of semiconductor substrate 1110.As above described about Figure 10 B, these grooves 1121 and 1123 can have the approximately Breadth Maximum of 1 μ m, but the typical case for example has the approximately narrower width of 0.3 μ m.
Figure 18 A-18B shows the formation with contiguous the first conductivity type impurity region 1115 of groove 1121,1123 and 1125 bottom.These impurity ranges 1115 can form as lower wall and the bottom that injecting mask injects grid groove 1120 with the first type conductivity dopant (for example boron) by the photoresist layer 1143 that uses anti-reflecting layer 1141 and/or patterning.According to some embodiment of the present invention, the injection of the first type conductivity dopant can be carried out with enough energy and dosage, to produce therein the impurity range 1115 that has the first higher type conductivity dopant concentration with respect to base 1111.Then this implantation step, blanket formula conductive layer (not shown) can be deposited on anti-reflecting layer 1141 and in grid groove 1120.The material of selecting the group that this blanket formula conductive layer can be comprised of the combination from aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal silicide and these electric conducting materials forms.Particularly, blanket formula conductive layer can form the compound of Ti/TiN/Al or Ti/TiN/W.Then this blanket formula layer is patterned to define the first electrode 1131 of adjacent trenches 1121,1123 and 1125 bottom.This patterning of blanket formula layer can be used as the anisotropic etching step to carry out, and this etching step plays the effect that selectivity is eat-back part blanket formula layer.During the anisotropic etching step, anti-reflecting layer 1141 can be used as etch stop layer.As shown in the figure, the first electrode 1131 can have than the lower upper surface (in grid groove 1120) in P-N junction interface between base 1111 and boundary layer 1113.
Also with reference to Figure 18 A-18B, blanket formula insulating barrier (not shown) can be deposited on anti-reflecting layer 1141 and in grid groove 1120.Then this blanket formula insulating barrier (it can be formed by the inter-level dielectric material from for example silicon dioxide) is eat-back to define the interior insulating barrier 1135 of grid groove 1120 by selectivity.This etchback step can need not photoetching and carry out.For example, the anisotropic etching step can be carried out as etch stop layer with anti-reflecting layer 1141.As shown in the figure, after eat-backing, the top surface of insulating barrier 1135 is lower than the top surface in boundary layer 1113.
Referring now to Figure 19 A-19B, another conductive layer (not shown) conformally be deposited on anti-reflecting layer 1141 as blanket formula layer and insulating barrier 1135 on.As mentioned above, the material of selecting the group that this conductive layer can be comprised of the combination from aluminium (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal silicide and these electric conducting materials forms.Photoresist layer (not shown) can be deposited on conductive layer, then is patterned to define photoresist mask 1144.Then define the second electrode 1133 with photoresist mask 1144 during etching step.Anti-reflecting layer 1141 can be used as etch stop layer again.During forming the technique of the second electrode 1133, at least a portion marginal zone 1119 can cover with hard mask 1146, in order to define the second electrode 1133a of the periphery of adjacent substrates 1110, as shown in Figure 10 A.As shown in Figure 19 B, the part of insulating barrier 1135 in marginal zone 1119 can be exposed by photoresist mask 1144 and hard mask 1146.
Referring now to Figure 20 A-20B, photoresist mask 1144 and hard mask 1146 can be removed, and another photoresist layer (not shown) can be formed.Then, this photoresist layer can be patterned (for example using wet etching) to define another photoresist mask 1145, and it exposes the first marginal zone 1119a.Then, can carry out dry etch step with the expose portion of selective removal insulating barrier 1135, thereby expose the bottom that extend the periphery of the contiguous semiconductor substrate 1110 of the first electrode 1131a.The bottom of these exposures of the first electrode 1131a can be used as the contact point that outside lead (for example wire-bonded) connects.
Other method embodiment of the present invention is illustrated by Figure 21 A-23A and Figure 21 B-23B.Particularly, Figure 21 A-21B is illustrated in and comprises light transmission conductive layer 1137 on boundary layer 1113.After this, as shown in Figure 22 A-23A, Figure 22 B-23B, Figure 12 A and Figure 12 C, anti-reflecting layer 1141 can conformally be deposited on substrate 1110.As shown in Figure 23 A-23B, the photoresist layer 1147 of patterning is formed on anti-reflecting layer 1141.Then, the photoresist layer 1147 of patterning eat-backs in selectivity during the step of expose portion of anti-reflecting layer 1141 and light transmission conductive layer 1137 as mask, thereby exposes the first electrode 1131a and peripheral adjacent respective lower substrate 1110.Then the photoresist layer 1147 of patterning is removed, as shown in Figure 12 C.
According to additional embodiment of the present invention, the solar cell embodiment of Figure 13 A-13B can use by the step shown in Figure 24 A-25A, Figure 24 B-25B and form.For example, the method that forms solar cell can comprise the modify steps of patterning the second electrode 1133, thus the upper surface of the second electrode 1133 and anti-reflecting layer 1141 coplines.This plane surface profile can be by making the second electrode 1133 planarizations to realize with anti-reflecting layer 1141 coplines, as shown in Figure 24 B.
The marginal portion of the second electrode 1133 is set to annular and extends 1133b.Extend 1133b (it is illustrated by Figure 13 B) and defined circular the second marginal zone 1119b (surface of the first electrode 1131b below its exposure) at the place, periphery of semiconductor substrate 1110.Circular the second marginal zone 1119b has than the less width of the width in Figure 10 " Wa ".Circular the second marginal zone 1119b can define by the photoresist layer 1149 that forms patterning on the planarized surface of the second electrode 1133 and anti-reflecting layer 1141, as shown in Figure 25 A-25B.Thereafter, as shown in Figure 13 A-13B, the part of the expose portion of the second electrode 1133 and following insulating barrier 1135 is selectively removed, thereby the narrower upper surface of the first electrode 1131b can be exposed.By increasing the total contact area between the second electrode 1133,1133b and boundary layer 1113, the solar cell embodiment of Figure 13 A-13B provides higher efficient (with respect to the solar cell embodiment of Figure 10 A-10B) potentially.
Referring now to Figure 26, above-described solar cell embodiment of the present invention can be used to power and control in network 4000, and power is controlled the power that network 4000 receives from solar battery array 3000.As shown, each solar battery array 3000 can be configured to a plurality of solar modules 2000, and each module comprises the array of solar cell 1000.Like this, voltage and/or electric current that the lower voltage that is provided by each solar cell 1000 and/or electric current can provide with the solar cell 1000 by other are combined, thereby produce relatively large power source.Power is controlled network 4000 and is depicted as and comprises output device 4100, power storage device 4200, charge/discharge controller 4300 and system controller 4400, system controller 4400 power ratio control storage devices 4200, charge/discharge controller 4300, power regulating system (PCS) 4120 and Mesh connection system 4140.Output device 4100 can comprise power regulating system (PCS) 4120 and Mesh connection system 4140.PCS 4120 can be for being transformed into from the direct current (DC) of solar battery array 3000 converter of alternating current (AC).Mesh connection system 4140 can be connected to external power system 5000.When the output that is produced by solar battery array 3000 surpassed the power that outputs to external power system 5000, charge/discharge controller 4300 was used for unnecessary energy is transferred to power storage device 4200.Alternatively, when the output that is produced by solar battery array 3000 was not enough to satisfy the demand of external power system 5000, charge/discharge controller 4300 was used for energy is fetched from power storage device 4200.
The above embodiment of the present invention can be manufactured to has different electrode structures and pattern, their incident lights of receiving on the first type surface of solar cell of response and support the efficient collection of electric charge carrier.For example, Figure 27 A is the plane graph of the integrated circuit solar cell 2700 of the additional embodiment according to the present invention, and Figure 27 B is that the I-I ' along the line of the solar cell 2700 of Figure 27 A cuts open the sectional view of getting.As shown in these figures, solar cell 2700 comprise by top surface electrode 2708 around the two-dimensional array in the second conductivity type district 2710 (being depicted as squared region), the second conductivity type district 2710 can have N-type conductivity.Each second conductivity type district 2710 and substrate zone 2702 (it can have P-type conduction) form P-N rectifying junction separately.As shown in Figure 27 B, can be fabricated into electrically contacting of P type substrate zone 2702 by groove base electrode 2704 (it is positioned at the place, bottom of netted groove).Netted top surface electrode 2708 is isolated with following groove base electrode 2704 electricity by the groove base electric insulation layer 2706 (for example silicon dioxide) that inserts, the upper surface of groove base electric insulation layer 2706 can with the upper surface copline of substrate zone 2702, top surface electrode 2708 and N-type district 2710 are formed on substrate zone 2702.
Figure 28 A is the plane graph of the integrated circuit solar cell 2800 of the additional embodiment according to the present invention, and Figure 28 B is that the I-I ' along the line of the solar cell 2800 of Figure 28 A cuts open the sectional view of getting.As shown in the plane graph of Figure 28 A, solar cell 2800 is similar to the solar cell 2700 of Figure 27 A, yet groove base electrode 2804 (seeing, for example Figure 28 B) is depicted as the uppermost light that extends up to solar cell 2800 and accepts the surface.Particularly, Figure 28 B illustrates has the P type substrate zone 2802 that a plurality of N-types district 2810 forms thereon, and a plurality of N-types district 2810 forms the P-N rectifying junctions with substrate zone 2802 respectively.Use a plurality of top surface electrodes 2808 to be fabricated into electrically contacting of N-type district 2810, be fabricated into electrically contacting of P type substrate zone 2802 by groove base electrode 2804, groove base electrode 2804 is depicted as the strip shaped electric poles that extends past abreast solar cell 2800.Further illustrate as Figure 28 B, groove base electrode 2804 and top surface electrode 2808 are electrically isolated from one by electric insulation layer 2806, and the light of electric insulation layer 2806 contiguous solar cells 2800 is accepted the surface and extended.Top surface electrode 2808 is also isolated by electric insulation sept 2809 and following substrate zone 2802 electricity, and electric insulation sept 2809 is arranged on below top surface electrode 2808.
Figure 29 A is the plane graph of the integrated circuit solar cell 2900 of the additional embodiment according to the present invention, and Figure 29 B is that the I-I ' along the line of the solar cell 2900 of Figure 29 A cuts open the sectional view of getting.As shown in Figure 29 A-29B, solar cell 2900 is similar to the solar cell embodiment of Figure 28 A-28B, yet electric insulation layer 2906 moves in substrate zones 2902 and at the opposite side on the top of groove base electrode 2904.Top surface electrode 2908 is arranged on the upper surface of electric insulation layer 2906, and this can make the N-type district 2910 in Figure 29 B larger than the N-type district 2810 in Figure 28 B.Thereby the solar cell embodiment of Figure 29 A-29B can have the light collection efficiency larger than the solar cell embodiment of Figure 28 A-28B.As shown in the figure, the solar cell embodiment of Figure 29 A-29B can also comprise and conformally be deposited in N-type district 2910 and the printing opacity insulating barrier 2912 in the interval between adjacent electrode 2908, makes the light of the contiguous solar cell 2900 of plane surface profile collect the surface and arranges.
Figure 30 A is the plane graph of the integrated circuit solar cell 3000 of the additional embodiment according to the present invention, and Figure 30 B is that the I-I ' along the line of the solar cell 3000 of Figure 30 A cuts open the sectional view of getting.As shown in Figure 30 A-30B, groove base electrode 3004 extends to the parallel striped of the optical receiving surface of crossing solar cell 3000.Each in these groove base electrodes 3004 is electrically connected to substrate zone 3002, and by each insulation spacer 3006 and N-type district's 3010 electricity isolation.These N-types districts 3010 form respectively the P-N knot with following substrate zone 3002, and electrically contact top surface electrode 3008.Electric insulation sept 3009 also is arranged on below top surface electrode 3008, thereby these electrodes 3008 and following substrate zone 3002 are isolated.
Figure 31 A is the plane graph of the integrated circuit solar cell 3100 of the additional embodiment according to the present invention, and Figure 31 B is that the I-I ' along the line of the solar cell 3100 of Figure 31 A cuts open the sectional view of getting.Solar cell 3100 is depicted as the substrate zone 3102 that comprises the square N-type district 3110 that has two-dimensional array on it, square N-type district 3110 by netted top surface electrode 3108 around.As shown in the figure, top surface electrode 3108 is separated and is isolated by electric insulation sept 3109 and substrate zone 3102.As shown in Figure 31 B, the bottom of strip-shaped grooves base electrode 3104 contiguous each grooves arranges.These groove base electrodes 3104 are electrically connected to substrate zone 3102.Electric insulation sept 3106 also is arranged between groove base electrode 3104 and N-type district 3110.Can use wire-bonded (not shown in Figure 31 A-31B) to be fabricated into the external control of groove base electrode 3104, wire-bonded is connected to the periphery of substrate zone 3102 (for example silicon wafer).
Figure 32 A is the plane graph of the integrated circuit solar cell 3200 of the additional embodiment according to the present invention, and Figure 32 B is that the I-I ' along the line of the solar cell 3200 of Figure 32 A cuts open the sectional view of getting.Solar cell 3200 is depicted as the substrate zone 3202 that comprises the square N-type district 3210 that has two-dimensional array thereon, and square N-type district 3210 forms the P-N knot with substrate zone 3202 respectively.A plurality of parallel strip groove base electrodes 3208 are arranged in each groove.As shown in the figure, these groove base electrodes 3208 are electrically connected to top N-type district 3210, but by electric insulation lining 3209 with around substrate zone 3202 electricity isolation, electric insulation lining 3209 extends along bottom and the sidewall of groove.As shown in the figure, a plurality of parallel strip trench electrode 3204 (it is conductively coupled to substrate zone 3202) also are arranged in respective groove.These electrodes 3204 (optical receiving surface of its contiguous solar cell 3200 extends) are by the array electric isolation of electric insulation sept 3206 (for example oxide spacer) with N-type district 3210.
Figure 33 is the plane graph of integrated circuit solar cell 3300 according to another embodiment of the present invention, and it is similar to the embodiment 3100 of Figure 31 A-31B.Solar cell 3300 is depicted as the square N-type district 3310 of the two-dimensional array that comprises thereon, square N-type district 3310 by netted top surface electrode 3308 around.The parallel strip groove base electrode 3304 also bottom of contiguous each groove (not shown in Figure 33) arranges.But opposite with the solar cell 3100 of Figure 31 A-31B, parallel strip groove base electrode 3304 extends at angle with the electrode 3104 with respect to Figure 31 A-31B.
Figure 34 A is the plane graph of the integrated circuit solar cell 3400 of the additional embodiment according to the present invention, Figure 34 B is that the I-I ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting, and Figure 34 C is that the II-II ' along the line of the solar cell embodiment of Figure 34 A cuts open the sectional view of getting.Like this, as shown in Figure 34 B-34C, the groove base electrode 3404 of right-angled intersection grid is embedded in P type substrate zone 3402.P type substrate zone 3402 forms the P-N rectifying junction with the array in square N-type district 3410 respectively.Also be provided with mesh electrode 3408, it is electrically connected to N-type district 3410.Mesh electrode 3408 is by electric insulation sept 3409 (for example silicon dioxide spacer thing) and substrate zone 3402 electricity isolation.Figure 35 is the plane graph of the integrated circuit solar cell 3500 of the additional embodiment according to the present invention, and it is similar to the embodiment of Figure 34 A-34C.As shown in the figure, the groove base electrode 3504 of the right-angled intersection grid of inclination is embedded in P type substrate zone, and P type substrate zone forms the P-N rectifying junction with the array in square N-type district 3510 respectively.Also be provided with mesh electrode 3508, it is electrically connected to N-type district 3510.
Figure 36 A is the plane graph of the solar cell 3600 of the additional embodiment according to the present invention, and Figure 36 B is that the I-I ' along the line of the solar cell 3600 of Figure 36 A cuts open the sectional view of getting.As shown in Figure 36 A-36B, the strip shaped electric poles 3608 of a plurality of relative thin be arranged on the optical receiving surface of solar cell 3600 and with a plurality of strip N-types district 3610 (alongside) side by side, a plurality of strip N-types districts 3610 forms respectively the P-N knot with following substrate zone 3602 (for example P type).These electrodes 3608 are isolated by electric insulation sept 3609 (for example oxide spacer) and following substrate zone 3602 electricity.Figure 36 A-36B also illustrates the groove base electrode 3604 that is parallel to N-type district 3610 and strip shaped electric poles 3608 extensions.These electrodes 3604 (it is electrically connected to substrate zone 3602) are by the N-type district 3610 electricity isolation of electric insulation sept 3606 with vicinity.
Figure 37 A is the plane graph of the solar cell 3700 of the additional embodiment according to the present invention, and Figure 37 B is that the I-I ' along the line of the solar cell 3700 of Figure 37 A cuts open the sectional view of getting.As shown in Figure 37 A-37B, the strip shaped electric poles 3708 of a plurality of relative thin is arranged on the optical receiving surface of solar cell 3700, each electrode 3708 is clipped between a pair of strip N-type district 3710, and strip N-type district 3710 forms the P-N knot with following substrate zone 3702 (for example P type) respectively.These electrodes 3708 are isolated by electric insulation sept 3709 (for example oxide spacer) and following substrate zone 3702 electricity.Figure 37 A-37B also illustrates the groove base electrode 3704 that is parallel to N-type district 3710 and strip shaped electric poles 3708 extensions.These electrodes 3704 (it is electrically connected to substrate zone 3702) are by the N-type district 3710 electricity isolation of electric insulation sept 3706 with vicinity.
In drawing and description, typical preferred embodiment of the present invention is disclosed, although specific term is used, they only use with general and descriptive meaning rather than in order to limit, scope of the present invention is set forth by additional claims.
The present invention requires in the U.S. Provisional Application No.61/054 of submission on May 19th, 2008,233, the U.S. Provisional Application No.61/058 that submits on June 3rd, 2008,322, the priority of the korean patent application No.2008-44062 that submits on May 13rd, 2008 and the korean patent application No.2008-49772 that submits on May 28th, 2008, and these openly are incorporated in this in the reference mode.

Claims (19)

1. solar cell comprises:
Substrate, have at the light on described substrate and collect surface and the P-N rectifying junction in described substrate, described P-N rectifying junction is included in the base of the first conductivity type in described substrate and the semiconductor layer of the second conductivity type of extending between described base and described light collection surface;
Groove extends through the described semiconductor layer of the second conductivity type and enters the described base of the first conductivity type;
The first electrode is couple to the described base of the first conductivity type in the bottom electrical of described groove;
Light transmission conductive layer is on the described semiconductor layer of the second conductivity type; And
The second electrode is conductively coupled to described semiconductor layer and the described light transmission conductive layer of the second conductivity type.
2. solar cell as claimed in claim 1, wherein said light transmission conductive layer comprise the material of selecting from the group that is made of zinc oxide and indium tin oxide and combination thereof.
3. solar cell as claimed in claim 1, wherein said the second electrode extend in described groove and contact the sidewall of described semiconductor layer of the second conductivity type and the sidewall of described light transmission conductive layer.
4. solar cell as claimed in claim 1, also be included in the anti-reflecting layer on described light transmission conductive layer.
5. solar cell as claimed in claim 4, wherein said anti-reflecting layer covers described the second electrode.
6. solar cell comprises:
Substrate, have at the light on described substrate and collect surface and the P-N rectifying junction in described substrate, described P-N rectifying junction is included in the base of the first conductivity type in described substrate and the semiconductor layer of the second conductivity type of extending between described base and described light collection surface;
Groove extends through the described semiconductor layer of the second conductivity type and enters the described base of the first conductivity type;
The first electrode is couple to the described base of the first conductivity type in the bottom electrical of described groove;
Anti-reflecting layer is collected on the surface at described light; And
The second electrode is conductively coupled to the described semiconductor layer of the second conductivity type, and described the second electrode is arranged at above described the first electrode in described groove and has upper surface with the coplanar planarization of upper surface of described anti-reflecting layer.
7. method that forms solar cell comprises:
Make the surface texturizing of silicon wafer to produce the Feng Hegu of localization in described surface, have the base of the first conductivity type in described silicon wafer;
The in-situ doped amorphous silicon layer of deposition the second conductivity type on the described surface of veining, thus definition has the non-rectification heterojunction of the veining on described surface;
Be transformed into clean the second conductivity type thereby be diffused into from described amorphous silicon layer a part that makes described base described base by the second type conductivity dopant with q.s from clean the first conductivity type, form the boundary layer of the second conductivity type in described base;
Formation extends through described amorphous silicon layer and described boundary layer and enters groove in described base;
Formation is conductively coupled to the first electrode of described amorphous silicon layer; And
The bottom electrical that is formed on described groove is couple to the second electrode of described base.
8. method as claimed in claim 7, wherein veining comprises that being exposed to etchant by the surface with described silicon wafer comes etching described surface, described etchant to cause forming residue with as further etched localization etching mask on described surface.
9. method as claimed in claim 8, wherein veining comprises described surface is exposed to the dry ecthing agent that comprises chlorine and fluorine.
10. method as claimed in claim 7, the boundary layer that wherein forms the second conductivity type in described base comprise form have from
Figure FSB00000950472500021
Arrive
Figure FSB00000950472500022
Scope in the boundary layer of thickness.
11. the temperature that method as claimed in claim 10, the boundary layer that wherein forms the second conductivity type in described base are included in the scope of 500 ℃ to 900 ℃ is annealed to described amorphous silicon layer.
12. method as claimed in claim 10 wherein deposits in-situ doped amorphous silicon layer and comprises that deposition has from 1 * 10 19cm -3To 1 * 10 21cm -3The in-situ doped amorphous silicon layer of the second conductivity type of the doping content in scope.
13. method as claimed in claim 10 wherein deposits in-situ doped amorphous silicon layer and comprises the in-situ doped amorphous silicon layer that uses low-pressure chemical vapor deposition deposition techniques the second conductivity type.
14. method as claimed in claim 7 wherein forms bottom deposition the second electrode that the second electrode is included in described groove; And wherein form top deposition the first electrode that the first electrode is included in described groove.
15. method as claimed in claim 14, wherein the electricity consumption dielectric spacer layer covers described the second electrode before forming the first electrode, and described electric insulation wall extends between the sidewall of described groove.
16. method as claimed in claim 15 wherein forms groove and comprises the latticed groove of formation, has the groove of a plurality of right-angled intersections that extend past described silicon wafer in described latticed groove.
17. method as claimed in claim 16, wherein said latticed groove is included in the outermost annular ditch groove of the periphery of described silicon wafer; And wherein carry out after forming the first electrode described the first electrode of selective removal the part of described annular ditch groove and below described electric insulation wall in the part of described annular ditch groove, thereby expose described the second electrode.
18. method as claimed in claim 17 also comprises a plurality of wire-bonded of the expose portion that is formed into described the second electrode in described annular ditch groove.
19. method as claimed in claim 17 wherein was injected into the first type conductivity dopant the described bottom of described groove before deposition the second electrode of the described bottom of described groove.
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US61/054,233 2008-05-19
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KR1020080049772A KR20090123612A (en) 2008-05-28 2008-05-28 Solar cell and method of forming the same
US5832208P 2008-06-03 2008-06-03
US61/058,322 2008-06-03
US12/437,583 2009-05-08
US12/437,595 2009-05-08
US12/437,583 US20090283145A1 (en) 2008-05-13 2009-05-08 Semiconductor Solar Cells Having Front Surface Electrodes
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