CN101621010A - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- CN101621010A CN101621010A CN200910008580A CN200910008580A CN101621010A CN 101621010 A CN101621010 A CN 101621010A CN 200910008580 A CN200910008580 A CN 200910008580A CN 200910008580 A CN200910008580 A CN 200910008580A CN 101621010 A CN101621010 A CN 101621010A
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- 238000000034 method Methods 0.000 claims abstract description 93
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of fabricating a semiconductor device includes forming a gate dielectric on a substrate, forming a gate structure on the gate dielectric, the gate structure comprising a stacked layer of a silicon layer and a metal layer, selectively etching the gate structure to form a gate pattern, forming a capping layer surrounding the gate pattern, plasma-treating the capping layer, and performing a gate reoxidation process.
Description
Related application
The application requires korean patent application 10-2008-0063183 that on June 30th, 2008 and October 8 in 2008, bu you can well imagine to be handed over and the priority of 10-2008-0098625, incorporates its full content into this paper by reference.
Technical field
The present invention relates to make the technology of semiconductor device, more specifically relate to the semiconductor device and the manufacture method thereof that comprise gate electrode with polysilicon metal (polymetal) structure.More specifically, the present invention relates to make the method for semiconductor device, in one or more embodiment, described method comprises: implement gate re-ox technology and suppress the oxidation of polysilicon metal interface simultaneously, and be not subjected to the influence of metallic pollution, form semiconductor device thus.
Background technology
Recently, in order to be provided at the operating characteristic that needs in the highly integrated semiconductor device, semiconductor device uses the gate electrode with so-called polysilicon metal structure, wherein stacks gradually high-melting-point and low resistance metal layer such as polysilicon (Poly-Si) layer and tungsten (W) layer.Gate electrode with polysilicon metal structure has the Poly-Si/WN/W structure, wherein stacks gradually polysilicon (Poly-Si) layer, tungsten nitride (WN) layer and tungsten (W) layer.Tungsten nitride layer is used as at the diffusion impervious layer that prevents from during the manufacturing process to react between tungsten layer and the polysilicon layer.
When the grid structure that wherein stacks gradually polysilicon layer, tungsten nitride layer and tungsten layer by selective etch on gate-dielectric forms gate pattern, on gate-dielectric, produce little groove and plasma damage.Implement gate re-ox technology to repair the damage of gate-dielectric.Since tungsten layer in gate re-ox technology oxidized in the volume rapid expanding, the selective oxidation processes of non-tungsten oxide layer or tungsten nitride layer so only use the oxidation polysilicon layer.Referring to, Selective Oxidation ofSilicon (100) vs.Tungsten Surfaces by Steam in Hydrogen, Journal of theElectrochemical Society, 150 volumes, the 10th phase, G597-G601 page or leaf (in October, 2003).
Figure 1A and 1B are presented at each stage sectional view of making in the typical method that comprises the flash memory with polysilicon metal structure gate electrode.
With reference to Figure 1A, on substrate 11, form and be also referred to as the gate-dielectric 12 of tunnel insulation layer, and on gate-dielectric 12, form grid structure.Grid structure comprises first polysilicon layer 13, dielectric layer 14, second polysilicon layer 15, tungsten nitride layer 16, tungsten layer 17 and the gate hard mask layer 18 as diffusion impervious layer as charge storage layer.On gate-dielectric 12, in turn pile up above-mentioned layer.
On gate hard mask layer 18, form photoresist pattern (not shown), and, form gate pattern 19 thus by using described photoresist pattern as etch stop layer etching grid structure.During this technology, what expose when forming gate pattern 19 produces little groove and plasma damage on the lower edge of the surface of gate-dielectric 12 and gate pattern 19.This damage is shown in the wavy line on 12 upper surfaces of gate-dielectric among Figure 1A.In addition, on the both sides of the dielectric layer 14 that exposes, also produce plasma damage.
In order to repair the little groove and the plasma damage of gate-dielectric 12 and dielectric layer 14, implement gate re-ox technology by using the selective oxidation processes that in Figure 1B, illustrates.As can be seen: by gate re-ox technology, gate-dielectric 12 under gate pattern 19 lower edge becomes thicker, and only on the side of first and second polysilicon layers 13 and 15, form oxide skin(coating) 13A and 15A, and do not have tungsten oxide layer 17 and tungsten nitride layer 16.
As mentioned above, when use has the gate electrode of polysilicon metal structure, strengthened Devices Characteristics by gate re-ox technology.Yet gate re-ox technology is introduced several problems, and is described referring now to Fig. 2,3A and 3B.
Fig. 2 is the retention characteristic curve chart according to metallic pollution in the typical flash memory part that comprises the gate electrode with polysilicon metal structure.
Particularly, Fig. 2 is to be T1 and T2 (the retention characteristic curve chart of T1＜T2) being higher than heat treatment time under 300 ℃ the temperature.As seen from Figure 2: retention characteristic is along with heat treatment time increases and deterioration.This is because charge stored is owing to the metallic pollution that the Metal Substrate accessory substance that produces during gate re-ox technology is caused spills in being used as first polysilicon layer 13 of charge storage layer.
Particularly, common gate re-ox technology is used H under for example about 700～about 900 ℃ high temperature
2O gas or O
2Gas is implemented.Therefore, tungsten layer 17 and H
2O gas or O
2Gas reaction is to produce gaseous metal base accessory substance such as WH
2O
4Or WO
xIn subsequent technique especially heat treatment, the Metal Substrate by-product contamination substrate 11 and the chamber of generation, the electrical property of deterioration semiconductor device.
In addition, even when removing the Metal Substrate accessory substance that in gate re-ox technology, produces fully by follow-up cleaning procedure, if but heat treatment is implemented in the oxygen atmosphere such as the subsequent technique that forms the grid spacer oxide skin(coating), then since produce with gate re-ox technology in identical Metal Substrate accessory substance, so cause metallic pollution.
Above-mentioned metallic pollution also produces in the electrode with polysilicon metal structure, and described polysilicon metal structure is used metal such as Mo, Ta, Ti, Ru, Ir and the Pt except W.
Fig. 3 A and 3B explanation comprise the polysilicon metal interface of the typical semiconductor device of the gate electrode with polysilicon metal structure.Particularly, Fig. 3 A is the photo of polysilicon metal interface cross section, and Fig. 3 B is that explanation uses electron energy loss spectroscopy (EELS) (EELS) to analyze the curve chart of the analysis result of polysilicon metal interface component.
With reference to figure 3A and 3B, as can be seen: after the gate re-ox technology, form the SiO of thickness on the interface of the tungsten nitride layer 16 contact tungsten layers 17 and second polysilicon layer 15 therein greater than 2nm
xDielectric layer.Dielectric layer increases the vertical resistor (vertical resistance) of grid, causes the problem in high frequency run duration such as signal delay.
Summary of the invention
One or more embodiments relate to semiconductor device and the manufacture method thereof that comprises the gate electrode with polysilicon metal structure, and described polysilicon metal structure prevents metallic pollution in gate re-ox technology.
One or more embodiments relate to semiconductor device and the manufacture method thereof that comprises the gate electrode with polysilicon metal structure, described polysilicon metal structure is by inhibition or prevent the oxidation at the interface of metal layer contacting polysilicon layer in gate re-ox technology, thereby can improve the vertical resistor of gate electrode.
One or more embodiments relate to semiconductor device and the manufacture method thereof that comprises the gate electrode with polysilicon metal structure, and described polysilicon metal structure can prevent the oxidation of metal level in gate re-ox technology.
One or more embodiments relate to the method for making semiconductor device, and described method comprises: form gate-dielectric on substrate; Form grid structure on described gate-dielectric, described grid structure comprises the stack layer of silicon layer and metal level; Optionally the described grid structure of etching is to form gate pattern; Form the cover layer that surrounds described gate pattern; The described cover layer of plasma treatment; With enforcement gate re-ox technology.
In one or more embodiment, the plasma treatment cover layer can be by using oxygen (O
2) plasma implements.The plasma treatment cover layer comprises: form plasma by using inert gas in chamber; With make oxygen (O
2) flow into the chamber wherein form plasma.
In one or more embodiment, the plasma treatment cover layer can be implemented under the temperature that is lower than gate re-ox technology.The plasma treatment cover layer can be implemented under about 50 ℃～about 250 ℃ temperature.Gate re-ox technology can be implemented under about 700 ℃～about 900 ℃ temperature.
Gate re-ox technology can be implemented by the mist that uses oxygen-containing gas and hydrogen-containing gas.Oxygen-containing gas can comprise H
2O gas or O
2Gas, hydrogen-containing gas can comprise H
2Gas.
Cover layer can form under about 50 ℃～about 250 ℃ temperature.Cover layer can comprise silicon oxide layer.Cover layer can pass through ald (ALD) technology or plasma enhanced atomic layer deposition (PEALD) technology forms.
In one or more embodiment, form cover layer and comprise: with the substrate that is formed with gate pattern on it chamber of packing into; Make silicon source gas flow into chamber; Clean silicon source gas; Make oxygen source gas flow into chamber; With the cleaning oxygen source gas.Silicon source gas flows and oxygen source gas flows and can comprise: make the gas that comprises amido flow into chamber with silicon source gas and oxygen source gas.Cover layer can form in plasma atmosphere.Plasma atmosphere can form by using argon gas or nitrogen.
In one or more embodiment, grid structure can comprise: comprise the stack layer of the silicon layer, metal level and the gate hard mask layer that stack gradually, or comprise the stack layer of the electric charge storage layer, dielectric layer, silicon layer, metal level and the gate hard mask layer that stack gradually.Charge storage layer can comprise silicon layer or dielectric layer.
According to one or more embodiment, the method for making semiconductor device comprises: form gate-dielectric on substrate; Form grid structure on described gate-dielectric, described grid structure comprises the stack layer of silicon layer and metal level; Optionally the described grid structure of etching is to form gate pattern; Form the cover layer that surrounds gate pattern; The described cover layer of plasma treatment; With enforcement gate re-ox technology in plasma atmosphere.
In one or more embodiment, implement gate re-ox technology and comprise: in chamber, form plasma by using inert gas; With make the mist of oxygen-containing gas and hydrogen-containing gas flow into the chamber wherein form plasma.Oxygen-containing gas can comprise H
2O gas or O
2Gas, hydrogen-containing gas can comprise H
2Gas.Gate re-ox technology can be implemented under about 200 ℃～about 900 ℃ temperature.
Description of drawings
Figure 1A and 1B are presented at the sectional view of making each stage in the typical method that comprises the flash memory with polysilicon metal structure gate electrode.
Fig. 2 is the retention characteristic curve chart according to metallic pollution in the typical flash memory part that comprises the gate electrode with polysilicon metal structure.
Fig. 3 A is the photo of polysilicon metal interface cross section.
Fig. 3 B is that explanation uses electron energy loss spectroscopy (EELS) (EELS) to analyze the curve chart of the analysis result of polysilicon metal interface component.
Fig. 4 A～4D shows the sectional view of making each stage of method of semiconductor device according to an embodiment.
Fig. 5 A～5C shows the sectional view of making each stage of method of semiconductor device according to another embodiment.
Fig. 6 is forming the sequential chart that is used for the exemplary curve of parallel process in the tectal technology by use ald (ALD) technology.
Fig. 7 is that explanation is according to the data point diagram on the curve of cover layer existence and non-existent metallic pollution degree.
Fig. 8 A and 8B are photo and the figure of explanation according to the polysilicon metal interface of the semiconductor device that comprises gate electrode of one or more embodiments, and gate electrode has and is applied with tectal bag polysilicon metal structure.
Fig. 9 A and 9B are the figure of explanation according to the tectal measurement characteristics of one or more embodiments.
Embodiment
Can understand other purpose and the advantage of one or more embodiments by following description, and pass through with reference to one or more embodiments, other purpose and the advantage of described one or more embodiments will become apparent.
In the drawings, the yardstick with layer and zone amplifies with clearly explanation.Also should be appreciated that, when layer (or film) be called as another layer or substrate " on " time, its can be directly on other layer or substrate, or also can have the intermediate layer.In addition, should understand when layer is called as at another layer D score, can also can there be one or more intermediate layers in it directly under another layer.In addition, also should understand when layer be called as two-layer " between " time, it can be at described only layer between two-layer, or also can have one or more intermediate layer.
One or more embodiment is to make the method for the semiconductor device that comprises gate electrode, and described gate electrode has the so-called polysilicon metal structure of wherein piling up polysilicon (poly-Si) layer and metal level.More specifically, one or more embodiment is to make the method for semiconductor device, and described method can be implemented gate re-ox technology and suppress simultaneously or prevent the wherein interface oxidation of metal layer contacting polysilicon layer, and is not subjected to the influence of metallic pollution.
For this reason, one or more embodiment comprises the cover layer of plasma treatment, and described cover encloses gate pattern also formed before gate re-ox technology there.
Below, will be described in conjunction with the embodiments, one of them embodiment is used to comprise the cell transistor of the dynamic random access memory (DRAM) of the gate electrode with polysilicon metal structure.
[embodiment]
Fig. 4 A～4D shows the sectional view of making each stage of method of semiconductor device according to an embodiment.
With reference to figure 4A, on substrate 21, form gate dielectric 22.Gate dielectric 22 can be by thermal oxidation technology by oxide silicon dioxide (SiO for example
2) form.
Can implement nitrogen treatment in addition and in subsequent technique, penetrate into substrate 21 with the impurity of avoiding being contained in the silicon layer 23 that on gate dielectric 22, to form (for example, boron (B)).Described nitrogen treatment can be by at nitrogenous gas atmosphere N for example
2Furnace treatment reason or rapid hot technics in O or the NO gas atmosphere are implemented.
On gate-dielectric 22, form grid structure.Grid structure can comprise the stacked structure that wherein in turn piles up silicon layer 23, diffusion impervious layer 24, metal level 25 and gate hard mask layer 26.
Diffusion impervious layer 24 prevents in subsequent technique the inter-level diffusion on the interface of silicon layer 23 contact metal layer 25 therein and reacts to each other.Diffusion impervious layer 24 can be by being selected from a kind of in the following refractory metal or can being formed by the stack layer of following refractory metal: titanium (Ti), cobalt (Co), molybdenum (Mo), platinum (Pt), iridium (Ir), ruthenium (Ru), chromium (Cr), tantalum (Ta) and zirconium (Zr).In addition, wherein the metal nitride that combines with nitrogen (N) of refractory metal such as tungsten nitride (WN
X) can be used as diffusion impervious layer 24.In addition, diffusion impervious layer 24 can comprise the stacked structure that wherein piles up refractory metal and metal nitride.According to an embodiment, diffusion impervious layer 24 is formed by tungsten nitride (WN).
Gate hard mask layer 26 is protected substructure and be used as etch stop layer in Patternized technique in subsequent technique.Gate hard mask layer 26 can comprise one or more kinds in the stacked structure that is selected from oxide skin(coating), nitride layer, oxynitride layer or above-mentioned layer.Oxide skin(coating) can comprise silicon dioxide (SiO
2) layer, boron phosphorus silicate glass (BPSG) layer, phosphosilicate glass (PSG) layer, tetraethyl orthosilicate (TEOS) layer, unadulterated silicate glass (USG) layer, spin-coating glass (SOG) layer, high-density plasma (HDP) layer or spin-on dielectric (SOD) layer.Nitride layer can comprise silicon nitride (Si
3N
4) layer.Oxynitride layer can comprise silicon oxynitride (SiON) layer.
On gate hard mask layer 26, form photoresist pattern (not shown).Pattern forms gate pattern 27 thus as etch stop layer etching grid structure by making with photoresist.Particularly, by making with photoresist pattern as etch stop layer etching grid hard mask layer 26, and, form gate pattern 27 thus by using gate hard mask layer after the etching as etch stop layer in turn etch metal layers 25, diffusion impervious layer 24 and silicon layer 23.
The etch process that is used to form gate pattern 27 can be implemented by dry etching process.Described dry etching process can be implemented by plasma etch process.Therefore, produce little groove and plasma damage in the surface of gate dielectric 22 that in the technology that forms gate pattern 27, exposes and the gate dielectric 22 under gate pattern 27 lower edge.Shown in the wave on the upper surface of gate dielectric 22 among Fig. 4 A.
Though do not show that the etched surfaces of silicon layer 23 can form has positive slopes (positive slope), be suppressed at the damage of gate pattern 27 lower edge lower gate dielectric mediums 22 in the etch process that forms gate pattern 27 with maximum.In one or more embodiment, the damage of gate dielectric 22 will obtain repairing in follow-up gate re-ox technology.
With reference to figure 4B, on the resulting structures that comprises gate pattern 27, form cover layer 28.Cover layer 28 suppresses or prevents the oxidation at the interface of the generation of metallic pollution in follow-up gate re-ox technology and silicon layer 23 contact metal layer 25.
Cover layer 28 can be formed such as silica by oxide.The silicon oxide layer that comprises in the cover layer 28 can comprise SiO
x(wherein x is a natural number), SiO
xF
y(wherein x and y are natural numbers) or SiO
xN
y(wherein x and y are natural numbers).
Cover layer 28 can be equal to or less than form with the technology of avoiding forming cover layer 28 under 300 ℃ the low temperature in the oxidation of metal level 25.Particularly, cover layer 28 can form under about 50 ℃～about 250 ℃ temperature.
The example that forms the method for cover layer 28 in low temperature (for example, being equal to or less than 300 ℃ temperature) technology can comprise: ald (ALD) technology, plasma strengthen atomic deposition (PEALD) technology, thermal oxidation technology and chemical vapor deposition (CVD) technology.Yet, so since thermal oxidation technology need at low temperatures in application, to have problems for a long time, so ALD technology or PEALD technology can be preferably as the technology of manufacturing semiconductor device.Similarly, CVD technology is owing to being difficult to control the thin layer homogeneity, so have problems in application.
On the other hand, because ALD technology or PEALD technology have more excellent step coverage than thermal oxidation technology and CVD technology, has the more cover layer 28 of homogeneous thickness so can on the resulting structures that comprises gate pattern 27, form.
Consider follow-up gate re-ox technology, cover layer 28 can form has thin thickness, and for example about 50～approximately
If the thickness of cover layer 28 less than
Think so and be difficult to prevent metallic pollution and the wherein oxidation at the interface of silicon layer 23 contact metal layer 25 in follow-up gate re-ox technology.On the other hand, if the thickness of cover layer 28 greater than
The uneven upper surface of gate dielectric 22 can be unsmooth in follow-up gate re-ox technology so.
Form silica cover layer 28 until conformal minimal thickness (for example, about 50～approximately below with reference to Fig. 6 detailed description by using ALD technology (to be equal to or less than 300 ℃) at low temperatures
) method.
When formation cover layer 28 was used to prevent the oxidation of metal level 25 down at low temperature (being equal to or less than 300 ℃), its inside comprised impurity such as chlorine (Cl) and carbon (C) usually.The impurity of cover layer 28 inside is by the silicon source gas and the catalyst generation (see figure 6) that are used for forming down at low temperature (being equal to or less than 300 ℃) silica cover layer 28.In this way, when impurity is present in the cover layer 28, be difficult to prevent effectively in follow-up gate re-ox technology the metallic pollution and the interface oxidation of silicon layer 23 contact metal layer 25 wherein.In addition, but the leakage current characteristic of the impurity deterioration cover layer 28 of cover layer 28 inside and in cover layer 28, produce a plurality of trap-charges.
Shown in Fig. 4 C,, implement impurity and the densification cover layer 28 (see Fig. 9 A and 9B) of plasma treatment to remove cover layer 28 inside for preventing the problem that impurity caused by cover layer 28 inside.In one or more embodiment, plasma treatment can be by using oxygen (O
2) plasma implements.Reference numeral 28A refers to the cover layer of plasma treatment.
Below describe and relate to impurity (for example chlorine and carbon) and the cover layer of the densification simultaneously 28A that removes cover layer 28A inside by plasma treatment.
In one or more embodiment, with substrate 21, cover layer 28A and the intermediate layer chamber of packing into, and by use inert gas for example argon gas (Ar) form plasma in chamber interior.When making oxygen (O
2) when flowing in the chamber that wherein forms plasma, because the plasma that forms, so oxygen ionization produces oxygen radical simultaneously.React to produce volatile accessory substance by the oxygen radical of plasma generation and the impurity of cover layer 28A inside, the impurity of the removable cover layer 28A of the volatile accessory substance inside of generation is discharged to the chamber outside simultaneously.The volatile accessory substance that produces can be Cl
xO
y(wherein x and y are natural numbers) and C
xO
y(wherein x and y are natural numbers).In addition, the space of the sky after the impurity of oxygen radical filling cover layer 28A inside removes, densification cover layer 28A thus.In one or more embodiment, plasma treatment can be implemented with the oxidation that prevents metal level 25 under about 50～about 250 ℃ temperature and improve process efficiency simultaneously.
In a word, inert gas produces plasma atmosphere in chamber interior, and removes the impurity and the densification cover layer 28A of cover layer 28A inside by the oxygen radical that plasma is obtained by oxygen ionization.
The impurity of cover layer 28A inside can be by using typical heat to handle for example boiler tube heat treatment in oxygen atmosphere or rapid hot technics (RTP) removes.Yet, when implementing heat treatment down when preventing the oxidation of metal level 25, the arts demand long period by using typical heat to handle at low temperature (being equal to or less than 300 ℃).This causes corresponding productive rate to reduce.And, can not remove the impurity of cover layer 28A inside.
On the other hand, owing to the high mars free radical that uses according to the plasma treatment of an embodiment by plasma generation, so can also can prevent the oxidation of metal level 25 in plasma treatment at for example about 100 ℃ of following implementing process of low temperature.In addition, because plasma treatment is used high mars free radical, so even it is implemented at low temperatures, the relevant processing time is also less than the typical heat processing time.
With reference to figure 4D, implement gate re-ox technology.Implement gate re-ox technology, to repair little groove and the plasma damage that in the technology that forms gate pattern 27, on gate dielectric 22, produces.
In one or more embodiment, can reoxidize process implementing gate re-ox technology to avoid the oxidation of metal level 25 by using selectivity.Reference numeral 22A refers to the gate dielectric 22 of having repaired damage by gate re-ox technology.
Gate re-ox technology can be by using oxygen-containing gas and hydrogen-containing gas mist implement being higher than under the temperature of plasma treatment.In one or more embodiment, oxygen-containing gas can comprise H
2O gas or O
2Gas, hydrogen-containing gas can comprise H
2Gas.For example, gate re-ox technology can be by using H under about 700 ℃～about 900 ℃ temperature
2O/H
2Mist or O
2/ H
2Mist is implemented.
In above-mentioned mist, hydrogen-containing gas prevents the oxidation of metal level 25 in gate re-ox technology, and oxygen-containing gas is repaired the damage of gate-dielectric 22.
By gate re-ox technology, oxide skin(coating) 23A only forms on the sidewall of silicon layer 23, and comprises that the damage of the gate dielectric 22A of gate pattern 27 lower edge obtains repairing.At this, because cover layer 28A surrounds gate pattern 27, even so gate re-ox technology the higher temperature that is higher than the plasma treatment temperature for example about 700～about 900 ℃ implement down, also can prevent metallic pollution and the interface oxidation of silicon layer 23 contact metal layer 25 (seeing Fig. 7,8A and 8B) wherein.
By technology and the gate re-ox technology of implementing plasma treatment cover layer 28A simultaneously, the gate dielectric 22A that the impurity of removable cover layer 28A inside and acquisition damage obtain repairing.This can realize by implement gate re-ox technology in plasma atmosphere.Below describe relate to according to other～individual embodiment implements plasma treatment and gate re-ox technology simultaneously.
Though show, finish the process of making semiconductor device by implementing a series of typical semiconductor device manufacturing process (comprising for example technology and the source electrode and the drain ion injection technology of the sept oxide skin(coating) of LDD ion implantation technology, formation gate pattern 27).
Even implement high temperature (being equal to or higher than 300 ℃) technology in the oxygen atmosphere identical with finishing technology (especially forming the technology of the sept oxide skin(coating) of gate pattern 27 after the gate re-ox technology) that semiconductor device makes, cover layer 28A also can prevent the metallic pollution and the interface oxidation of silicon layer 23 contact metal layer 25 wherein.In addition, cover layer 28A can prevent the oxidation of metal level 25.
Therefore, in one or more embodiment, the formation of cover layer 28A can prevent the metallic pollution and the interface oxidation of silicon layer 23 contact metal layer 25 wherein in gate re-ox technology and subsequent technique.
In addition, by implementing impurity and the simultaneously densification cover layer 28A of plasma treatment, can further prevent the metallic pollution and the interface oxidation of silicon layer 23 contact metal layer 25 wherein in gate re-ox technology and subsequent technique effectively to remove cover layer 28A inside.
In addition, by being implemented in the technology that forms cover layer 28A under the low temperature (being equal to or less than 300 ℃), can prevent the oxidation of metal level 25 in the technology that forms cover layer 28A.
Therefore, can increase the electrical characteristics and the yields of the semiconductor device that comprises gate electrode with polysilicon metal structure according to the method for one or more embodiment.
The following description that relates to another embodiment of the invention is applied to flash memory.
[another embodiment]]
Fig. 5 A～5C shows the sectional view of making each stage of method of semiconductor device according to another embodiment.
With reference to figure 5A, on substrate 41, form gate dielectric.The gate-dielectric of flash memory is commonly referred to tunnel insulation layer 42.Tunnel insulation layer 42 can be by thermal oxidation by oxide silicon dioxide (SiO for example
2) form.
Can implement nitrogen treatment in addition and in subsequent technique, penetrate into substrate 21 to prevent the impurity that is contained in the charge storage layer 43 that on tunnel insulation layer 42, to form.Described nitrogen treatment can be by at nitrogenous gas atmosphere N for example
2Furnace treatment reason (furnacethermal treament) or rapid hot technics in O or the NO gas atmosphere are implemented.
On tunnel insulation layer 42, form grid structure.Grid structure can have the stacked structure that wherein in turn piles up charge storage layer 43, dielectric layer 44, silicon layer 45, diffusion impervious layer 46, metal level 47 and gate hard mask layer 48.
Diffusion impervious layer 46 prevents in subsequent technique the inter-level diffusion on the interface of silicon layer 45 contact metal layer 47 therein and reacts to each other.Diffusion impervious layer 46 can be by being selected from a kind of in the following refractory metal or can being formed by the stack layer of following refractory metal: titanium (Ti), cobalt (Co), molybdenum (Mo), platinum (Pt), iridium (Ir), ruthenium (Ru), chromium (Cr), tantalum (Ta) and zirconium (Zr).In addition, the metal nitride such as the tungsten nitride (WN that combine with nitrogen (N) of refractory metal wherein
X) can be used as diffusion impervious layer 46.In addition, diffusion impervious layer 46 can comprise the stacked structure that wherein piles up refractory metal and metal nitride.According to another embodiment, diffusion impervious layer 46 is formed by tungsten nitride (WN).
Gate hard mask layer 48 is protected substructure and be used as etch stop layer in Patternized technique in subsequent technique.Gate hard mask layer 48 can be formed by one or more kinds that are selected from oxide skin(coating), nitride layer, oxynitride layer or its stack layer.
On gate hard mask layer 48, form photoresist pattern (not shown) and pattern forms gate pattern 49 thus as etch stop layer etching grid structure by making with photoresist.Particularly, by making with photoresist pattern as etch stop layer etching grid hard mask layer 48, and, form gate pattern 49 thus by using gate hard mask layer 48 after the etching as etch stop layer in turn etch metal layers 47, diffusion impervious layer 46 and silicon layer 45, dielectric layer 44 and charge storage layer 43.As a reference, in gate pattern 49, charge storage layer 43 is commonly referred to floating grid (FG), and dielectric layer 44 is commonly referred to control dielectric (control dielectric).And the stack layer of silicon layer 45, diffusion impervious layer 46 and metal level 47 is commonly referred to control grid (CG).
The etch process that forms gate pattern 49 can be implemented by dry etching process.Described dry etching process can be implemented by plasma etching process.Therefore, produce little groove and plasma damage in the surface of the sidewall of the dielectric layer 44 that in the technology that forms gate pattern 49, exposes, tunnel insulation layer 42 and the tunnel dielectric 42 under gate pattern 49 lower edge.As shown in the uneven upper surface of tunnel insulation layer 42 among Fig. 5 A.
Though do not show that the etched surfaces of charge storage layer 43 can form has positive slopes, be suppressed at the damage of the tunnel insulation layer 42 of gate pattern 49 lower edge in the etch process that forms gate pattern 49 with maximum.The not plane surface of tunnel insulation layer 42 will obtain in follow-up gate re-ox technology smoothly.
With reference to figure 5B, on the resulting structures that comprises gate pattern 49, form cover layer 50.Cover layer 50 suppresses or prevent to produce the metallic pollution and the interface oxidation of silicon layer 45 contact metal layer 47 wherein in follow-up gate re-ox technology.
The example that forms the method for cover layer 50 in low temperature (for example, being equal to or less than 300 ℃ temperature) technology can comprise: ald (ALD) technology, plasma strengthen atomic deposition (PEALD) technology, thermal oxidation technology and chemical vapor deposition (CVD) technology.Yet ALD technology or PEALD technology can be preferred for making the technology of semiconductor device.Because there is the problem that needs under the low temperature for a long time in thermal oxidation technology, so this is correct.Similarly, there is the problem that is difficult to control the thin layer homogeneity in CVD technology.
On the other hand, because ALD technology or PEALD technology have more excellent step coverage than thermal oxidation technology and CVD technology, has the more cover layer 50 of homogeneous thickness so can on the resulting structures that comprises gate pattern 27, form.
Consider follow-up gate re-ox technology, cover layer 50 can form has thin thickness, for example about
～approximately
If the thickness of cover layer 50 less than
Be difficult to prevent in follow-up gate re-ox technology the metallic pollution and the interface oxidation of silicon layer 45 contact metal layer 47 wherein.On the other hand, if the thickness of cover layer 50 greater than
The uneven upper surface of gate dielectric 42 can be unsmooth in follow-up gate re-ox technology so.
Formation silica cover layer 50 is (for example, about until the minimal thickness of homogeneous by using ALD technology (to be equal to or less than 300 ℃) at low temperatures below with reference to Fig. 6 detailed description
～approximately
) method.
Owing to form cover layer 50 to prevent the oxidation of metal level 47, so its inside comprises impurity such as chlorine (Cl) and carbon (C) down at low temperature (being equal to or less than 300 ℃).The impurity of cover layer 50 inside is by the silicon source gas and the catalyst generation (see figure 6) that are used for forming down at low temperature (being equal to or less than 300 ℃) silica cover layer 50.Like this, when impurity is present in the cover layer 50, be difficult to prevent effectively in follow-up gate re-ox technology the metallic pollution and the interface oxidation of silicon layer 45 contact metal layer 47 wherein.In addition, but the leakage current characteristic of the impurity deterioration cover layer 50 of cover layer 50 inside and in cover layer 50, produce a plurality of trap-charges.
Shown in Fig. 5 C,, in plasma atmosphere, implement gate re-ox technology for preventing problem that impurity caused and simplified manufacturing technique by cover layer 50 inside.That is, implement to be used to the gate re-ox technology (seeing Fig. 9 A and 9B) that removes the plasma treatment of cover layer 50 inner impurity and densification cover layer 50 and be used to repair the dielectric layer 44 and the gate-dielectric 42 of damage simultaneously.Reference numeral 50A refers to the cover layer of plasma treatment, and Reference numeral 42A and 44A refer to respectively by gate-dielectric and dielectric layer after the gate re-ox technology reparation damage.
By above-mentioned technology, the impurity of cover layer 50A inside is removed and described layer is carried out densification.And oxide skin(coating) 43A and 45A form on the sidewall of silicon layer 45 that is formed by polysilicon and charge storage layer 43, and gate-dielectric 42A obtains repairing with the damage that comprises the dielectric layer 44A of gate pattern 49 lower edge.In one or more embodiment, because cover encloses gate pattern 49, so can prevent from during above-mentioned technology, to produce metallic pollution and the interface oxidation of silicon layer 45 contact metal layer 47 (seeing Fig. 7,8A and 8B) wherein.
Below describe and relate to impurity (for example, chlorine and carbon) and the cover layer of the densification simultaneously 50A that under plasma atmosphere, removes cover layer 50A inside by gate re-ox technology.
The substrate 41 that will the comprise cover layer 50A chamber of packing into, and by use inert gas for example argon gas (Ar) form plasma in chamber interior.Make the mist of oxygen-containing gas and hydrogen-containing gas flow into the chamber that wherein forms plasma.In one or more embodiment, H
2O gas or O
2Gas can be used as oxygen-containing gas, H
2Gas can be used as hydrogen-containing gas.According to another embodiment, gate re-ox technology can be implemented under about 200 ℃～about 900 ℃ temperature.
For example, if with H
2O/H
2Mist or O
2/ H
2Mist flows into the chamber that wherein forms plasma under about 200 ℃～about 900 ℃ of temperature, H
2O/H
2Mist or O
2/ H
2Therefore mist also produces hydrogen (H) free radical and oxygen (O) free radical by the plasma ionization that forms in chamber interior.React to produce volatile accessory substance by the oxygen radical of plasma generation and the impurity (carbon and chlorine) of cover layer 50A inside, the impurity of the removable cover layer 50A of the volatile accessory substance inside of generation is discharged to the chamber outside simultaneously.In addition, the space of the sky after the impurity of oxygen radical filling cover layer 50A inside removes, densification cover layer 50A thus.In addition, oxygen radical and the silicon layer 45 that is formed by polysilicon and charge storage layer 43 reactions to be forming oxide skin(coating) 43A and 45A on its sidewall, and the level and smooth not plane surface of dielectric layer 44A and gate dielectric 42A.At this, hydroperoxyl radical is used to prevent the oxidation of metal level 47.
In a word, inert gas produces plasma atmosphere in chamber interior, is removed the not plane surface of impurity, densification cover layer 50A and the level and smooth gate dielectric 42A and the dielectric layer 44A of cover layer 50A inside by the oxygen radical of oxygen generation by plasma.Carry out selective oxidation to prevent the oxidation of metal level 47 between technology by plasma by the hydroperoxyl radical that hydrogen produces.
Even gate re-ox technology is implemented down at low temperature (being lower than 300 ℃), handle with typical heat and to compare because the high activity of the oxygen radical that uses, thus the processing time can further shorten.In addition, even gate re-ox technology is implemented down at high temperature (being higher than 300 ℃), hydroperoxyl radical and cover layer 50A also can prevent the oxidation at interface between the oxidation of metal level 47 and silicon layer 45 and the metal level 47.
As described in conjunction with an embodiment, low temperature (about 50 ℃～about 250 ℃) implement down plasma treatment (oxygen plasma) with the impurity and densification cover layer 50A that remove cover layer 50A inside after, can implement gate re-ox technology by the mist that uses oxygen-containing gas and hydrogen-containing gas down in the temperature that is higher than the plasma treatment temperature (about 700 ℃～about 900 ℃).
Though do not show, finish the process of making semiconductor device by implementing a series of typical semiconductor device manufacturing process, described process for fabrication of semiconductor device comprises for example technology and the source electrode and the drain ion injection technology of the sept oxide skin(coating) of LDD ion implantation technology, formation gate pattern 49.
Even implement high temperature (being equal to or higher than 300 ℃) technology in the oxygen atmosphere identical with finishing technology (especially forming the technology of the sept oxide skin(coating) of gate pattern 49 after the gate re-ox technology) that semiconductor device makes, cover layer 50A also can prevent the metallic pollution and the interface oxidation of silicon layer 45 contact metal layer 47 wherein.In addition, cover layer 50A can prevent the oxidation of metal level 47.
In this way, the formation of cover layer 50A can prevent in gate re-ox technology and subsequent technique the metallic pollution and the interface oxidation of silicon layer 45 contact metal layer 47 wherein.
In addition, by implementing impurity and the simultaneously densification cover layer 50A of plasma treatment, can further prevent in gate re-ox technology and subsequent technique the metallic pollution and the interface oxidation of silicon layer 45 contact metal layer 47 wherein effectively to remove cover layer 50A inside.
And, can simplified manufacturing technique by implementing plasma treatment and gate re-ox technology (that is, by in plasma atmosphere, implementing gate re-ox technology) simultaneously.
In addition, by forming cover layer 50A down, can prevent the oxidation of metal level 47 between technology at low temperature (being equal to or less than 300 ℃).
Therefore, one or more embodiment can improve the electrical characteristics and the yields of the semiconductor device that comprises the gate electrode with polysilicon metal structure.
[forming tectal method]
Fig. 6 is at the sequential chart that forms the exemplary curve of the parallel process in the above-mentioned tectal method by use ALD technology, in conjunction with exemplary.
With reference to figure 6, can form by implementing following exemplary cell circulation several times in conjunction with the above-mentioned cover layer of embodiment.
[unit circulation]
(silicon source and catalyst/cleaning/oxygen source and catalyst/cleaning)
In the unit circulation, " silicon source " is meant and injects the silicon source gas that is used to form silicon oxide layer, " cleaning " is meant the injection purge gas, " oxygen source " is meant and injects the oxygen source gas that is used to form silicon oxide layer, and " catalyst " is meant that injection is to reduce the catalyst gas of technological temperature in the technology that forms silicon oxide layer.Can control tectal gross thickness by repeating to implement unit circulation n time (wherein n is a natural number).That is, having thin thickness for example makes an appointment with
Cover layer can form by the number of times of control repetitive circulation.
More specifically, be that the chamber of 300 ℃ or lower (50 ℃～250 ℃) adsorbs the silicon source by making silicon source gas and catalyst gas flow into keep underlayer temperature.In one or more embodiment, argon gas (Ar) can be used as the carrier gas of silicon source gas and catalyst gas.
Silicon source gas can comprise and being selected from by SiCl
4, Si
2Cl
6With three (dimethylamino) silane (TDMA:(CH
3)
2N)
3SiH) a kind of in the group of Zu Chenging.Catalyst gas can comprise amino-contained (NH
2) gas.Described amino-contained gas can comprise NH
3Gas or C
5H
5N gas.
Implement cleaning to flow into N
2Thereby gas removes catalyst gas and unreacted silicon source gas.
Feasible O as oxygen source
2Silicon source and O that gas and catalyst gas flow and absorbed to order about
3Reaction between the gas, silicon oxide layer deposited on the atomic layer level thus.At this, O
3Gas is as oxidant.
Implement cleaning to flow into N
2Thereby gas removes catalyst gas, unreacted O
3Gas and byproduct of reaction.
Remove O
3Outside the gas, also can use O
2Gas, H
2O gas, NO gas or N
2O gas comes silica source as oxygen source.Remove N
2Outside the gas, also can be used as purge gas such as the inert gas of Ar gas.As another cleaning, can use vacuum pump to discharge residual gas or byproduct of reaction to outside.In forming the technology of silicon oxide layer, can form plasma atmosphere and do not use catalyst gas, to reduce technological temperature.Plasma atmosphere can be by using argon gas (Ar) or nitrogen (N
2) form.The two can be used for reducing technological temperature catalyst gas and plasma atmosphere.
The cover layer of describing in conjunction with embodiment can form by above-mentioned technology.
By using ALD technology or PEALD technology, can on the resulting structures that is comprising gate pattern under the low temperature (being equal to or less than 300 ℃), form the cover layer of homogeneous thickness.
In addition, by using catalyst gas or plasma atmosphere, forming tectal temperature can reduce.Therefore, in forming tectal technology, can prevent the oxidation of metal level effectively.
[effect]
Fig. 7 is the data point diagram on the curve of the metallic pollution degree that whether exists according to cover layer of explanation.Adopt secondary ion mass spectroscopy (SIMS) not form therein in the zone of electrode of polysilicon metal structure and measure tungsten (W) pollution level.
As seen from Figure 7, the metallic pollution degree that wherein forms tectal embodiment is starkly lower than and does not wherein form tectal embodiment.
Fig. 8 A and 8B explanation comprise the polysilicon metal interface of the semiconductor device of gate electrode, and described gate electrode has according to the tectal polysilicon metal structure of having of above-mentioned one or more embodiments.Particularly, Fig. 8 A is the cross-section photograph at interface between polysilicon (poly-Si) layer and tungsten (W) layer, and Fig. 8 B is that explanation is analyzed data point and the correlogram of the exemplary analysis result of component between polysilicon layer and the tungsten layer by using electron energy loss spectroscopy (EELS) (EELS).Though not clear demonstration forms the tungsten nitride (WN as diffusion impervious layer between tungsten layer and polysilicon layer
X) layer.
As above described with reference to figure 3A and 3B, comprise not having the typical gate electrode of tectal polysilicon metal structure that following problem is arranged: because after gate re-ox technology, the interface oxidation of polysilicon layer contact tungsten layer has silica (SiO so form
x) dielectric layer of component.
Yet,, as have shown in Fig. 8 A and 8B of the gate electrode that comprises tectal polysilicon metal structure the dielectric layer that not have generation to have the silica component after the gate re-ox technology according to one or more embodiment.Therefore, one or more embodiment can prevent the increase of gate electrode vertical resistor, prevents thus in high frequency signal delay in service.
With reference to the EELS figure of Fig. 3 B that shows polysilicon metal interface component analysis result and 8B, nitrogen (N) component comes from the tungsten nitride (WN as the diffusion impervious layer that forms between polysilicon layer and tungsten layer
X) layer.
Fig. 9 A and 9B are the measurement result figure of explanation according to the cover layer component of one or more embodiments.Particularly, Fig. 9 A comprises the curve chart of electric capacity (C/Cox) to voltage (V) measurement result, and Fig. 9 B comprises the curve chart of current density to the electric field measurement result.Cover layer (the O of the oxide skin(coating) (thermal oxide) that forms by thermal oxidation technology, the oxide skin(coating) (LP-CVD oxide), cover layer (former state deposition, As Dep) and the oxygen plasma treatment that form by low-pressure chemical vapor deposition process
2Plasma oxide) in each curve, contrasts each other, and comparing result is mapped.Clearly show tectal some advantage according to one or more embodiment.
Can find out by Fig. 9 A, according to the cover layer (O of the oxygen plasma treatment of one or more embodiment
2Plasma oxide) has and be similar to the common known electrical characteristics that form by thermal oxidation technology with oxide skin(coating) (thermal oxide) of superperformance.
Can find out by Fig. 9 B, compare with the oxide skin(coating) (LP-CVD oxide) that the holder low-pressure chemical vapor deposition process forms, according to the cover layer (O of the oxygen plasma treatment of one or more embodiment with the cover layer (As Dep) of non-oxygen plasma treatment
2Plasma oxide) has excellent more resistance to electric field.
Though, for instance, be used to comprise the semiconductor device of the gate electrode with polysilicon metal structure according to the know-why of embodiment, it is evident that: theme of the present invention also can be used to comprise any semiconductor device of the electrode with polysilicon metal structure.
By forming cover layer, can prevent in gate re-ox technology and subsequent technique (the especially high temperature in oxygen atmosphere (300 ℃ or higher) technology) metallic pollution and the interface oxidation of silicon layer contact metal layer wherein.
By removing impurity and the densification cover layer simultaneously in the cover layer, can further prevent in gate re-ox technology and subsequent technique the metallic pollution and the interface oxidation of silicon layer contact metal layer wherein effectively.
By in plasma atmosphere, implementing gate re-ox technology, can remove the described layer of impurity, densification in the cover layer.In addition, can implement gate re-ox technology simultaneously.Therefore, can simplify production process of semiconductor device.
By forming cover layer down, can prevent to form the oxidation of metal level in the technology at cover layer at low temperature (being equal to or less than 300 ℃).
Therefore, can improve the electrical characteristics and the yields of the semiconductor device that comprises gate electrode with polysilicon metal structure.
Though described embodiment, those skilled in the art can make various variations and change apparently.
Claims (28)
1. method of making semiconductor device, described method comprises:
On substrate, form gate-dielectric;
Form grid structure on described gate-dielectric, described grid structure comprises the stack layer of silicon layer and metal level;
Optionally the described grid structure of etching is to form gate pattern;
Form the cover layer that surrounds described gate pattern;
The described cover layer of plasma treatment; With
Implement gate re-ox technology.
2. method according to claim 1, wherein the described cover layer of plasma treatment is by using oxygen (O
2) plasma implements.
3. method according to claim 1, wherein the described cover layer of plasma treatment comprises:
By using inert gas in chamber, to form plasma; With
Make oxygen (O
2) flow into the described chamber wherein form described plasma.
4. method according to claim 1, wherein the described cover layer of plasma treatment is implemented under the temperature that is lower than described gate re-ox technological temperature.
5. method according to claim 4, wherein the described cover layer of plasma treatment is implemented under about 50 ℃～about 250 ℃ temperature.
6. method according to claim 4, wherein said gate re-ox technology is implemented under about 700 ℃～about 900 ℃ temperature.
7. method according to claim 1, wherein said gate re-ox technology is implemented by the mist that uses oxygen-containing gas and hydrogen-containing gas.
8. method according to claim 7, wherein said oxygen-containing gas comprises H
2O gas or O
2Gas, described hydrogen-containing gas comprises H
2Gas.
9. method according to claim 1, wherein said cover layer forms under about 50 ℃～about 250 ℃ temperature.
10. method according to claim 9, wherein said cover layer comprises silicon oxide layer.
11. method according to claim 1 wherein forms described cover layer by ald (ALD) technology or plasma enhanced atomic layer deposition (PEALD) technology.
12. method according to claim 1 wherein forms described cover layer and comprises:
With the described substrate that is formed with described gate pattern on it chamber of packing into;
Make silicon source gas flow into described chamber;
Clean described silicon source gas;
Make oxygen source gas flow into described chamber; With
Clean described oxygen source gas.
13. comprising, method according to claim 12, wherein said silicon source gas be selected from by Si
2Cl
6, SiCl
4In the group of forming with three (dimethylamino) silane (TDMS) any one.
14. comprising, method according to claim 12, wherein said oxygen source gas be selected from by O
2, O
3, NO, N
2O and H
2In the group that O forms any one.
15. method according to claim 12 wherein flows described silicon source gas and described oxygen source gas by making the gas that comprises amido flow into described chamber with described silicon source gas and described oxygen source gas.
16. method according to claim 15, wherein said amino-contained gas comprises NH
3Gas or C
5H
5N gas.
17. method according to claim 12, wherein said cover layer forms in plasma atmosphere.
18. method according to claim 17 is wherein by using argon gas or nitrogen to form described plasma atmosphere.
19. comprising, method according to claim 1, wherein said metal level be selected from the group of forming by tungsten (W), molybdenum (Mo), tantalum (Ta), titanium (Ti), ruthenium (Ru), iridium (Ir) and platinum (Pt) any one.
20. method according to claim 1, wherein said grid structure comprises: comprise the stack layer of the silicon layer, metal level and the gate hard mask layer that stack gradually, or comprise the stack layer of the charge storage layer, dielectric layer, silicon layer, metal level and the gate hard mask layer that stack gradually.
21. method according to claim 20, wherein said charge storage layer comprises silicon layer or dielectric layer.
22. a method of making semiconductor device, described method comprises:
On substrate, form gate-dielectric;
Form grid structure on described gate-dielectric, described grid structure comprises the stack layer of silicon layer and metal level;
Optionally the described grid structure of etching is to form gate pattern;
Form the cover layer that surrounds described gate pattern;
The described cover layer of plasma treatment; With
In plasma atmosphere, implement gate re-ox technology.
23. method according to claim 22 is wherein implemented described gate re-ox technology and is comprised:
By using inert gas in chamber, to form plasma; With
Make the mist of oxygen-containing gas and hydrogen-containing gas flow into the described chamber that wherein forms described plasma.
24. method according to claim 23, wherein said oxygen-containing gas comprises H
2O gas or O
2Gas, described hydrogen-containing gas comprises H
2Gas.
25. method according to claim 22, wherein said gate re-ox technology is implemented under about 200 ℃～about 900 ℃ temperature.
26. a semiconductor device comprises:
The gate-dielectric that on substrate, forms;
The gate pattern structure that on described gate-dielectric, forms, described gate pattern structure comprises the stack layer of silicon layer and metal level; With
Surround the cover layer of described gate pattern structure.
27. method according to claim 26, wherein said gate pattern structure comprises: comprise the stack layer of the silicon layer, metal level and the gate hard mask layer that stack gradually, or comprise the stack layer of the charge storage layer, dielectric layer, silicon layer, metal level and the gate hard mask layer that stack gradually.
28. semiconductor device according to claim 27, wherein said charge storage layer comprises silicon layer or dielectric layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080063183 | 2008-06-30 | ||
| KR20080063183 | 2008-06-30 | ||
| KR1020080098625 | 2008-10-08 |
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| Publication Number | Publication Date |
|---|---|
| CN101621010A true CN101621010A (en) | 2010-01-06 |
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ID=41514168
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910008580A Pending CN101621010A (en) | 2008-06-30 | 2009-02-03 | Semiconductor device and method of fabricating the same |
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| Country | Link |
|---|---|
| KR (1) | KR101036928B1 (en) |
| CN (1) | CN101621010A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856259A (en) * | 2011-07-01 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN113025991A (en) * | 2021-02-26 | 2021-06-25 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101259551B1 (en) * | 2011-06-09 | 2013-04-30 | 연세대학교 산학협력단 | Flash memory device including tunnel insulation layer of high dielectric and method for fabricating the same |
| KR101813513B1 (en) | 2011-11-30 | 2018-01-02 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing semiconductor devices |
| KR102342850B1 (en) | 2015-04-17 | 2021-12-23 | 삼성전자주식회사 | Curing method of dielectric layer for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2004262508A1 (en) * | 2003-03-24 | 2005-02-17 | Wellstat Biologics Corporation | Newcastle disease virus administration |
| KR20060021794A (en) * | 2004-09-04 | 2006-03-08 | 삼성전자주식회사 | Method for manufacturing semiconductor device |
| KR20060100092A (en) * | 2005-03-16 | 2006-09-20 | 삼성전자주식회사 | Method for manufacturing a semiconductor device |
-
2008
- 2008-10-08 KR KR1020080098625A patent/KR101036928B1/en not_active IP Right Cessation
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856259A (en) * | 2011-07-01 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN113025991A (en) * | 2021-02-26 | 2021-06-25 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN113025991B (en) * | 2021-02-26 | 2022-07-22 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20100003164A (en) | 2010-01-07 |
| KR101036928B1 (en) | 2011-05-25 |
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