CN101610435A - Queue-type all-optical buffer - Google Patents
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Abstract
Queue-type all-optical buffer belongs to full light packet switch field, it is characterized in that: queue-type all-optical buffer is formed by a plurality of smooth buffer unit cascades, and the up output of smooth buffer units at different levels links to each other successively with higher level's descending input, constitutes data feedback channel.The packet that is input to smooth buffer units at different levels is by the last line output of signal input end decision or at buffer memory at the corresponding levels.The control signal output ends of any i level light buffer unit is connected to the signal input end of i+1 level light buffer unit, and avoiding has data cached Bao Shidi i+1 level light buffer unit to i level light buffer unit dateout in i level light buffer unit.When two packets arrived buffer memory simultaneously, the packet that priority is high was directly exported, and the packet that priority is low deposits buffer memory in.The queue-type all-optical buffer that the present invention proposes has first-in first-out, after the formation characteristics that go out after going into, can handle two packets simultaneously, have memory capacity and easily expand, need not advantages such as outer increase control signal.
Description
Technical field
The invention belongs to information photoelectron technology field, the full optical buffer in the particularly full light packet network.
Background technology
In recent years, optical communication network develops rapidly, along with the sharp increase of bandwidth demand, at a high speed, flexible and good extensibility becomes the developing direction of optical-fiber network of future generation day by day.Modern optical networks no longer contents just to utilize optical fiber transmission signal, and the work that some were finished in electric territory after opto-electronic conversion originally as exchange, route, storage, forwarding etc., is introduced in the light territory just gradually, and the method for utilizing full light signal to handle realizes.Wherein, full light packet technology owing to can be directly in the light territory to packet exchange, operation such as route is considered to one of all-optical network solution of tool potentiality.
Full optical buffer by storage and the forwarding to the light packet, can solve the data packet collisions problem as the core devices of full light packet technology on time domain.If there are two packets to arrive certain port simultaneously, they can be aliasing in together, cause loss of data, this is called data packet collisions, if certain packet elder generation's buffer memory a period of time is exported again with buffer, just can make two packets successively by this port, avoided the generation of data packet collisions.Than electric buffer, the full optical buffer access speed is fast, transparent to modulation format and data transfer rate, control is flexible, has caused extensive studies interest.
The full optical buffer that present stage is reported both at home and abroad mainly is divided into two big classes, through-type and feedback cycle type.
For through-type optical buffer, its cache-time can't be controlled flexibly.In case the length of optical fiber or slow optical wave guide determines that cache-time is just fixing, can not do dynamic adjustment according to network traffic data.Promptly allow to adjust, must be when not having data traffic, by manually carrying out yet.Therefore, through-type buffer has only been realized the time-delay of packet, does not have realization storage and forwarding truly.If network traffic data is very big, need cache-time very long, the buffer based on slow optical wave guide just is difficult to be competent at so; And if with optical fiber as the buffer memory medium, need very long optical fiber again, cause buffer structure bulky complex.The advantage of through-type buffer is that to being buffered data packet length without limits, the signal-to-noise ratio degradation of packet is also smaller behind buffer memory.
For feedback cycle type buffer, it can really realize the storage and the forwarding of packet according to the depositing in and reading of network traffic data determination data bag.Cache-time can increase cache-time by increasing cycle-index by ring cavity length and cycle-index decision, and physics realization is simpler than through-type buffer memory, and required components and parts also significantly reduce.But the circulation feedback type full optical buffer of report all has only the one-level storage depth at present, can only store a packet, and capacity can't be expanded.And most of special control signal that need be extra, that have even need the signal of telecommunication, make buffer become the photoelectricity mixed type by full light type, and can not be according to the cache-time of network traffic data Based Intelligent Control packet, flexibility and extensibility all are restricted.
Because the pluses and minuses of above two types full optical buffer, a kind of research of intelligentized full optical buffer is extensively carried out, its can be automatically according to the storage and the forwarding of network traffic data determination data bag, utilize packet itself just can directly control, and do not need outer increase control signal it.The H.J.S.Dorren group of Holland PSV Eindhoven Polytechnics has proposed a kind of buffering scheme (Y.Liu based on full light monostable flipflop and wavelength shifter, M.T.Hill, et.al., " Demonstration of a variable optical delay fora recirculating buffer by using all-optical signal processing ", IEEE Photon.Technol.Lett., vol.16, pp.1748-1750,2004.).When two packets arrived certain port simultaneously, the packet that priority is high was directly exported, and the packet that priority is low is buffered in the ring cavity, just exported when the port free of data is conflicted.This scheme does not need outer increase control signal, and is simple in structure, but has only the one-level storage depth, can only deposit a packet.On this basis, our laboratory seminar has applied for " stack type whole optical caching device " (patent: Wang Jing, Zhang Hongming, Fu Xin Yao Minyu), has proposed a kind of stack type whole optical caching device, can utilize the read-write of packet control buffer itself, and memory capacity can be expanded.
But stack type whole optical caching device also has its shortcoming: the first, stack type whole optical caching device structurally be go into afterwards earlier, after go into the nesting structural embedded control that goes out earlier, this has just caused when network is busy, after the packet output earlier sometimes of arriving; Second, be equally because go into afterwards earlier, after go into the nesting structural embedded control that goes out earlier, originally the packet that was buffered can shift at the bottom of stack, and shifts the signal to noise ratio all can worsen packet each time, so the situation that the packet that arrives constantly for difference when busy of network worsens is different; The 3rd, at least 6 active devices of a packets need of buffer memory, the complexity of system and cost are than higher.
In order to solve three problems above-mentioned, the present invention is on the basis of stack type whole optical buffering scheme, a kind of queue-type all-optical buffer has been proposed, be first-in first-out on the structure, after the queue-type structure that goes out after going into, any moment all is that the packet that arrives first goes out team earlier, after to packet after go out team, for the signal-to-noise ratio degradation situation basically identical of packet, and packet of buffer memory reduced by 2 active devices, reduced the complexity and the cost of system when network was busy.The present invention simultaneously is also the same with stack type whole optical caching device to have the read-write that can utilize packet control buffer itself, and the extendible characteristics of memory capacity.
Summary of the invention
The present invention proposes a kind of queue-type all-optical buffer, formed by a plurality of smooth buffer unit cascades, is a kind of first-in first-out, after the queue-type storage organization that goes out after going into.Each light buffer unit contains light buffer memory control sub unit, first wavelength shifter and control signal preprocessor.Light buffer memory control sub unit contains full light monostable flipflop, wavelength division multiplexer MUX, second wavelength shifter and the demodulation multiplexer DEMUX that connects successively.Each light buffer unit has two data terminals, promptly descending input and up output, and two control signal ends, i.e. signal input end and control signal output ends.
The invention is characterized in, form by the cascade of I level light buffer unit, i=1,2, I, it is a kind of first-in first-out, after the queue-type buffer that goes out after going into, described queue-type all-optical buffer has two inputs and an output, the priority height of first input end 1 wherein, and the priority of second input 2 is low, described first input end 1 is divided into two-way through a coupler: one road input signal arrives output through behind another coupler, another road is connected to the signal input end of the 1st grade of described smooth buffer unit by the 0th grade of control signal preprocessor, i=1, described second input 2 are connected to the descending input of the light buffer memory control sub unit of described queue-type all-optical buffer bottom, wherein:
Described smooth buffer unit i at different levels contains light buffer memory control sub unit, first wavelength shifter and control signal preprocessor, wherein:
Light buffer memory control sub unit contains full light monostable flipflop, wavelength division multiplexer MUX, second wavelength shifter and the demodulation multiplexer DEMUX that connects successively, wherein:
Full light monostable flipflop, its signal input end links to each other with the control signal output ends of i-1 level light buffer unit,
Wavelength division multiplexer MUX has two inputs, an output: the wavelength of first input end and described full light monostable flipflop is λ
IAThe direct current light output end link to each other, and the wavelength of second input and described full light monostable flipflop is λ
IBThe direct current light output end link to each other, the selection of its medium wavelength makes λ
IAWith λ
IBDifference,
Second wavelength shifter, a data input, a data output and a direct current light input end are arranged, wherein the direct current light input end links to each other with the output of described wavelength division multiplexer MUX, and the descending input of described smooth buffer unit i is coupled with the data output end of first wavelength shifter of described smooth buffer unit i and links to each other with the data input pin of described second wavelength shifter
Demodulation multiplexer DEMUX, its input links to each other with the data output end of described second wavelength shifter, and described demodulation multiplexer DEMUX has two outputs, and one is up output, links to each other with the descending input of the described smooth buffer unit of i-1 level, and output wavelength is λ
IAFlashlight, another output output wavelength is λ
IBFlashlight, be divided into two-way through after the fiber delay time: be connected to control signal output ends behind the control signal preprocessor of the first via by described i level light buffer unit, be sent to the signal input end of the described smooth buffer unit of i+1 level, also promptly in the described full light monostable flipflop in the described smooth buffer memory control sub unit of the described smooth buffer unit of i+1 level, the second tunnel is connected to the data input pin of described first wavelength shifter of described i level buffer unit;
First wavelength shifter has a data input, a data output and a direct current light input end, and wherein to import a wavelength be λ to the direct current light input end
ICDirect current light, λ wherein
ICSelection make λ
ICWith λ
IAAnd λ
IBAll different, the described demodulation multiplexer DEMUX output wavelength of the described smooth buffer memory control sub unit of described i level light buffer unit is λ
IBThe output of flashlight is through being divided into two-way after the fiber delay time, wherein one the tunnel links to each other with the data input pin of described first wavelength shifter, the be coupled data input pin of described second wavelength shifter of the described smooth buffer memory control sub unit that is connected to described i level light buffer unit of the descending input of the data output end of described first wavelength shifter and described i level light buffer unit;
The control signal preprocessor has an input and an output, and the described demodulation multiplexer DEMUX output wavelength of the described smooth buffer memory control sub unit of described i level light buffer unit is λ
IBThe output of flashlight is through being divided into two-way after the fiber delay time, one tunnel input that is connected to described control signal preprocessor wherein, the output of described control signal preprocessor is connected to the signal input end of the described smooth buffer unit of i+1 level as the control signal output ends of described i level light buffer unit, also promptly in the described full light monostable flipflop of the described smooth buffer memory control sub unit of the described smooth buffer unit of i+1 level;
As packet in described i level light buffer unit during buffer memory, can be input to the signal input end of the described smooth buffer unit of i+1 level simultaneously through the control signal that produces behind the control signal preprocessor at the same level by described packet, close its data feedback channel, stop the described smooth buffer unit of i+1 level to the up dateout bag of described i level light buffer unit, prevent that packet is overlapping in the described i level light buffer unit, otherwise, when packet exported described i level light buffer unit to from the described smooth buffer unit of i+1 level is up, described i level light buffer unit did not have packet at this moment.
The invention has the advantages that:
1. the conflict of two packets be can handle, can memory time and storage depth in the buffer queue be wrapped in according to network busy extent determination data;
2. memory capacity is easily expanded, and system complexity only increases with memory capacity is linear;
3. directly with the read-write of packet control buffer memory itself, need not to add special control signal;
4. with respect to stack type whole optical caching device, packet of buffer memory has reduced the quantity of required active device;
5. with respect to stack type whole optical caching device, first-in first-out, after different these two problems of signal-to-noise ratio degradation degree of the data pack buffer overlong time that arrived earlier for second input when having avoided network busy of the queue-type storage organization that goes out after going into and the packet that arrives constantly for difference.
Description of drawings:
Fig. 1. queue-type all-optical buffer overall structure figure is formed by a plurality of smooth buffer unit cascades:
1.1 the light buffer unit, 1.2 full optical buffer The general frame.
Fig. 2. with storage depth is that 3 queue-type all-optical buffer is an example, if have from the first packet packet1 of described first input end 1 and from the second packet packet2 of described second input 2, and the packet of former queue-type all-optical buffer in first order light buffer unit is when being packet0, the described first packet packet1 couples directly to the straight-through output of output of described queue-type all-optical buffer, leaves buffer (solid line); The described second packet packet2 goes upward to second level light buffer unit after entering described queue-type all-optical buffer always, buffer memory in the buffer unit of the second level (chain-dotted line); Described packet packet 0 continues buffer memory (dotted line) in first order unit; Packet 1 output, packet 2 deposits buffer memory in, and packet 0 continues buffer memory, packet 0 output earlier when exporting later on, packet 2 back outputs; " √ " expression has control signal, and " * " expression does not have control signal.
Fig. 3. with storage depth is that 3 queue-type all-optical buffer is an example, if described first input end 1 has the first packet packet1, described second input, 2 free of data bags input, and the packet of former queue-type all-optical buffer in first order light buffer unit is when being packet0, buffer (solid line) is left in the described first packet packet 1 straight-through output; Described packet packet 0 continues buffer memory (dotted line); " √ " expression has control signal, and " * " expression does not have control signal.
Fig. 4. with storage depth is that 3 queue-type all-optical buffer is an example, if described first input end 1 free of data bag input, described second input 2 has packet packet2 input, and the packet of former queue-type all-optical buffer in first order light buffer unit is when being packet0, the up output that exports described queue-type all-optical buffer to of described packet packet0 leaves buffer (dotted line); The described second packet packet2 is buffer memory one-period (chain-dotted line) in the light buffer unit of the described second level; " √ " expression has control signal, and " * " expression does not have control signal.
Fig. 5. with storage depth is that 3 queue-type all-optical buffer is an example, described first input end 1, second input 2 be free of data bag when input all, packet packet0 in the then former queue-type all-optical buffer first order light buffer unit outputs to the output of described queue-type all-optical buffer from the up output of described first order light buffer unit, leaves buffer (dotted line); " √ " expression has control signal, and " * " expression does not have control signal.
Fig. 6. the inner detailed structure of light buffer unit, wherein light buffer memory control sub unit comprises full light monostable flipflop, All Optical Wave Converter, wavelength division multiplexer MUX and demodulation multiplexer DEMUX.
Fig. 7. full light monostable flipflop, form by the SOA optical fiber ring laser of two couplings, two states are arranged, a stable state, a unstable state.
Fig. 8. All Optical Wave Converter comprises two All Optical Wave Converter, i.e. first wavelength shifter and second wavelength shifter in each grade light buffer unit.
Fig. 9. based on the control signal pretreatment module of Mach-Zehnder interferometers:
9.1 structure chart, 9.2 effect schematic diagrames.
Figure 10. based on the control signal pretreatment module of full optical bistability trigger:
10.1 structure chart, 10.2 effect schematic diagrames.
Embodiment
Key of the present invention is, whether the light buffer memory control sub unit in the described smooth buffer unit is used for the control data bag will carry out buffer memory, when control signal was added in the signal input end of light buffer unit, packet is buffer memory in the light buffer unit, otherwise then by the upwards output of up output.The wavelength of demodulation multiplexer DEMUX is λ in the described smooth buffer memory control sub unit
IAOutput constitute the up output of described smooth buffer unit, and another wavelength is λ
IBOutput through being divided into two-way after the time delay optical fiber, wherein one the tunnel becomes λ through first wavelength shifter with wavelength Conversion
ICBe coupled with the descending input of described smooth buffer unit afterwards and be connected to the data input pin of second wavelength shifter in the described smooth buffer memory control sub unit, other one the tunnel through constituting described smooth buffer unit control signal output ends after the control signal preprocessor.The control end of full light monostable flipflop constitutes the signal input end of described smooth buffer unit in the described smooth buffer memory control sub unit.Above-mentioned two data ports, promptly descending input and up output constitute two data terminals of described smooth buffer unit, and two control end correspondences the control signal output ends and the input of light buffer unit.Packet is input to the light buffer unit from described descending input, exports or buffer memory in the light buffer unit from up output.When the signal input end no signal, the packet that enters the light buffer unit is exported from up output, on the contrary buffer memory in the light buffer unit then.
Described queue-type all-optical buffer has two inputs and an output, the priority height of first input end 1, and the priority of second input 2 is low.1 fen two-way of described first input end, the one tunnel couples directly to described output, and another road is connected to the signal input end of first order light buffer unit through the control signal preprocessor.Described second input 2 is connected to the descending input of queue-type all-optical buffer bottom light buffer memory control sub unit.Described output is coupled to form by two-way, respectively from the up output of described first input end 1 and first order light buffer unit.
In described queue-type all-optical buffer, any i level light buffer unit constitutes level cache separately.The up output of i+1 level light buffer unit is connected to the descending input of i level light buffer unit, and the recursion that makes progress step by step successively constitutes buffer memorys at different levels, and forms data feedback channel.The control signal output ends of any i level light buffer unit is connected to the signal input end of i+1 level light buffer unit.As packet in i level light buffer unit during buffer memory, can be input to the signal input end of i+1 level light buffer unit simultaneously by the control signal that produces behind the described packet process control signal preprocessor, close its data feedback channel, stop i+1 level light buffer unit to the up dateout bag of i level light buffer unit, prevent packet aliasing in the i level light buffer unit.Otherwise, when packet exports i level light buffer unit to from i+1 level light buffer unit is up, the signal input end that i+1 level light buffer unit is described does not necessarily have control signal, promptly there is not packet in the i level light buffer unit, so do not have the packet aliasing in the i level light buffer unit.
Suppose to have in the first order buffer unit in the original queue-type all-optical buffer packet packet 0 to exist:
When described first input end 1, second input 2 have the first packet packet 1, the second packet packet, 2 inputs respectively, the described first packet packet 1 couples directly to output, straight-through output, the described second packet packet 2 enters the descending input that always is up to second level light buffer unit behind the buffer.Because of the described first packet packet 1 is input to the signal input end of described first order light buffer unit after through the 0th grade of control signal preprocessor, so described former packet packet 0 buffer memory in first order light buffer unit still.First order light buffer unit control signal output ends has signal to be connected to the signal input end of second level light buffer unit, and the described second packet packet 2 enters behind the buffer unit of the second level at the unit inner buffer.
Import when described first input end 1 has the first packet packet 1, during the input of second input, 2 free of data bags, the described first packet packet 1 couples directly to output, straight-through output.On the other hand, because of the signal input end of described first order light buffer unit has the control signal input that is formed by the described first packet packet 1, so described former packet packet 0 continues buffer memory.
When described first input end 1 free of data bag input, when second input 2 has the second packet packet, 2 inputs, because of the signal input end no signal of first order light buffer unit, described former packet packet 0 is left buffer by line output on the first order light buffer unit.On the other hand, be input to second level light buffer unit signal input end because of first order light buffer unit control signal output ends has signal, the described second packet packet 2 by the input of second input 2 enters behind the light buffer unit of the second level buffer memory one-period in the unit.
When described first input end 1, the second input 2 free of data bag whens input all, the signal input end of described first order light buffer unit is no signal all, and described former packet packet 0 is left buffer by line output on the first order light buffer unit.
The present invention proposes the queue-type all-optical buffer that a kind of memory capacity can be expanded continuously, can handle two packets that arrive described buffer simultaneously, and can determine memory time and storage depth flexibly according to the depositing in and reading of network traffic data Based Intelligent Control packet.Its system block diagram is formed by a plurality of smooth buffer unit cascades as shown in Figure 1, is a kind of first-in first-out, after the queue stores structure that goes out after going into.The buffer memory of packet is to realize by the time delay optical fiber in the smooth buffer units at different levels.
Shown in Fig. 1 .1, every grade of light buffer unit has 1 signal input end, 1 control signal output ends, and 2 data terminals are respectively descending input and up output.The up output of smooth buffer units at different levels links to each other successively with the descending input of higher level's light buffer unit, constitutes data feedback channel.There is time delay optical fiber to be used to realize the buffer memory of packet in smooth buffer units at different levels inside.The control signal output ends of smooth buffer units at different levels links to each other with the signal input end of subordinate's light buffer unit.The packet of importing every grade of light buffer unit is determined from up output output or at light buffer unit inner buffer at the corresponding levels by signal input end.When the signal input end no signal, packet is exported from up output; When signal input end had signal, packet was at light buffer unit inner buffer at the corresponding levels.
As Fig. 1 .2, the up output of i+1 level light buffer unit links to each other with the descending input of i level light buffer unit, the control signal output ends of i level light buffer unit links to each other with the signal input end of i+1 level light buffer unit, is used for preventing the last line output and the interior cached data packet aliasing of i level light buffer unit of i+1 level light buffer unit.When in the i level light buffer unit packet being arranged, can be input to the signal input end of i+1 level light buffer unit behind this packet process control signal preprocessor simultaneously, close its data feedback channel, stop i+1 level light buffer unit to the up dateout bag of i level light buffer unit, thereby prevented the aliasing of packet in the i level light buffer unit.Otherwise, when packet exports i level light buffer unit to from i+1 level light buffer unit is up, the signal input end that i+1 level light buffer unit is described does not necessarily have control signal, i.e. free of data bag in the i level light buffer unit is not so have the packet aliasing in i level light buffer unit.Like this, in every grade of light buffer unit a packet can only be arranged, this packet is from the descending input of light buffer unit or be buffered in packet in the light buffer unit at the corresponding levels; Also can only export a circuit-switched data, promptly go up line output.
Whole queue-type all-optical buffer has two inputs, and an output can be handled two packets that arrive queue-type all-optical buffer simultaneously.The priority of first input end 1 is higher, and the priority of second input 2 is lower.1 fen two-way of first input end, the one tunnel couples directly to the output of queue-type all-optical buffer, and another road is connected to the signal input end of first order light buffer unit by the 0th grade of control signal preprocessor.2 of second inputs are connected to the descending input of the light buffer memory control sub unit of queue-type all-optical buffer bottom.The output of queue-type all-optical buffer is coupled to form by two-way, respectively from the up output of first input end 1 and first order light buffer unit.When first input end 1 and second input 2 all have packet to arrive, only to carrying out buffer memory from the low packet of the priority of second input 2, to from the high packet of the priority of first input end 1, then straight-through output, not buffer memory.
Supposing that the packet from first input end 1 is packet 1, is packet 2 from the packet of second input 2, and the packet that originally was buffered in the first order light buffer unit is packet 0.Wherein packet 0 is positioned at the top of whole queue-type all-optical buffer because of being in first order light buffer unit, is called team's packet again.Have or not the packet input respectively with regard to the first input end 1 and second input 2 below, divide four kinds of situation discussion.
As Fig. 2, when first input end 1 and second input 2 had the first packet packet 1, the second packet packet, 2 inputs respectively, the described first packet packet 1 coupled directly to output, is led directly to output, shown in solid line; The described second packet packet 2 enters the descending input that queue-type all-optical buffer goes upward to second level light buffer unit afterwards always.Because of the described first packet packet 1 also is input to the signal input end of first order light buffer unit simultaneously by the 0th grade of control signal preprocessor,, shown in dotted line so described former packet packet 0 continues buffer memory in first order light buffer unit.Output to the signal input end of second level light buffer unit because of first order light buffer unit has control signal in addition, the then described second packet packet 2 is at second level light buffer unit inner buffer, and not upwards output is shown in chain-dotted line.So the described first packet packet 1 is directly exported, the described second packet packet 2 deposits second level light buffer unit in, and described former packet packet 0 deposits first order light buffer unit in.When exporting in the future, described former packet packet 0 goes out team earlier, goes out team behind the described second packet packet 2, meets first-in first-out, after the formation characteristics that go out after going into.
As Fig. 3, when having the first packet packet 1, first input end 1 imports, and during the input of second input, 2 free of data bags, the described first packet packet 1 couples directly to output, and straight-through output is shown in solid line.On the other hand, because of the signal input end of first order light buffer unit has the control signal input, described former packet packet 0 continues buffer memory, and is shown in dotted line.
As Fig. 4, when the input of first input end 1 free of data bag, when second input 2 has second packet packet2 input, because of the signal input end of first order light buffer unit does not have control signal, described former packet packet 0 is by line output on the first order light buffer unit, leave buffer, shown in dotted line.On the other hand, the signal input end of second level light buffer unit has control signal, and the described second packet packet 2 buffer memory one-period in the light buffer unit of the second level is shown in chain-dotted line.
As Fig. 5, when the first vocal input end 1 and second input 2 all during the input of free of data bag, then the signal input end of first order light buffer unit does not have control signal, and described former packet packet 0 is by line output on the first order light buffer unit, leave buffer, shown in dotted line.
The inside detailed structure of light buffer unit as shown in Figure 6, the light buffer unit is made up of light buffer memory control sub unit, first wavelength shifter and control signal preprocessor.Wherein light buffer memory control sub unit is by full light monostable flipflop, second wavelength shifter, and wavelength division multiplexer MUX and demodulation multiplexer DEMUX form, and three data terminals and a signal input end are arranged.The wavelength of demodulation multiplexer DEMUX is λ
IAOutput constitute the up output of light buffer memory control sub unit, wavelength is λ
IBOutput constitute the descending output of light buffer memory control sub unit, this output is divided into two-way in the light buffer unit, one tunnel process control signal preprocessor is connected to control signal output ends, and the descending input of another Lu Yuguang buffer unit is coupled together and is connected to the descending input of light buffer memory control sub unit.The input of second wavelength shifter constitutes the descending input of light buffer memory control sub unit.Packet is input to light buffer memory control sub unit from descending input, from up output output or continuation buffer memory in the light buffer unit.The control end of full light monostable flipflop constitutes the signal input end of light buffer memory control sub unit.Full light monostable flipflop has two states, when control end does not have light signal, is in stable state; When control end has signal, be in unstable state.For i level unit, full light monostable flipflop output wavelength λ during stable state
IADirect current light; During unstable state, output wavelength λ
IBDirect current light.These two direct current light are input to second wavelength shifter through wavelength division multiplexer MUX coupling.By as can be known preceding, second wavelength shifter of each grade light buffer memory control sub unit receives only in the cached data packet in the packet of descending input input of light buffer unit at the corresponding levels or the light buffer unit at the corresponding levels.When the control input end of light buffer unit did not have control signal, full light monostable flipflop was in stable state, output λ
IADirect current light, to be converted to wavelength be λ to second wavelength shifter the input data
IAPacket, go up line output through demodulation multiplexer DEMUX; When there was control signal the control input end of light buffer unit, full light monostable flipflop was in unstable state, output λ
IBDirect current light, to be converted to wavelength be λ to wavelength shifter the input data
IBPacket, line output under demodulation multiplexer DEMUX continues buffer memory in light buffer unit at the corresponding levels.
Full light monostable flipflop as shown in Figure 7.Full light monostable flipflop is made up of two SOA optical fiber ring lasers that are coupled, SOA (Semiconductor Optical Amplifier, semiconductor optical amplifier) makes gain media, isolator makes the light one-way transmission, and band pass filter (BPF:Band Pass Filter) is selected wavelength.The bias current of SOA 1 is bigger than SOA 2, so ratio of gains ring 2 height of ring 1, ring 1 can swash to be penetrated.The output light of SOA 1 enters ring 2 through coupler, consumes the charge carrier of SOA 2, makes ring 2 can not get enough gains, can not swash and penetrate.This ring 1 swashs to be penetrated, and encircles the stable state that 2 repressed states are called full light monostable flipflop.Ring 1 output wavelength λ under the stable state
IADirect current light, encircle 2 no-outputs.If, then control the charge carrier that light can consume SOA 1 from DC control light of control end input, the gain of ring 1 is reduced, the light that is coupled to ring 2 from SOA 1 also can reduce.When control light was enough strong, ring 1 no longer can suppress to encircle 2, and ring 2 enters to swash penetrates attitude, and the output of SOA 2 is optically coupled into SOA 1 and extraneous control light suppresses to encircle 1 together, it can not be swashed penetrate.This under the assistance of external world's control light, ring 2 swashs to be penetrated, and the 1 repressed state that encircles is called unstable state.Unstable state is ring 1 no-output down, encircles 2 output wavelength λ
IBDirect current light.If remove extraneous control light under the unstable state, the output light of SOA 2 is not sufficient to consume the charge carrier in the SOA 1, and system can get back to ring 1 sharp penetrating again, encircles 2 repressed stable states.
The structure of All Optical Wave Converter comprises a data input as shown in Figure 8, data output and direct current light input end.By preceding described, each grade buffer unit comprises two wavelength shifters, the light buffer memory control sub unit that is used in each grade, i.e. second wavelength shifter, another is used for needing cached data packet to carry out wavelength Conversion to light buffer unit at the corresponding levels, with its wavelength Conversion to λ
IC, i.e. first wavelength shifter.For second wavelength shifter, because wherein every grade of buffer memory control sub unit can only receive a road in descending input or the light buffer unit cached data packet at the corresponding levels, so the descending input of the light buffer unit among Fig. 8 is coupling in light buffer unit cached data packet at the corresponding levels, enters circulator.Direct current light (λ from full light monostable flipflop output
IA/ λ
IB) behind isolator, enter SOA, in SOA, it is λ that the amplitude information of input data is transformed into wavelength by the cross-gain mudulation effect
IAOr λ
IBLight on, export through circulator.Filter, Polarization Controller and polarization beam splitter prism are used for reducing noise.Like this, just to be transformed into wavelength be λ to the amplitude information of input data carry
IAOr λ
IBLight on.For first wavelength shifter, the cached data packet wavelength of exporting from light buffer memory control sub unit that needs is λ
IBIf this moment, packets need continued at light buffer unit buffer memory, the direct current light that then is input in first wavelength shifter is the same with signal light wavelength, can be in SOA phenomenon such as generation interference make data distortion, so need be with the wavelength Conversion of packet to λ
IC, λ
ICSelection make itself and λ
IAAnd λ
IBAll different.So simultaneously, because the cross-gain modulation has logic negate function, input data and dateout are opposite polarity.In conjunction with Fig. 1 and Fig. 6, learn that by above-mentioned principle for each grade light buffer unit, data have experienced odd number time wavelength conversion by descending input input up to up output output; For whole queue-type all-optical buffer, the packet of second input input is opposite with the quantity of the light buffer unit of queue-type all-optical buffer up to the parity of the wavelength Conversion number of times of output experience from entering queue-type all-optical buffer.With the quantity of light buffer unit is that 3 grades queue-type all-optical buffer is an example, the packet of second input, 2 inputs lives through even number time wavelength conversion in output, therefore need not to carry out a wavelength Conversion again and change polarity, is that the queue-type all-optical buffer of even number then need carry out a wavelength Conversion at output and makes the polarity of output signal consistent with input signal for light buffer unit quantity.It should be noted that, the packet why second input is imported is opposite with the quantity of the light buffer unit of queue-type all-optical buffer up to the parity of the wavelength Conversion number of times of output experience from entering queue-type all-optical buffer, be because the input in the queue-type all-optical buffer bottom has a light buffer memory control sub unit, its effect is to be used for judging whether queue-type all-optical buffer has stored full team, if formation is full, then packet loss then can take place in the packet by 2 inputs of second input, if formation less than, upwards output to the descending input of afterbody light buffer unit.Packet by 2 inputs of second input need also promptly carry out a logic negate through a wavelength Conversion through this light buffer memory control sub unit.
The front points out that in this queue-type all-optical buffer, the control signal output ends of i level light buffer unit is connected to the signal input end of i+1 level light buffer unit, can utilize packet itself as control signal, need not outer increase control signal.But the time span of considering control signal should be slightly larger than long data packet, and the company in the packet may make control fails for 0 yard, is necessary control signal is done preliminary treatment, as shown in Figure 1.Pretreated purpose has two: (1) elongates control signal length on time domain; (2) company in the elimination packet is 0 yard.The present invention proposes the scheme of two kinds of control signal preprocessors, a kind of mach zhender (Mach-Zehnder) interferometer that utilizes, and as Fig. 9, another kind utilizes full optical bistability trigger, as Figure 10.First kind of scheme such as Fig. 9 .1, packet is divided into two-way after entering Mach-Zehnder interferometers, is respectively reference arm and time-delay arm, inserts one section fiber delay line in the time-delay arm, and two arms are coupled then.The long L of tentation data bag, the time-delay that the time-delay arm is introduced is that (D＜L), then the long D+L of control signal that obtains after the two paths of data coupling is slightly longer than packet for D.Its effect schematic diagram is shown in Fig. 9 .2.But this scheme can not solve and connect 0 yard problem in the packet.Second kind of scheme such as Figure 10 are input to two control ends of full optical bistability trigger to packet and the later packet of time-delay respectively, make control signal with one tunnel output of the full light device of bistable state.The structure of the full light device of bistable state and full light monostable flipflop noted earlier are in full accord, and just the bias current of two SOA is the same, makes the gain of two rings equal substantially, and two stable states so just can be arranged.Among Figure 10 .1, the control end set 1 of full optical bistability trigger receives packet earlier, and full optical bistability trigger is put stable state 1, exports a direct current light.After packet finished, full optical bistability device remained on stable state 1, continued this direct current light of output.When the delay data bag entered control end set 2, full optical bistability trigger was put stable state 2, and output direct current light stops.The control signal that obtains like this is a square wave, do not contain 0 yard, and its length is slightly larger than data packet length.The long L of tentation data bag, delaying time is D (D is slightly larger than L), then the length of control signal also is D.Its effect schematic diagram is shown in Figure 10 .2.Here need to prove, though packet from the time that second input of whole queue-type all-optical buffer bottom arrives the descending input of smooth buffer units at different levels be different, but the time difference is far smaller than the time-delay that time delay optical fiber is brought, the length that only needs the control signal of increase control signal preprocessor generation, make that when queue-type all-optical buffer second input 2 has the data input control signal of first order light buffer unit output can receive that existence always gets final product in the process of descending input packet at second level light buffer unit.
In sum, the queue-type all-optical buffer based on cascade light buffer unit of the present invention's proposition has following characteristics:
1. directly export for the high packet of priority, not buffer memory. For the low packet of priority, according to having The free of data conflict determines whether to carry out buffer memory.
2. smooth buffer units at different levels can only be simultaneously from the data of descending input or light buffer unit buffer memory at the corresponding levels Road receive data, prevented the aliasing of input light buffer unit data.
3. smooth buffer units at different levels can only be exported from a road of up output or light buffer unit buffer memory at the corresponding levels simultaneously Data, or upper line output, or buffer memory have or not control signal to determine by the control signal input.
4. whole queue-type all-optical buffer is a kind of FIFO, after the queue structure that goes out after entering, the number that deposits in earlier Little according to the bag storage depth, after the packet storage depth that deposits in big.
System complexity only and memory capacity linear, can enlarge very easily memory capacity, and not show The increase system complexity of work.
Claims (7)
1. queue-type all-optical buffer, it is characterized in that, form by the cascade of I level light buffer unit, i=1,2, I, it is a kind of first-in first-out, after the queue-type buffer that goes out after going into, described queue-type all-optical buffer has two inputs and an output, the priority height of first input end (1) wherein, and the priority of second input (2) is low, described first input end (1) is divided into two-way through a coupler: one road input signal is through arriving output behind another coupler, and another road is connected to the signal input end of the 1st grade of described smooth buffer unit, i=1 by the 0th grade of control signal preprocessor, described second input (2) is connected to the descending input of the light buffer memory control sub unit of described queue-type all-optical buffer bottom, wherein:
Described smooth buffer unit i at different levels contains light buffer memory control sub unit, first wavelength shifter and control signal preprocessor, wherein:
Light buffer memory control sub unit contains full light monostable flipflop, wavelength division multiplexer MUX, second wavelength shifter and the demodulation multiplexer DEMUX that connects successively, wherein:
Full light monostable flipflop, signal input end links to each other with the control signal output ends of the described smooth buffer unit of i-1 level,
Wavelength division multiplexer MUX has two inputs, an output: the wavelength of first input end and described full light monostable flipflop is λ
IAThe direct current light output end link to each other, and the wavelength of second input and described full light monostable flipflop is λ
IBThe direct current light output end link to each other, the selection of its medium wavelength makes λ
IAWith λ
IBDifference,
Second wavelength shifter, a data input, a data output and a direct current light input end are arranged, wherein the direct current light input end links to each other with the output of described wavelength division multiplexer MUX, and the descending input of described smooth buffer unit i is coupled with the data output end of first wavelength shifter of described smooth buffer unit i and links to each other with the data input pin of described second wavelength shifter
Demodulation multiplexer DEMUX, its input links to each other with the data output end of described second wavelength shifter, and described demodulation multiplexer DEMUX has two outputs, and one is up output, links to each other with the descending input of the described smooth buffer unit of i-1 level, and output wavelength is λ
IAFlashlight, another output output wavelength is λ
IBFlashlight, be divided into two-way through after the fiber delay time: be connected to control signal output ends behind the control signal preprocessor of the first via by described i level light buffer unit, be sent to the signal input end of the described smooth buffer unit of i+1 level, also promptly in the described full light monostable flipflop in the described smooth buffer memory control sub unit of the described smooth buffer unit of i+1 level, the second tunnel is connected to the data input pin of described first wavelength shifter of described i level buffer unit;
First wavelength shifter has a data input, a data output and a direct current light input end, and wherein to import a wavelength be λ to the direct current light input end
ICDirect current light, λ wherein
ICSelection make λ
ICWith λ
IAAnd λ
IBAll different, the described demodulation multiplexer DEMUX output wavelength of the described smooth buffer memory control sub unit of described i level light buffer unit is λ
IBThe output of flashlight is through being divided into two-way after the fiber delay time, wherein one the tunnel links to each other with the data input pin of described first wavelength shifter, the be coupled data input pin of described second wavelength shifter of the described smooth buffer memory control sub unit that is connected to described i level light buffer unit of the descending input of the data output end of described first wavelength shifter and described i level light buffer unit;
The control signal preprocessor has an input and an output, and the described demodulation multiplexer DEMUX output wavelength of the described smooth buffer memory control sub unit of described i level light buffer unit is λ
IBThe output of flashlight is through being divided into two-way after the fiber delay time, one tunnel input that is connected to described control signal preprocessor wherein, the output of described control signal preprocessor is connected to the signal input end of the described smooth buffer unit of i+1 level as the control signal output ends of described i level light buffer unit, also promptly in the described full light monostable flipflop of the described smooth buffer memory control sub unit of the described smooth buffer unit of i+1 level;
As packet in described i level light buffer unit during buffer memory, can be input to the signal input end of the described smooth buffer unit of i+1 level simultaneously through the control signal that produces behind the control signal preprocessor at the same level by described packet, close its data feedback channel, stop the described smooth buffer unit of i+1 level to the up dateout bag of described i level light buffer unit, prevent that packet is overlapping in the described i level light buffer unit, otherwise, when packet exported described i level light buffer unit to from the described smooth buffer unit of i+1 level is up, described i level light buffer unit did not have packet at this moment.
2. queue-type all-optical buffer according to claim 1, it is characterized in that, when having simultaneously from the first packet packet (1) of described first input end (1) and from the second packet packet (2) of described second input (2), and the packet of former queue-type all-optical buffer in first order light buffer unit is when being packet (0), the described first packet packet (1) couples directly to the straight-through output of output of described queue-type all-optical buffer, the described second packet packet (2) enters the descending input that always goes upward to second level light buffer unit behind the described queue-type all-optical buffer, meanwhile, the described first packet packet (1) also enters the signal input end that the 0th grade of control signal preprocessor is connected to described first order light buffer unit afterwards, described first order light buffer unit has the control signal input, described first order light buffer unit has control signal to output to the signal input end of described second level light buffer unit, the then described second packet packet (2) buffer memory in the light buffer unit of the described second level, not upwards output, described packet packet (0) is buffer memory in described first order light buffer unit, not upwards output; When described queue-type all-optical buffer dateout bag, described packet packet (0) goes out team earlier, goes out team behind the described second packet packet (2).Meet first-in first-out, after the formation characteristics that go out after going into.
3. queue-type all-optical buffer according to claim 1, it is characterized in that, when described first input end (1) has the first packet packet (1), the input of described second input (2) free of data bag, and the packet of former queue-type all-optical buffer in described first order light buffer unit is when being packet (0), the described first packet packet (1) couples directly to the straight-through output of output of described queue-type all-optical buffer, and the signal input end of described first order light buffer unit has the control signal input of the described first packet packet (1) through producing behind described the 0th grade of control signal preprocessor, thereby described packet packet (0) continues buffer memory in described first order light buffer unit.
4. queue-type all-optical buffer according to claim 1, it is characterized in that, when the input of described first input end (1) free of data bag, described second input (2) has packet packet (2) input, and the packet of former queue-type all-optical buffer in first order light buffer unit is when being packet (0), the up output that exports described queue-type all-optical buffer to of described packet packet (0), and the signal input end of described second level light buffer unit has control signal input, makes the described second packet packet (2) buffer memory one-period in the light buffer unit of the described second level.
5. queue-type all-optical buffer according to claim 1, it is characterized in that, when described first input end (1), second input (2) free of data bag whens input all, the packet packet (0) in the then former queue-type all-optical buffer first order light buffer unit outputs to the output of described queue-type all-optical buffer from the up output of described first order light buffer unit.
6. queue-type all-optical buffer according to claim 1 is characterized in that, described control signal preprocessor is made of Mach-Zehnder interferometers or full optical bistability trigger.
7. queue-type all-optical buffer according to claim 1, it is characterized in that, when the storage depth of described queue-type all-optical buffer is an even number, be the number of described smooth buffer unit when being even number, carry out a logic negate again from the packets need of the up output output of described first order light buffer unit.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102801613A (en) * | 2012-07-11 | 2012-11-28 | 武汉邮电科学研究院 | Optical stacking device and optical queue device based on same |
| WO2015100838A1 (en) * | 2013-12-31 | 2015-07-09 | 华为技术有限公司 | Annular optical buffer and optical signal storage and reading method |
| CN105099945A (en) * | 2014-04-24 | 2015-11-25 | 比亚迪股份有限公司 | CAN network system and packet transmission control method |
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| CN101350672B (en) * | 2008-09-05 | 2011-03-30 | 清华大学 | Stack type whole optical caching device |
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| CN102801613A (en) * | 2012-07-11 | 2012-11-28 | 武汉邮电科学研究院 | Optical stacking device and optical queue device based on same |
| CN102801613B (en) * | 2012-07-11 | 2015-04-08 | 武汉邮电科学研究院 | Optical stacking device and optical queue device based on same |
| WO2015100838A1 (en) * | 2013-12-31 | 2015-07-09 | 华为技术有限公司 | Annular optical buffer and optical signal storage and reading method |
| US9709744B2 (en) | 2013-12-31 | 2017-07-18 | Huawei Technologies Co., Ltd. | Annular optical shifter and method for shifting optical signal |
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| CN105099945A (en) * | 2014-04-24 | 2015-11-25 | 比亚迪股份有限公司 | CAN network system and packet transmission control method |
| CN110661731A (en) * | 2019-09-26 | 2020-01-07 | 光大兴陇信托有限责任公司 | Message processing method and device |
| CN112423163A (en) * | 2020-10-12 | 2021-02-26 | 江西师范大学 | Optical buffer based on coherent feedback |
| CN112423163B (en) * | 2020-10-12 | 2023-03-14 | 江西师范大学 | Optical buffer based on coherent feedback |
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